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    SURFACE TREATMENT STRUCTURE OF CIRCUIT PATTERN
    1.
    发明申请
    SURFACE TREATMENT STRUCTURE OF CIRCUIT PATTERN 审中-公开
    电路图形表面处理结构

    公开(公告)号：US20130233602A1

    公开(公告)日：2013-09-12

    申请号：US13416158

    申请日：2012-03-09

    Applicant: Ting-Hao Lin ,  Yu-Hui Wu

    Inventor： Ting-Hao Lin ,  Yu-Hui Wu

    IPC: H05K1/09

    CPC classification number: H05K3/243 ,  H01L2224/13111 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/81444 ,  H01L2224/85444 ,  H05K3/24 ,  H05K2201/0341 ,  H01L2924/00014

    Abstract: A surface treatment structure formed on a circuit pattern on a printed circuit board is provided, which includes a first gold layer, a palladium layer, and a second gold layer stacked from bottom to top, respectively, or includes a palladium layer, and a second gold layer stacked from bottom to top, respectively. The palladium layer is used to prevent the diffusion of the copper ions from the circuit pattern. Only a thin surface treatment structure of the circuit pattern of the present invention is required to achieve excellent wire bonding, so that the overall thickness is reduced, and the manufacture cost is also reduced. Furthermore, the uniformness of palladium is better than that of nickel, and thereby the surface treatment structure of the circuit pattern of the present invention is suitably used for manufacturing the fine-line circuits, thereby having a wider industrial applicability.

    Abstract translation: 提供了形成在印刷电路板上的电路图案上的表面处理结构，其包括分别从底部至顶部堆叠的第一金层，钯层和第二金层，或包括钯层，第二金层 金层分别从底部到顶部堆叠。 钯层用于防止铜离子从电路图案扩散。 需要本发明的电路图形的薄的表面处理结构来实现优良的引线接合，从而减小总体厚度，并且制造成本也降低。 此外，钯的均匀性优于镍，因此本发明的电路图案的表面处理结构适用于制造细线电路，从而具有更广的工业实用性。

    Semiconductor Load Board
    2.
    发明申请
    Semiconductor Load Board 审中-公开
    半导体负载板

    公开(公告)号：US20120228011A1

    公开(公告)日：2012-09-13

    申请号：US13043462

    申请日：2011-03-09

    Applicant: Chien-Wei Chang ,  Ting-Hao Lin ,  Ya-Hsiang Chen

    Inventor： Chien-Wei Chang ,  Ting-Hao Lin ,  Ya-Hsiang Chen

    IPC: H05K1/09 ,  H05K1/00

    CPC classification number: H01L23/49816 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05567 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/13076 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/014 ,  H05K3/4007 ,  H05K2201/0367 ,  H01L2224/05552

    Abstract: Disclosed is a semiconductor load board, including a substrate, a plurality of connection pads, a patterned circuit layer, a dielectric layer, a plurality of solder pads, and a plurality of solders. The connection pads and the patterned circuit layer are located on the substrate. The dielectric layer is formed on the substrate, the connection pads and the patterned circuit layer, and has a plurality of openings corresponding to the plurality of connection pads. The solder pads are formed in the openings, and the width of the solder pads is smaller than or equals to the maximum width of the openings of the dielectric layer, and a protruding portion which has a width smaller than the minimum width of the openings of the dielectric layer can also be formed, such that the problems of short-circuit failure and electrical interference can be reduced.

    Abstract translation: 公开了一种半导体负载板，包括基板，多个连接焊盘，图案化电路层，电介质层，多个焊盘和多个焊料。 连接焊盘和图案化电路层位于衬底上。 介电层形成在基板上，连接焊盘和图案化电路层上，并且具有对应于多个连接焊盘的多个开口。 焊盘形成在开口中，并且焊盘的宽度小于或等于电介质层的开口的最大宽度，并且宽度小于开口的最小宽度的突出部分 还可以形成电介质层，从而可以减少短路故障和电气干扰的问题。

    Method of fabricating board having high density core layer and structure thereof
    4.
    发明授权
    Method of fabricating board having high density core layer and structure thereof 有权
    具有高密度芯层的板的制造方法及其结构

    公开(公告)号：US07875809B2

    公开(公告)日：2011-01-25

    申请号：US11766194

    申请日：2007-06-21

    Applicant: Chien-Wei Chang ,  Ting-Hao Lin ,  Jen-Fang Chang ,  Yu-Te Lu ,  Chia-Chi Lo

    Inventor： Chien-Wei Chang ,  Ting-Hao Lin ,  Jen-Fang Chang ,  Yu-Te Lu ,  Chia-Chi Lo

    IPC: H05K1/00

    CPC classification number: H05K3/4602 ,  H05K3/108 ,  H05K3/427 ,  H05K2201/0347 ,  H05K2201/09536 ,  H05K2201/0959 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49165

    Abstract: A circuit board includes a core layer substrate having a plated through hole filled with a dielectric material. The plated through hole has a sidewall coated with an inner electroless copper layer, and an electroplated metal layer plated on the inner electroless copper layer before the plated through hole is filled with the dielectric material. The outer portion of the filled plated through hole is thicker than the center portion and tapered toward the center portion to form a depressed surface on the filled plated through hole. The core layer substrate is covered with a patterned electroless copper layer and a patterned electroplated copper layer that connect with the inner electroless copper layer and electroplated metal layer of the plated through hole. The patterned electroplated copper layer forms a flat copper pad above the plated through hole.

    Abstract translation: 电路板包括具有填充有介电材料的电镀通孔的芯层基板。 电镀通孔具有涂覆有内部化学镀铜层的侧壁和在电镀通孔填充有电介质材料之前镀在内部化学镀铜层上的电镀金属层。 填充电镀通孔的外部比中心部分厚，并且朝向中心部分逐渐变细，以在填充的电镀通孔上形成凹陷表面。 芯层衬底被覆有图案化的无电铜层和与电镀通孔的内部化学镀铜层和电镀金属层连接的图案化电镀铜层。 图案化的电镀铜层在电镀通孔上方形成平坦的铜焊盘。

    Method For Fabricating Buried Capacitor Structure
    5.
    发明申请
    Method For Fabricating Buried Capacitor Structure 有权
    制造掩埋电容器结构的方法

    公开(公告)号：US20100307666A1

    公开(公告)日：2010-12-09

    申请号：US12479811

    申请日：2009-06-07

    Applicant: Chien-Wei Chang ,  Ting-Hao Lin ,  Ya-Hsiang Chen ,  Yu-Te Lu

    Inventor： Chien-Wei Chang ,  Ting-Hao Lin ,  Ya-Hsiang Chen ,  Yu-Te Lu

    IPC: B32B37/00

    CPC classification number: B32B37/02 ,  B32B38/06 ,  B32B2038/047 ,  B32B2457/08 ,  B32B2457/16 ,  H01G4/236 ,  H01G4/33 ,  H05K1/162 ,  H05K3/4602 ,  H05K2201/09236 ,  H05K2201/09509 ,  H05K2203/1461

    Abstract: A method for fabricating a buried capacitor structure includes: laminating a first dielectric layer having a capacitor embedded therein with a second dielectric layer to bury the capacitor therebetween; forming a first circuit pattern on a first metal layer of the first dielectric layer and a second circuit pattern on a second metal layer of the second dielectric layer; depositing a first insulating layer and a second insulating layer on the first metal layer and the second metal layer, respectively; electrically connecting a positive electrode end and a negative electrode end of the capacitor to the second metal layer by a positive through-hole and a negative through-hole, thereby manufacturing the buried capacitor structure.

    Abstract translation: 一种埋入式电容器结构的制造方法，其特征在于：将具有嵌入其中的电容器的第一电介质层与第二电介质层层叠， 在所述第一介电层的第一金属层上形成第一电路图案，在所述第二介电层的第二金属层上形成第二电路图案; 分别在第一金属层和第二金属层上沉积第一绝缘层和第二绝缘层; 通过正通孔和负通孔将电容器的正极端子和负极端子电连接到第二金属层，从而制造埋入式电容器结构。

    Non-Plating Line Plating Method Using Current Transmitted From Ball Side
    6.
    发明申请
    Non-Plating Line Plating Method Using Current Transmitted From Ball Side 审中-公开
    使用从球侧传输的电流的非电镀线电镀方法

    公开(公告)号：US20100075497A1

    公开(公告)日：2010-03-25

    申请号：US12236493

    申请日：2008-09-23

    Applicant: Chien-Wei Chang ,  Ting-Hao Lin ,  Yu-Te Lu

    Inventor： Chien-Wei Chang ,  Ting-Hao Lin ,  Yu-Te Lu

    IPC: H01L21/44 ,  H01L21/288

    CPC classification number: H05K3/242 ,  H05K3/42 ,  H05K2201/0352 ,  H05K2203/1476 ,  H05K2203/1581

    Abstract: A non-plating line (NPL) plating method is provided. The NPL plating method is featured in that at first it forms a circuit layer on a bump side only, and therefore a plating current can be transmitted via a plating metal layer on a ball side to the circuit layer (enclosed by an insulation layer, e.g., a solder resist or a photoresist) on the bump side, and thus forming a protection layer, e.g., plating gold, on the plating metal layer on the circuit layer and the ball side. In such a way, the plating gold is formed after the insulation layer, so that there won't be any plating gold existed beneath the insulation layer of the bump side (connected with dies). Hence, the insulation layer can be prevented from dropping off from the protection layer, i.e., the plating gold, and thus the reliability of the products can be improved.

    Abstract translation: 提供非电镀线（NPL）电镀方法。 NPL镀覆方法的特征在于，它首先仅在凸块侧形成电路层，因此电镀电流可以通过球侧的电镀金属层传输到电路层（由绝缘层包围，例如 ，阻焊剂或光致抗蚀剂），从而在电路层和球侧的电镀金属层上形成保护层，例如镀金。 以这种方式，在绝缘层之后形成电镀金，使得在凸起侧（与模具连接）的绝缘层下方不存在镀金。 因此，可以防止绝缘层从保护层即电镀金脱落，从而可以提高产品的可靠性。

    COMPOSITE CIRCUIT BOARD AND METHOD FOR MANUFACTURING THE SAME
    8.
    发明申请
    COMPOSITE CIRCUIT BOARD AND METHOD FOR MANUFACTURING THE SAME 失效
    复合电路板及其制造方法

    公开(公告)号：US20070144768A1

    公开(公告)日：2007-06-28

    申请号：US11319998

    申请日：2005-12-27

    Applicant: Ting-Hao Lin ,  Chung-Yuan Chen

    Inventor： Ting-Hao Lin ,  Chung-Yuan Chen

    IPC: H05K1/03

    CPC classification number: H05K3/4691 ,  H05K3/0052 ,  H05K3/0097 ,  H05K3/4688 ,  H05K2203/065 ,  H05K2203/167 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49155

    Abstract: A composite circuit board comprises multiple soft panels evenly mounted on a rigid panel. The soft panels are positioned on the rigid panel in proper alignment via locating pins on the rigid panel and corresponding holes in the soft panels. The soft panels are securely bonded to the rigid panel to form the composite circuit boards. The smaller size of the soft panels minimizes the alignment problems caused by the different heat expansion rates of the soft panel and the rigid panel.

    Abstract translation: 复合电路板包括均匀地安装在刚性面板上的多个软面板。 柔性面板通过刚性面板上的定位销和软面板中的相应孔定位在刚性面板上，以适当对准。 软面板牢固地结合到刚性面板上以形成复合电路板。 较小尺寸的软面板使由柔性面板和刚性面板的不同热膨胀率引起的对准问题最小化。

    Solid tape automated bonding packaging method
    10.
    发明授权
    Solid tape automated bonding packaging method 失效
    实心胶带自动粘接包装方法

    公开(公告)号：US5763294A

    公开(公告)日：1998-06-09

    申请号：US856966

    申请日：1997-05-15

    Applicant: Ting-Hao Lin

    Inventor： Ting-Hao Lin

    IPC: H01L21/60

    CPC classification number: H01L24/86 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/181

    Abstract: A solid tape automated bonding method includes steps of: applying a pattern of a first dry film on a first portion of a copper plate; forming wiring; forming bumps; removing dry film and exposing the wiring and the bumps; selectively laminating an insulator layer onto portions of the exposed copper plate and the wiring; laminating a metal layer on the insulator layer; applying glue on the metal layer, the bumps, and respective exposed portions of the wiring and the copper plate; etching the copper plate thus exposing one side of the wiring as ball pads and exposing one side of the insulator layer; coating solder resist on the exposed bottom side of the insulator layer; removing the glue; attaching a die against the bumps; applying mold compound onto the die so as to fix the die in place; and attaching solder balls onto the ball pads. This method provides relatively high density of wiring and simplification in manufacturing.

    Abstract translation: 固体胶带自动接合方法包括以下步骤：将第一干膜的图案施加在铜板的第一部分上; 形成布线 形成凸块; 去除干膜并暴露布线和凸块; 选择性地将绝缘体层压到暴露的铜板和布线的部分上; 在绝缘体层上层压金属层; 在金属层，凸块以及布线和铜板的各自的暴露部分上施加胶水; 蚀刻铜板，从而将布线的一侧作为球垫露出并暴露绝缘体层的一侧; 在绝缘体层的暴露的底侧涂覆阻焊剂; 去除胶水; 将模具贴靠在凸起上; 将模具化合物涂覆在模具上，以将模具固定就位; 并将焊球附着到球垫上。 该方法提供相对较高的布线密度和制造简化。

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