公开(公告)号：US20240314932A1

公开(公告)日：2024-09-19

申请号：US18136358

申请日：2023-04-19

Applicant: UNIMICRON TECHNOLOGY CORP.

Inventor： Chen-An TSAI

IPC: H05K1/16 ,  H01F17/00 ,  H01F41/04 ,  H05K1/11 ,  H05K3/46

CPC classification number: H05K1/165 ,  H01F17/0013 ,  H01F41/041 ,  H05K1/115 ,  H05K3/4644 ,  H05K2201/086 ,  H05K2201/09527 ,  H05K2201/09563 ,  H05K2201/1003

Abstract: The present invention includes an aluminum board, an electromagnet core, and a coil. The aluminum board includes a first surface, a second surface opposite to the first surface, and multiple through vias in communication with the first surface and the second surface. The electromagnet core is mounted on the first surface, and the through vias are located on two opposite sides of the electromagnet core. The coil is mounted through the through vias to wrap around the electromagnet core. An inside wall of each of the through vias forms an anodic aluminum oxide (AAO) by an anodizing process. The present invention is able to decrease via size of a conductive through via of a vertically embedded inductor. This allows through vias to be more densely formed on a board, and thus increases an amount of the coil wrapped around the electromagnetic core and increases inductance of the inductor.

公开(公告)号：US20180033719A1

公开(公告)日：2018-02-01

申请号：US15725144

申请日：2017-10-04

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Li-Chuan TSAI ,  Chih-Cheng LEE

IPC: H01L23/498 ,  H01L21/48 ,  H05K1/02 ,  H05K3/36 ,  H05K3/22 ,  H05K3/00 ,  H05K1/18 ,  H05K1/11 ,  H05K3/40 ,  H01L23/00

CPC classification number: H01L23/49838 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/17 ,  H01L2224/16227 ,  H01L2924/15153 ,  H01L2924/15313 ,  H01L2924/19105 ,  H05K1/0266 ,  H05K1/0298 ,  H05K1/111 ,  H05K1/115 ,  H05K1/181 ,  H05K1/183 ,  H05K3/0017 ,  H05K3/0026 ,  H05K3/0047 ,  H05K3/22 ,  H05K3/36 ,  H05K3/40 ,  H05K3/4682 ,  H05K3/4697 ,  H05K2201/0158 ,  H05K2201/09472 ,  H05K2201/09527 ,  H05K2201/10204 ,  H05K2203/166 ,  Y02P70/611

Abstract: A semiconductor substrate includes: (1) a first dielectric structure having a first surface and a second surface opposite the first surface; (2) a second dielectric structure having a third surface and a fourth surface opposite the third surface, wherein the fourth surface faces the first surface, the second dielectric structure defining a through hole extending from the third surface to the fourth surface, wherein a cavity is defined by the through hole and the first dielectric structure; (3) a first patterned conductive layer, disposed on the first surface of the first dielectric structure; and (4) a second patterned conductive layer, disposed on and contacting the second surface of the first dielectric structure and including at least one conductive trace, wherein the first dielectric structure defines at least one opening, and a periphery of the opening corresponds to a periphery of the through hole of the second dielectric structure.

公开(公告)号：US20170156214A1

公开(公告)日：2017-06-01

申请号：US15430869

申请日：2017-02-13

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Shigeru TAGO ,  Daisuke TSURUGA

IPC: H05K1/18 ,  H05K1/02 ,  H05K3/46 ,  H05K1/11

CPC classification number: H05K1/185 ,  H01L2224/04105 ,  H01L2224/19 ,  H01L2224/73267 ,  H01L2224/92244 ,  H05K1/0243 ,  H05K1/028 ,  H05K1/115 ,  H05K1/186 ,  H05K3/4617 ,  H05K3/4644 ,  H05K3/4691 ,  H05K2201/0129 ,  H05K2201/05 ,  H05K2201/09527 ,  H05K2201/10515 ,  H05K2203/0285 ,  H05K2203/063

Abstract: A component-embedded substrate includes first to sixth thermoplastic resin bases, a first electronic component in the second thermoplastic resin base and including a first terminal, and a second electronic component in the fifth thermoplastic resin base and including a second terminal. The first terminal faces the second electronic component in a stacking direction. The second terminal faces the first electronic component in the stacking direction. A first planar conductor to which the first terminal is directly bonded is provided on the third thermoplastic resin base. An interlayer connection conductor to which the second terminal is directly bonded and in communication with the first planar conductor is provided in or on the fourth thermoplastic resin base.

公开(公告)号：US20160307875A1

公开(公告)日：2016-10-20

申请号：US15191774

申请日：2016-06-24

Applicant: Renesas Electronics Corporation

Inventor： Yoichiro KURITA ,  Masaya KAWANO ,  Koji SOEJIMA

IPC: H01L25/065 ,  H01L25/00

CPC classification number: H01L25/50 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/13 ,  H01L23/3121 ,  H01L23/49816 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L24/02 ,  H01L24/16 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/16 ,  H01L25/18 ,  H01L2221/68345 ,  H01L2221/68372 ,  H01L2224/02319 ,  H01L2224/02331 ,  H01L2224/02333 ,  H01L2224/02372 ,  H01L2224/02373 ,  H01L2224/02379 ,  H01L2224/02381 ,  H01L2224/16137 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16238 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/83005 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L2225/06555 ,  H01L2225/06582 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/18161 ,  H01L2924/19015 ,  H01L2924/19041 ,  H01L2924/19105 ,  H05K3/0058 ,  H05K3/284 ,  H05K3/4682 ,  H05K2201/0195 ,  H05K2201/09527 ,  H05K2201/096 ,  H05K2201/09972 ,  H05K2203/016 ,  H05K2203/0733 ,  H05K2203/1469 ,  H01L2924/00 ,  H01L2224/0401

Abstract: In a conventional electronic device and a method of manufacturing the same, reduction in cost of the electronic device is hindered because resin used in an interconnect layer on the solder ball side is limited. The electronic device includes an interconnect layer (a first interconnect layer) and an interconnect layer (a second interconnect layer). The second interconnect layer is formed on the undersurface of the first interconnect layer. The second interconnect layer is larger in area seen from the top than the first interconnect layer and is extended to the outside from the first interconnect layer.

公开(公告)号：US09408310B2

公开(公告)日：2016-08-02

申请号：US13857167

申请日：2013-04-05

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Shunsuke Chisaka

IPC: H05K1/03 ,  H05K1/18 ,  H05K3/32 ,  H05K3/46 ,  H05K3/40

CPC classification number: H05K1/185 ,  H05K1/182 ,  H05K1/186 ,  H05K3/32 ,  H05K3/4069 ,  H05K3/4617 ,  H05K3/4632 ,  H05K2201/09527 ,  H05K2201/09781 ,  H05K2203/063 ,  Y10T29/49139

Abstract: A substrate includes a built-in component that suppresses resin flow occurring in the case of thermocompression bonding in a region where vias and wiring conductors are provided and that reduces the occurrence of via defects and wiring-conductor defects. The resin flow occurring in an outer side portion of a frame-shaped electrode is suppressed in the case of thermocompression bonding by encircling the periphery of a built-in component with the frame-shaped electrode. Because of this structure, the occurrence of defects in vias and wiring conductors arranged in an outer side portion of the frame-shaped electrode may be reduced.

Abstract translation: 基板包括抑制在设置有通孔和布线导体的区域中的热压接时发生的树脂流动并且减少了通孔缺陷和布线导体缺陷的发生的内置部件。 在通过用框状电极环绕内置部件的周围的热压接的情况下，在框状电极的外侧部分发生的树脂流被抑制。 由于这种结构，可以减少布置在框架状电极的外侧部分中的通孔和布线导体中的缺陷的发生。

公开(公告)号：US20150053462A1

公开(公告)日：2015-02-26

申请号：US14062912

申请日：2013-10-25

Applicant: Unimicron Technology Corp.

Inventor： Ming-Hao Wu ,  Wei-Ming Cheng ,  Hung-Lin Chang

IPC: H05K1/02

CPC classification number: H05K1/0206 ,  H01L21/568 ,  H01L24/19 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/73259 ,  H05K1/0203 ,  H05K1/0207 ,  H05K1/16 ,  H05K1/185 ,  H05K3/4602 ,  H05K2201/0187 ,  H05K2201/0195 ,  H05K2201/09527 ,  H05K2201/10219

Abstract: A wiring board structure adapted to carry a heat generating component is provided. The wiring board structure includes a core layer, an active cooler, a dielectric layer and a plurality of conductive vias. The core layer has a cavity penetrating through the core layer. The active cooler includes a cold surface and a hot surface. The active cooler is disposed in the cavity. The dielectric layer covers the core layer and fills a gap between the active cooler and the cavity. The heat-generating component is disposed on an outer surface of the dielectric layer. The conductive vias are disposed in the dielectric layer and connecting the cold surface and the outer surface to connect the heat-generating component and the active cooler. A wiring board structure having an active cooling via is also provided.

Abstract translation: 提供适于承载发热部件的布线板结构。 布线板结构包括芯层，有源冷却器，电介质层和多个导电通孔。 芯层具有穿透芯层的腔体。 主动冷却器包括冷表面和热表面。 有源冷却器设置在空腔中。 电介质层覆盖芯层并填充主动式冷却器和空腔之间的间隙。 发热部件设置在电介质层的外表面上。 导电通孔设置在电介质层中，并连接冷表面和外表面，以连接发热部件和主动冷却器。 还提供了具有主动冷却通路的布线板结构。

公开(公告)号：US20150027762A1

公开(公告)日：2015-01-29

申请号：US14444144

申请日：2014-07-28

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Yong Sang SHIN ,  Joo Sung PARK

IPC: H05K1/02 ,  H05K1/11 ,  H05K1/09

CPC classification number: H05K1/0271 ,  H05K1/112 ,  H05K1/113 ,  H05K3/4644 ,  H05K2201/09527 ,  H05K2201/09627 ,  H05K2201/09781 ,  H05K2201/0979

Abstract: Disclosed herein is a printed circuit board capable of increasing reliability by decreasing stress between an insulating layer and solder balls. The printed circuit board includes: an insulating layer part including circuit patterns and connecting lands having solder balls seated thereon and including a plurality of insulating layers; a plurality of connecting pads and non-connecting pads formed at the insulating layer part; and a plurality of reinforcing vias formed in the non-connecting pads and reinforcing a close adhesion state between the insulating layer part and the non-connecting pads.

Abstract translation: 这里公开了能够通过降低绝缘层和焊球之间的应力来提高可靠性的印刷电路板。 印刷电路板包括：包括电路图案的绝缘层部分和其上安装有焊球并且包括多个绝缘层的连接焊盘; 多个连接焊盘和形成在绝缘层部分的非连接焊盘; 以及形成在所述非连接焊盘中的多个加强通孔，并且在所述绝缘层部分和所述非连接焊盘之间增强紧密粘合状态。

公开(公告)号：US08935850B2

公开(公告)日：2015-01-20

申请号：US13776024

申请日：2013-02-25

Applicant: Ibiden Co., Ltd.

Inventor： Masahiro Kaneko ,  Satoru Kose ,  Hirokazu Higashi

IPC: H05K3/02 ,  H05K3/10 ,  H05K1/11 ,  H01L21/683 ,  H01L25/065 ,  H01L23/498 ,  H01L23/00 ,  H05K3/38 ,  H05K3/00

CPC classification number: H05K3/42 ,  H01L21/6835 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49866 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L2221/68345 ,  H01L2224/32057 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/484 ,  H01L2224/48599 ,  H01L2224/48644 ,  H01L2224/73265 ,  H01L2224/83385 ,  H01L2224/85001 ,  H01L2224/85385 ,  H01L2224/85444 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3025 ,  H05K1/0313 ,  H05K1/113 ,  H05K1/115 ,  H05K3/007 ,  H05K3/108 ,  H05K3/22 ,  H05K3/388 ,  H05K2201/0344 ,  H05K2201/09509 ,  H05K2201/09527 ,  H05K2201/09563 ,  H05K2203/072 ,  H05K2203/1377 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165 ,  H01L2924/00012 ,  H01L2924/00011 ,  H01L2924/00 ,  H01L2224/05599

Abstract: A method for manufacturing a printed wiring board includes forming a removable layer on a support substrate, forming an interlayer resin insulation layer on the removable layer, forming a penetrating hole in the interlayer resin insulation layer, forming a first conductive layer on the interlayer resin insulation layer and on a side wall of the penetrating hole, forming a conductive circuit on the interlayer resin insulation layer, forming a via conductor in the penetrating hole, removing the support substrate from the interlayer resin insulation layer by using the removable layer, forming a protruding portion of the via conductor protruding from a surface of the interlayer resin insulation layer, and forming a surface-treatment coating on a surface of the protruding portion of the via conductor.

Abstract translation: 一种制造印刷电路板的方法，包括在支撑基板上形成可移除层，在可移除层上形成层间树脂绝缘层，在层间树脂绝缘层中形成贯通孔，在层间树脂绝缘层上形成第一导电层 在所述贯通孔的侧壁上形成导电电路，在所述层间树脂绝缘层上形成导通电路，在所述贯通孔中形成通路导体，使用所述可移除层从所述层间树脂绝缘层除去所述支撑基板， 所述通孔导体的一部分从所述层间树脂绝缘层的表面突出，并且在所述通孔导体的所述突出部分的表面上形成表面处理涂层。

公开(公告)号：US08685796B2

公开(公告)日：2014-04-01

申请号：US11856730

申请日：2007-09-18

Applicant: Yoichiro Kurita ,  Koji Soejima ,  Masaya Kawano

Inventor： Yoichiro Kurita ,  Koji Soejima ,  Masaya Kawano

IPC: H01L21/44

CPC classification number: H01L23/3128 ,  H01L21/4857 ,  H01L21/6835 ,  H01L23/3135 ,  H01L23/5389 ,  H01L25/0652 ,  H01L25/18 ,  H01L2221/68345 ,  H01L2224/0554 ,  H01L2224/05573 ,  H01L2224/13025 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/18161 ,  H01L2924/19041 ,  H01L2924/19105 ,  H05K3/0058 ,  H05K3/284 ,  H05K3/4682 ,  H05K2201/0195 ,  H05K2201/09527 ,  H05K2201/09972 ,  H05K2203/016 ,  H05K2203/1469 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: The electronic device includes a first interconnect layer and a second interconnect layer. The second interconnect layer is provided on the lower surface of the first interconnect layer. The first interconnect layer includes a via plug (first conductive plug). An end face of the via plug on the side of the second interconnect layer is smaller in area than the opposite end face. The via plug is exposed on the surface of the first interconnect layer facing the second interconnect layer. An insulating resin forming the first interconnect layer is higher in thermal decomposition temperature than an insulating resin forming the second interconnect layer.

Abstract translation: 电子设备包括第一互连层和第二互连层。 第二互连层设置在第一互连层的下表面上。 第一互连层包括通孔插头（第一导电插头）。 通孔塞在第二互连层一侧的端面的面积小于相对端面。 通孔插头暴露在面向第二互连层的第一互连层的表面上。 形成第一互连层的绝缘树脂的热分解温度高于形成第二互连层的绝缘树脂。

公开(公告)号：US08618424B2

公开(公告)日：2013-12-31

申请号：US12969961

申请日：2010-12-16

Applicant: Tomoko Yamada

Inventor： Tomoko Yamada

IPC: H05K1/11

CPC classification number: H05K3/4652 ,  H05K3/421 ,  H05K2201/09527 ,  H05K2201/096

Abstract: The multilayer wiring substrate includes: a first insulating layer comprising a first surface and a second surface opposite to the first surface; a second insulating layer on the first surface of the first insulating layer; a first wiring pattern on the second surface of the first insulating layer; a second wiring pattern on a surface of the second insulating layer; a first via formed through the first insulating layer; a second via formed through the second insulating layer; and a third wiring pattern formed on the first surface of the first insulating layer and embedded in the second insulating layer, the third wiring pattern having a hole therethrough. A diameter of the hole is smaller than each diameter of the first and second vias. The first via and the second via are connected to each other through a metal filled in the hole of the third wiring pattern.

Abstract translation: 多层布线基板包括：第一绝缘层，包括第一表面和与第一表面相对的第二表面; 在所述第一绝缘层的所述第一表面上的第二绝缘层; 在第一绝缘层的第二表面上的第一布线图案; 在所述第二绝缘层的表面上的第二布线图案; 通过所述第一绝缘层形成的第一通孔; 通过第二绝缘层形成的第二通孔; 以及形成在第一绝缘层的第一表面上并嵌入第二绝缘层中的第三布线图案，第三布线图案具有穿过其的孔。 孔的直径小于第一和第二通孔的每个直径。 第一通孔和第二通孔通过填充在第三布线图案的孔中的金属彼此连接。