公开(公告)号：US12114429B2

公开(公告)日：2024-10-08

申请号：US17770396

申请日：2020-09-07

Applicant: AUTONETWORKS TECHNOLOGIES, LTD. ,  SUMITOMO WIRING SYSTEMS, LTD. ,  SUMITOMO ELECTRIC INDUSTRIES, LTD. ,  SUMITOMO ELECTRIC PRINTED CIRCUITS, INC.

Inventor： Hideo Takahashi ,  Shinichi Takase ,  Hiroki Shimoda ,  Tsutomu Kitajima ,  Yoshiro Adachi ,  Yuuki Oohashi ,  Manabu Sudou

IPC: H05K1/18 ,  H05K1/11

CPC classification number: H05K1/189 ,  H05K1/115 ,  H05K2201/09281 ,  H05K2201/09427 ,  H05K2201/09854

Abstract: A flexible printed circuit board including a terminal includes a flexible printed circuit board that includes an electrically conductive line and the terminal soldered to the flexible printed circuit board. The flexible printed circuit board includes a land and a soldering restricting section. The land is electrically connected to the electrically conductive line and has a metal surface and is soldered to the terminal. The soldering restricting section has a non-metal surface and is not soldered to the terminal. The terminal includes an overlapping section and a protrusion section. The overlapping section overlaps the land and is soldered to the land and includes a removed section that is formed in such a manner that a portion is partially removed in a predefined area. The protruding section is continuous from the overlapping section and protrudes to an area that does not overlap the flexible printed circuit board.

公开(公告)号：US20240244749A1

公开(公告)日：2024-07-18

申请号：US18414732

申请日：2024-01-17

Applicant: QUAN MEI TECHNOLOGY CO., LTD.

Inventor： Ching-Ming FANG

IPC: H05K1/11 ,  H01R12/58 ,  H01R43/02 ,  H05K3/00 ,  H05K3/42

CPC classification number: H05K1/115 ,  H01R12/58 ,  H01R43/0256 ,  H05K3/0047 ,  H05K3/423 ,  H05K2201/09854 ,  H05K2203/0723

Abstract: A circuit board includes a substrate having opposite upper and lower surfaces, and an insertion hole extending through the upper and lower surfaces and having an expansion hole portion and an insertion hole portion connected to and communicating with each other. The insertion hole has a maximum width measured from one end of the insertion hole portion passing radially through the centers of the insertion hole portion and the expansion hole portion to one end of the expansion hole portion that is radially opposite to the one end of the insertion hole portion. The maximum width is greater than a hole diameter of the insertion hole portion, while the hole diameter of the insertion hole portion is greater than a hole diameter of the expansion hole portion. An electronic device having the circuit board and a method of manufacturing the same are also disclosed.

公开(公告)号：US12022613B2

公开(公告)日：2024-06-25

申请号：US17747653

申请日：2022-05-18

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Yong Wan Ji ,  Jin Uk Lee ,  Eun Sun Kim ,  Young Hun You

IPC: H05K1/11 ,  B32B15/00 ,  H05K1/02

CPC classification number: H05K1/115 ,  B32B15/00 ,  H05K1/0298 ,  H05K1/11 ,  H05K2201/09854

Abstract: A printed circuit board includes: a first insulating layer having a recess portion in one surface of the first insulating layer; a first circuit pattern embedded in the first insulating layer and being in contact with a lower surface of the recess portion; a second insulating layer disposed on the one surface of the first insulating layer to be disposed in at least a portion of the recess portion; and a via penetrating through at least a portion of the second insulating layer, disposed in the recess portion, and connected to the first circuit pattern.

公开(公告)号：US11812546B2

公开(公告)日：2023-11-07

申请号：US17783094

申请日：2021-05-10

Applicant: SUMITOMO ELECTRIC PRINTED CIRCUITS, INC. ,  SUMITOMO ELECTRIC INDUSTRIES, LTD.

Inventor： Koji Nitta ,  Takafumi Uemiya ,  Suguru Yamagishi ,  Shigeki Shimada ,  Hiroshi Ueda ,  Satoshi Kiya

IPC: H05K1/02

CPC classification number: H05K1/0242 ,  H05K1/024 ,  H05K2201/0715 ,  H05K2201/09609 ,  H05K2201/09854

Abstract: A high-frequency circuit includes a first dielectric layer, a circuit layer, a second dielectric layer arranged in this order, the circuit layer includes a transmission line of a high-frequency signal and a ground pattern disposed around the transmission line. An electromagnetic wave shield is disposed in the first dielectric layer and the second dielectric layer around the transmission line. The electromagnetic wave shield includes a first ground electric conductor formed on an inner surface of at least one first hole formed to extend through the first dielectric layer without extending through the ground pattern, and a second ground electric conductor formed on an inner surface of at least one second hole formed to extend through the second dielectric layer without extending through the ground pattern. The first ground electric conductor and the second ground electric conductor are each electrically connected to the ground pattern.

公开(公告)号：US11744022B2

公开(公告)日：2023-08-29

申请号：US17536429

申请日：2021-11-29

Applicant: Kyocera AVX Components (San Diego), Inc.

Inventor： Seung Hyuk Choi ,  Hyun Jun Hong ,  Tae Wook Kim ,  Cheong Ho Ryu ,  Young Sang Kim ,  Sung Jun Kim

IPC: H05K3/46 ,  H05K3/00 ,  H05K3/18 ,  H05K3/28 ,  H05K3/42

CPC classification number: H05K3/0026 ,  H05K3/0014 ,  H05K3/185 ,  H05K3/188 ,  H05K3/28 ,  H05K3/423 ,  H05K3/4644 ,  H05K3/4652 ,  H05K2201/09018 ,  H05K2201/09118 ,  H05K2201/09827 ,  H05K2201/09854 ,  H05K2203/0582 ,  H05K2203/0588 ,  H05K2203/072 ,  H05K2203/107 ,  Y10T29/49124 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: A method of forming a multi-layer circuit on a curved substrate includes forming, by a laser direct structuring process, a first layer of the multi-layer circuit on a first surface of the curved substrate. The method includes applying a first layer of paint to the first layer of the multi-layer circuit. The method includes forming, by the laser direct structuring process, a second layer of the multi-layer circuit on the first layer of the paint and electrically coupled to the first layer of the multi-layer circuit. The method includes applying a second layer of paint over the second layer of the multi-layer circuit and forming, by the laser direct structuring process, a third layer of the multi-layer circuit on the second layer of the paint and electrically coupled to the second layer of the multi-layer circuit.

公开(公告)号：US20230199959A1

公开(公告)日：2023-06-22

申请号：US17996285

申请日：2021-04-16

Applicant: LG INNOTEK CO., LTD.

Inventor： Won Suk JUNG

IPC: H05K1/11 ,  H05K1/02

CPC classification number: H05K1/116 ,  H05K1/0298 ,  H05K2201/09854 ,  H05K2201/09827

Abstract: A circuit board according to an embodiment includes a first insulating layer; a second insulating layer disposed on an upper surface of the first insulating layer; a first circuit pattern buried in a lower region of the first insulating layer and including a first via pad; a second circuit pattern disposed between the first insulating layer and the second insulating layer and including a second via pad; a third circuit pattern buried in an upper region of the second insulating layer and including a third via pad; a first via disposed in the first insulating layer and connecting the first via pad and the second via pad; and a second via disposed in the second insulating layer and connecting the second via pad and the third via pad, and wherein at least one of an upper surface and a lower surface of the second via includes a convex portion in an upward or downward direction.

公开(公告)号：US20190215950A1

公开(公告)日：2019-07-11

申请号：US16358360

申请日：2019-03-19

Applicant: AT&S (China) Co. Ltd.

Inventor： Nikolaus Bauer-Öppinger ,  ZhaoJian Chen ,  Yucun Dou ,  Wilhelm Tamm

IPC: H05K1/02 ,  H05K1/09 ,  H05K3/42 ,  H05K3/00 ,  H05K1/11 ,  H05K1/18

CPC classification number: H05K1/0206 ,  H05K1/0209 ,  H05K1/09 ,  H05K1/112 ,  H05K1/181 ,  H05K3/0026 ,  H05K3/0035 ,  H05K3/42 ,  H05K2201/09509 ,  H05K2201/096 ,  H05K2201/09781 ,  H05K2201/09827 ,  H05K2201/09854 ,  H05K2203/107 ,  H05K2203/1476

Abstract: A component carrier includes a layer stack formed of an electrically insulating structure and an electrically conductive structure. Furthermore, a bore extends into the layer stack and has a first bore section with a first diameter (D1) and a connected second bore section with a second diameter (D2) differing from the first diameter (D1). A thermally conductive material fills substantially the entire bore. The bore is in particular formed by laser drilling.

公开(公告)号：US20180317319A1

公开(公告)日：2018-11-01

申请号：US15962076

申请日：2018-04-25

Applicant: Asahi Glass Company, Limited

Inventor： Shigetoshi MORI ,  Motoshi ONO ,  Mamoru ISOBE ,  Kohei HORIUCHI

IPC: H05K1/03 ,  H05K1/11

CPC classification number: H05K1/0306 ,  H05K1/115 ,  H05K3/002 ,  H05K3/0029 ,  H05K2201/09854

Abstract: A glass substrate includes a plurality of through holes that penetrate from a first surface to a second surface of the glass substrate. Each through hole has an upper aperture with a first diameter on the first surface and a lower aperture with a second diameter on the second surface. For each of ten through holes selected from the plurality of through holes, a side wall length is obtained from the first and second diameters and the thickness of the glass substrate, and an R value is obtained by dividing the side wall length by the thickness of the glass substrate. The R values fall within a range of 1 to 1.1. A B value, obtained from dividing a difference between the greatest R value and the smallest R value by an average of the R values followed by multiplication with 100, is 5% or less.

公开(公告)号：US20180084648A1

公开(公告)日：2018-03-22

申请号：US15811901

申请日：2017-11-14

Applicant: OLYMPUS CORPORATION

Inventor： Takahide MIYAWAKI

IPC: H05K1/18 ,  H05K3/30 ,  H05K3/34 ,  H05K1/14 ,  H05K3/36

CPC classification number: H05K1/186 ,  H01L23/13 ,  H01L23/5385 ,  H05K1/145 ,  H05K1/147 ,  H05K3/0014 ,  H05K3/301 ,  H05K3/3494 ,  H05K3/363 ,  H05K3/368 ,  H05K3/4697 ,  H05K2201/0141 ,  H05K2201/0154 ,  H05K2201/041 ,  H05K2201/042 ,  H05K2201/09854 ,  H05K2201/10015 ,  H05K2201/10022 ,  H05K2201/10636 ,  Y02P70/611

Abstract: A three-dimensional wiring board includes a chip component including a first end electrode and a second end electrode, a first wiring board with a recessed portion including a first junction electrode on a bottom surface, and a second wiring board, disposed on the first wiring board, including a second junction electrode, where the chip component is vertically housed in the recessed portion, the first end electrode is joined to the first junction electrode, and the second end electrode is joined to the second junction electrode.

公开(公告)号：US09860985B1

公开(公告)日：2018-01-02

申请号：US13716726

申请日：2012-12-17

Applicant: Lockheed Martin Corporation

Inventor： Jack V. Ajoian

IPC: H05K1/11 ,  H05K3/42 ,  H05K3/34 ,  H05K3/46

CPC classification number: H05K1/115 ,  H01L2924/01078 ,  H01L2924/01079 ,  H05K1/0222 ,  H05K1/111 ,  H05K1/112 ,  H05K1/116 ,  H05K3/3452 ,  H05K3/429 ,  H05K3/4602 ,  H05K2201/0355 ,  H05K2201/096 ,  H05K2201/09809 ,  H05K2201/09854

Abstract: A system and method of isolating a layer-to-layer transition between conductors in a multilayer printed circuit board includes formation of a first ground via at least partially surrounding a first signal conductor in at least one layer of the printed circuit board and formation of a second ground via at least partially surrounding a second signal conductor in another layer of the printed circuit board. The first and second ground vias are plated with a conductive material.