公开(公告)号：US12002795B2

公开(公告)日：2024-06-04

申请号：US17719857

申请日：2022-04-13

Applicant: Google LLC

Inventor： Houle Gan ,  Richard Stuart Roy ,  Yujeong Shim ,  William F. Edwards, Jr. ,  Chenhao Nan

IPC: H05K1/11 ,  H01L25/16 ,  H05K1/18 ,  H01L23/00

CPC classification number: H01L25/162 ,  H05K1/11 ,  H05K1/183 ,  H01L24/16 ,  H01L2224/16225 ,  H05K2201/10015 ,  H05K2201/1003 ,  H05K2201/10159 ,  H05K2201/10166 ,  H05K2201/1053 ,  H05K2201/10704 ,  H05K2201/10719

Abstract: A pluggable processor module includes a microprocessor package, a voltage regulator including a capacitor board, and contacts that each include a first side in contact with the microprocessor package and a second side in contact with the capacitor board. An assembly includes the pluggable processor module and a printed circuit board assembly (“PCBA”) including a module aperture that is large enough to receive the power board and narrower than the capacitor board.

公开(公告)号：US20240107674A1

公开(公告)日：2024-03-28

申请号：US17952895

申请日：2022-09-26

Applicant: Infineon Technologies Austria AG

Inventor： Eung San Cho ,  Danny Clavette

IPC: H05K1/18 ,  H02M3/00 ,  H05K1/11 ,  H05K1/14 ,  H05K3/00 ,  H05K3/30 ,  H05K3/36

CPC classification number: H05K1/18 ,  H02M3/003 ,  H05K1/117 ,  H05K1/141 ,  H05K1/145 ,  H05K3/0052 ,  H05K3/30 ,  H05K3/366 ,  H02M3/1584 ,  H05K2201/047 ,  H05K2201/09145 ,  H05K2201/10015 ,  H05K2201/1003 ,  H05K2201/1053

Abstract: This disclosure includes multiple assemblies, sub-assemblies, etc., as well as one or more methods of fabricating same. For example, a first assembly includes a first circuit board. The first circuit board further includes first connector elements disposed on a first edge of the first circuit board and second connector elements disposed on a second edge of the first circuit board. The first edge may be disposed substantially opposite the second edge on the first circuit board. The apparatus may further include first circuitry affixed to the first circuit board. The first edge of the first circuit board aligns with a first axial end of the first circuitry and the second edge of the first circuit board aligns with a second axial end of the first circuitry. The first assembly is used to fabricate a second assembly.

公开(公告)号：US20230309233A1

公开(公告)日：2023-09-28

申请号：US17842709

申请日：2022-06-16

Applicant: Kioxia Corporation

Inventor： Satoru FUKUCHI

IPC: H05K1/18 ,  H01L23/498 ,  H01L25/16 ,  H05K1/11

CPC classification number: H05K1/181 ,  H01L23/49827 ,  H01L25/16 ,  H01L25/162 ,  H01L23/49838 ,  H05K1/113 ,  H05K2201/10378 ,  H05K2201/10174 ,  H05K2201/10515 ,  H05K2201/1053 ,  H05K2201/09518 ,  H05K2201/09481 ,  H05K2201/10734

Abstract: An electronic device according to an embodiment includes first and second substrates, first and second conductors, and an electronic component. The first substrate includes a first connector portion, first pad portions, and a first transmission line. The first pad portions include a second pad portion, the first transmission line coupling the second pad portion and the first connector portion. The second substrate includes third pad portions. The third pad portions include a fourth pad portion and a fifth pad portion. The first conductor is coupled to the fourth pad portion and to the second pad portion. The second conductor is coupled to the fifth pad portion. The first electronic component has one end coupled to the first conductor and other end coupled to the second conductor.

公开(公告)号：US20230197622A1

公开(公告)日：2023-06-22

申请号：US17559431

申请日：2021-12-22

Applicant: Intel Corporation

Inventor： Karumbu Meyyappan ,  Jeffory L, Smalley ,  Gregorio Murtagian ,  Srikant Nekkanty ,  Pooya Tadayon ,  Eric J.M. Moret ,  Bijoyraj Sahu

IPC: H01L23/538 ,  H01L23/498 ,  H01R12/52 ,  H01L25/00 ,  H01L25/18 ,  H01L25/065 ,  H01R12/58 ,  H05K3/32 ,  H05K1/18

CPC classification number: H01L23/5384 ,  H01L23/49827 ,  H01L23/5385 ,  H01R12/52 ,  H01L25/50 ,  H01L25/18 ,  H01L25/0655 ,  H01R12/58 ,  H05K3/32 ,  H05K1/181 ,  H05K2201/10189 ,  H05K2201/10378 ,  H05K2201/10515 ,  H05K2201/1053

Abstract: An electronic system and associated methods are disclosed. In one example, the electronic system includes an interposer including electrically conductive interposer interconnect, a first interposer surface, and a second interposer surface; a processor package including at least one processor integrated circuit (IC), the processor package attached to the first interposer surface and electrically connected to the interposer interconnect; a first liquid metal well array including multiple liquid metal wells attached to a second interposer surface and the interposer interconnect; a second liquid metal well array including a first array surface attached to the first interposer surface and the interposer interconnect; and a packaged companion IC to the processor IC attached to a second array surface of the second liquid metal well array.

公开(公告)号：US20190165012A1

公开(公告)日：2019-05-30

申请号：US16245286

申请日：2019-01-11

Applicant: KONINKLIJKE PHILIPS N.V.

Inventor： Marc Anthony CHAPPO

IPC: H01L27/146 ,  H01L23/00 ,  H01L23/367 ,  H05K1/18

CPC classification number: H01L27/1469 ,  A61B6/032 ,  A61B6/4233 ,  H01L23/3675 ,  H01L24/14 ,  H01L24/16 ,  H01L24/81 ,  H01L27/14618 ,  H01L27/14661 ,  H01L27/14663 ,  H01L2224/131 ,  H01L2224/14131 ,  H01L2224/14135 ,  H01L2224/16145 ,  H01L2224/81815 ,  H05K1/18 ,  H05K3/3436 ,  H05K2201/10151 ,  H05K2201/1053 ,  H01L2924/014

Abstract: A module assembly device (402) is configured for assembling a module assembly (114) for a detector array (110) of an imaging system (100). The module assembly device includes a base (400) having a long axis (401). The module assembly device further includes a first surface (406) of the base and side walls (408) protruding perpendicular up from the first surface and extending in a direction of the long axis along at least two sides of the base. The first surface and side walls form a recess (404) configured to receive the module substrate on the surface and within the side walls. The module assembly device further includes protrusions (403) protruding from the side walls in a direction of the side walls. The protrusions and side walls interface forming a ledge which serves as a photo-detector array tile support (410) configured to receive the photo-detector array tile (118) over the ASIC and the module substrate.

公开(公告)号：US20190150268A1

公开(公告)日：2019-05-16

申请号：US16249391

申请日：2019-01-16

Applicant: FUJI ELECTRIC CO., LTD.

Inventor： Hideyo NAKAMURA ,  Masafumi HORIO

IPC: H05K1/02 ,  H05K1/18 ,  H01L25/065 ,  H01L25/07 ,  H01L25/16 ,  H05K1/03

CPC classification number: H05K1/025 ,  H01L25/0655 ,  H01L25/072 ,  H01L25/162 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48139 ,  H01L2224/73265 ,  H01L2924/13055 ,  H01L2924/13091 ,  H02M7/003 ,  H02M7/487 ,  H05K1/0306 ,  H05K1/181 ,  H05K2201/10166 ,  H05K2201/10174 ,  H05K2201/1053 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A semiconductor device includes a first circuit board on which a first switching element and a first diode connected in inverse parallel are mounted, a second circuit board on which a second switching element and a second diode connected in inverse parallel are mounted, a printed circuit board disposed opposite the first circuit board and the second circuit board, and a plurality of conductive posts which electrically connect the first switching element, the second switching element, the first diode, the second diode, the first circuit board, or the second circuit board and metal layers of the printed circuit board. The first switching element and the second switching element are connected in anti-series to form a bidirectional switch.

公开(公告)号：US20180242455A1

公开(公告)日：2018-08-23

申请号：US15961859

申请日：2018-04-24

Applicant: SKYWORKS SOLUTIONS, INC.

Inventor： Mark A. KUHLMAN ,  Anthony James LOBIANCO ,  Thomas NOLL ,  Robert W WARREN ,  Howard E. CHEN

IPC: H05K1/18 ,  H01L23/00 ,  H01L23/31 ,  H01L25/16 ,  H05K3/32 ,  H05K3/28

CPC classification number: H05K1/181 ,  H01L23/3121 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/16 ,  H01L2224/16265 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48471 ,  H01L2224/48472 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01082 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19103 ,  H01L2924/19104 ,  H05K3/284 ,  H05K3/321 ,  H05K2201/10166 ,  H05K2201/10515 ,  H05K2201/1053 ,  H05K2201/10636 ,  Y02P70/611 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Single-die or multi-die packaged modules that incorporate three-dimensional integration of active devices with discrete passive devices to create a package structure that allows active devices (such as, silicon or gallium-arsenide devices) to share the same footprint area as an array of passive surface mount components. In one example, a module includes at least one active device stacked on top of an array of passive surface mount components on a substrate. A conductive or non-conductive adhesive can be used to adhere the active device to the array of passive devices.

公开(公告)号：US10008474B2

公开(公告)日：2018-06-26

申请号：US15206729

申请日：2016-07-11

Applicant: International Business Machines Corporation

Inventor： Thomas J. Brunschwiler ,  Andreas Christian Doering ,  Ronald Peter Luijten ,  Stefano Sergio Oggioni ,  Patricia Maria Sagmeister ,  Martin Leo Schmatz

IPC: H01L29/40 ,  H01L25/065 ,  H01L23/498 ,  H01L23/31 ,  H01L23/00 ,  H01L23/367

CPC classification number: H01L25/0655 ,  H01L23/13 ,  H01L23/3114 ,  H01L23/36 ,  H01L23/367 ,  H01L23/49805 ,  H01L23/49838 ,  H01L24/48 ,  H01L25/105 ,  H01L2224/48091 ,  H01L2224/48225 ,  H01L2924/00014 ,  H01L2924/153 ,  H05K1/145 ,  H05K3/3442 ,  H05K3/366 ,  H05K3/403 ,  H05K2201/10515 ,  H05K2201/1053 ,  H05K2201/10727 ,  H05K2201/10984 ,  H05K2203/0228 ,  H05K2203/143 ,  H01L2224/45099

Abstract: Embodiments of the invention are directed to an integrated circuit (IC) package assembly, including: one or more printed circuit boards (PCBs); and a set of chip packages, each including: an overmold; and an IC chip, overmolded in the overmold, and wherein: the chip packages are stacked transversely to an average plane of each of the chip packages, thereby forming a stack wherein a main surface of one of the chip packages faces a main surface of another one of the chip packages; and each of the chip packages is laterally soldered to one or more of said one or more PCBs and arranged transversally to each of said one or more PCBs, whereby an average plane of each of said one or more PCBs extends transversely to the average plane of each of the chip packages of the stack. Further embodiments are directed to related devices and fabrication methods.

公开(公告)号：US20180168038A1

公开(公告)日：2018-06-14

申请号：US15892740

申请日：2018-02-09

Applicant: International Business Machines Corporation

Inventor： Ai Kiar Ang ,  Michael Lauri

IPC: H05K1/11 ,  H05K3/34 ,  H05K1/18 ,  H01L23/495 ,  H05K1/03 ,  H01L25/00 ,  H01L25/10 ,  H05K3/32 ,  H05K1/14 ,  H01L21/48

CPC classification number: H05K1/11 ,  H01L21/4839 ,  H01L23/49537 ,  H01L23/49555 ,  H01L23/49565 ,  H01L23/49575 ,  H01L25/105 ,  H01L25/50 ,  H01L2225/1029 ,  H01L2924/181 ,  H05K1/0313 ,  H05K1/144 ,  H05K1/18 ,  H05K1/181 ,  H05K3/328 ,  H05K3/341 ,  H05K3/3421 ,  H05K3/3426 ,  H05K2201/10015 ,  H05K2201/10227 ,  H05K2201/10515 ,  H05K2201/1053 ,  H05K2201/10962 ,  Y02P70/613 ,  H01L2924/00012

Abstract: A method includes forming a multi-stacked electronic device having two or more electronic components, each of the electronic components includes a leadframe, the leadframes of each electronic component are physically joined together using a non-solder metal joining process to form a joint, and the joint is located outside a solder connection region.

公开(公告)号：US20180153035A1

公开(公告)日：2018-05-31

申请号：US15880155

申请日：2018-01-25

Applicant: International Business Machines Corporation

Inventor： Ai Kiar Ang ,  Michael Lauri

IPC: H05K1/11 ,  H05K3/32 ,  H05K1/18 ,  H01L25/10 ,  H05K3/34 ,  H01L23/495 ,  H05K1/03 ,  H01L21/48 ,  H01L25/00 ,  H05K1/14

CPC classification number: H05K1/11 ,  H01L21/4839 ,  H01L23/49537 ,  H01L23/49555 ,  H01L23/49565 ,  H01L23/49575 ,  H01L25/105 ,  H01L25/50 ,  H01L2225/1029 ,  H01L2924/181 ,  H05K1/0313 ,  H05K1/144 ,  H05K1/18 ,  H05K1/181 ,  H05K3/328 ,  H05K3/341 ,  H05K3/3421 ,  H05K3/3426 ,  H05K2201/10015 ,  H05K2201/10227 ,  H05K2201/10515 ,  H05K2201/1053 ,  H05K2201/10962 ,  Y02P70/613 ,  H01L2924/00012

Abstract: A method includes forming a multi-stacked electronic device having two or more electronic components, each of the electronic components includes a leadframe, the leadframes of each electronic component are physically joined together using a non-solder metal joining process to form a joint, and the joint is located outside a solder connection region.