公开(公告)号：US20190088336A1

公开(公告)日：2019-03-21

申请号：US15811695

申请日：2017-11-14

Applicant: PHISON ELECTRONICS CORP.

Inventor： Wei Lin ,  Yu-Cheng Hsu ,  Szu-Wei Chen ,  Yu-Siang Yang

IPC: G11C16/10 ,  G06F12/02 ,  G06F11/10 ,  G11C29/52 ,  G11C16/30 ,  G11C16/08 ,  G11C16/26

CPC classification number: G11C29/52 ,  G06F11/1068 ,  G06F11/1072 ,  G06F12/0246 ,  G06F2212/7201 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C16/30

Abstract: A decoding method, a memory controlling circuit unit, and a memory storage device are provided. The method includes: when first data is read from a first upper physical programming unit of a first physical programming unit group by using a second voltage selected from a first read voltage group, and a first error bit count of the first data is not greater than a first error bit count threshold, recording the second voltage; when a second data is read from a first lower physical programming unit of a second physical programming unit group by using a fourth voltage selected from a second read voltage group, and a second error bit count of the second data is not greater than a second error bit count threshold, recording the fourth voltage; generating a lookup table according to the second voltage and the fourth voltage; and performing a decoding operation according to the lookup table.

公开(公告)号：US10025660B2

公开(公告)日：2018-07-17

申请号：US15009771

申请日：2016-01-28

Applicant: PHISON ELECTRONICS CORP.

Inventor： Wei Lin ,  Tien-Ching Wang ,  Kuo-Hsin Lai

IPC: G06F11/00 ,  G06F11/10 ,  G11C29/52

CPC classification number: G06F11/1068 ,  G06F11/1012 ,  G11C29/52

Abstract: A data reading method for a rewritable non-volatile memory module is provided. The method includes performing an error correction decoding operation on an user data stream according to an error checking and correcting (ECC) code to generate a first decoded data stream; searching uncorrectable sub-data units from decoded sub-data units of the first decoded data stream; selecting a target sub-data unit from the uncorrectable sub-data units; adjusting the target sub-data unit in the first decoded data stream to generate an adjusted user data stream; and re-performing the error correction decoding operation on the adjusted user data stream to generate a second decoded data stream; if the second decoded data stream has no error bit, transmitting the second decoded data stream as a corrected data stream to a host system.

公开(公告)号：US20180136841A1

公开(公告)日：2018-05-17

申请号：US15412065

申请日：2017-01-23

Applicant: PHISON ELECTRONICS CORP.

Inventor： Wei Lin ,  Yu-Cheng Hsu ,  Szu-Wei Chen

IPC: G06F3/06

CPC classification number: G11C16/10 ,  G06F3/06 ,  G11C7/1006 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/08 ,  G11C29/76

Abstract: A data writing method for a rewritable non-volatile memory module having a plurality of physical erasing units and a memory control circuit unit and a memory storage apparatus using the same are provided. Each of the physical erasing units has a plurality of physical programming unit sets, and each of the physical programming unit sets has a plurality of physical programming unit. The method includes receiving data and arranging the data to generate a first data stream and a second data stream. The method also includes encoding the first data stream and the second data stream to generate a third data stream, and issuing a programming command sequence to write the first data stream, the second data stream and the third data stream respectively into a first physical programming unit, a second physical programming unit and a third physical programming unit of a physical programming unit set.

公开(公告)号：US09837435B1

公开(公告)日：2017-12-05

申请号：US15461478

申请日：2017-03-17

Applicant: PHISON ELECTRONICS CORP.

Inventor： Chun-Yen Chang ,  Chun-Hu Cheng ,  Wei Lin ,  Yu-Chien Chiu ,  Chien Liu

IPC: H01L27/00 ,  H01L27/11582 ,  H01L29/792 ,  H01L27/11568 ,  H01L29/10 ,  H01L27/11551 ,  H01L21/822 ,  H01L27/11578 ,  H01L27/06 ,  H01L27/11502

CPC classification number: H01L27/11582 ,  G11C11/22 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/11502 ,  H01L27/11551 ,  H01L27/11568 ,  H01L27/11578 ,  H01L29/1037 ,  H01L29/7926

Abstract: A three-dimensional non-volatile memory structure including a substrate, a stacked structure, a charge storage pillar, a channel pillar, and a ferroelectric material pillar is provided. The stacked structure is disposed on the substrate and includes a plurality of conductive layers and a plurality of first dielectric layers, and the conductive layers and the first dielectric layers are alternately stacked. The charge storage pillar is disposed in the stacked structure. The channel pillar is disposed inside the charge storage pillar. The ferroelectric material pillar is disposed inside the channel pillar.

公开(公告)号：US20170168893A1

公开(公告)日：2017-06-15

申请号：US15009771

申请日：2016-01-28

Applicant: PHISON ELECTRONICS CORP.

Inventor： Wei Lin ,  Tien-Ching Wang ,  Kuo-Hsin Lai

IPC: G06F11/10 ,  G11C29/52

CPC classification number: G06F11/1068 ,  G06F11/1012 ,  G11C29/52

Abstract: A data reading method for a rewritable non-volatile memory module is provided. The method includes performing an error correction decoding operation on an user data stream according to an error checking and correcting (ECC) code to generate a first decoded data stream; searching uncorrectable sub-data units from decoded sub-data units of the first decoded data stream; selecting a target sub-data unit from the uncorrectable sub-data units; adjusting the target sub-data unit in the first decoded data stream to generate an adjusted user data stream; and re-performing the error correction decoding operation on the adjusted user data stream to generate a second decoded data stream; if the second decoded data stream has no error bit, transmitting the second decoded data stream as a corrected data stream to a host system.

公开(公告)号：US20160284414A1

公开(公告)日：2016-09-29

申请号：US14727878

申请日：2015-06-02

Applicant: PHISON ELECTRONICS CORP.

Inventor： Wei Lin ,  Tien-Ching Wang ,  Kuo-Hsin Lai ,  Yu-Cheng Hsu ,  Chi-Heng Yang

IPC: G11C16/14 ,  G11C29/44 ,  G11C16/26 ,  G06F3/06 ,  G06F12/08

CPC classification number: G11C16/14 ,  G06F3/0604 ,  G06F3/0619 ,  G06F3/0629 ,  G06F3/0679 ,  G06F12/0246 ,  G06F12/0802 ,  G06F2212/1044 ,  G06F2212/7203 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/26 ,  G11C16/349 ,  G11C29/021 ,  G11C29/028 ,  G11C29/4401 ,  G11C2029/0409 ,  G11C2211/5648

Abstract: A data programming method, a memory storage device and a memory control circuit unit are provided. The method includes: receiving first data and programming the first data into a first lower physical programming unit; receiving second data; in response to the second data to be programmed into a first upper physical programming unit corresponding to the first lower physical programming unit, performing a first data obtaining operation which does not include reading the first lower physical programming unit by using a default read voltage; and programming the second data into the first upper physical programming unit according to the third data obtained through the first data obtaining operation.

Abstract translation: 提供数据编程方法，存储器存储装置和存储器控制电路单元。 该方法包括：接收第一数据并将第一数据编程到第一较低物理编程单元中; 接收第二数据; 响应于要被编程到与第一下部物理编程单元相对应的第一上部物理编程单元的第二数据，执行不包括通过使用默认读取电压读取第一下部物理编程单元的第一数据获取操作; 以及根据通过第一数据获取操作获得的第三数据将第二数据编程到第一上层物理编程单元中。

公开(公告)号：US20160240256A1

公开(公告)日：2016-08-18

申请号：US14692759

申请日：2015-04-22

Applicant: PHISON ELECTRONICS CORP.

Inventor： Wei Lin ,  Yu-Cheng Hsu ,  An-Cheng Liu ,  Siu-Tung Lam

IPC: G11C16/10 ,  G11C16/34

CPC classification number: G11C16/10 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/3459

Abstract: A memory programming method for a rewritable non-volatile memory module having memory cells is provided. The memory programming method includes: performing a first programming process on the memory cells according to write data and obtaining a first programming result of the first programming process; grouping the memory cells into programming groups according to the first programming result; and performing a second programming process on the memory cells according to the write data. The second programming process includes: programming a first programming group among the programming groups by using a first program voltage; and programming a second programming group among the programming groups by using a second program voltage. The first program voltage and the second program voltage are different. Moreover, a memory control circuit unit and a memory storage device are provided.

Abstract translation: 提供了一种用于具有存储器单元的可重写非易失性存储器模块的存储器编程方法。 存储器编程方法包括：根据写数据对存储器单元执行第一编程处理并获得第一编程处理的第一编程结果; 根据第一编程结果将存储器单元分组成编程组; 以及根据写入数据对存储器单元执行第二编程处理。 第二编程过程包括：通过使用第一编程电压对编程组中的第一编程组进行编程; 以及通过使用第二编程电压来编程所述编程组中的第二编程组。 第一编程电压和第二编程电压不同。 此外，提供存储器控制电路单元和存储器存储装置。

公开(公告)号：US20160232053A1

公开(公告)日：2016-08-11

申请号：US14693885

申请日：2015-04-23

Applicant: PHISON ELECTRONICS CORP.

Inventor： Wei Lin ,  Yu-Cheng Hsu ,  An-Cheng Liu ,  Siu-Tung Lam

IPC: G06F11/10 ,  G11C29/50 ,  G11C29/52

CPC classification number: G06F11/108 ,  G06F11/1072 ,  G11C5/148 ,  G11C11/5628 ,  G11C16/12 ,  G11C16/3459 ,  G11C29/021 ,  G11C29/028 ,  G11C29/42 ,  G11C29/52 ,  G11C2029/0409 ,  G11C2029/0411

Abstract: The present disclosure provides a memory management method for a rewritable non-volatile memory module. The rewritable non-volatile memory module includes physical programming units, each of which includes multiple bits. The memory management method includes: identifying a first physical programming unit by applying a predetermined read voltage, where the first physical programming unit is identified as in a fully-erased status; identifying a second and a third physical programming units which are programmed before the first physical programming unit; acquiring status data of the second and the third physical programming unit; computing a difference of the status data between the second and the third physical programming unit; if the difference is larger than a threshold, identifying the second physical programming unit as in a program failure status.

Abstract translation: 本公开提供了一种用于可重写非易失性存储器模块的存储器管理方法。 可重写非易失性存储器模块包括物理编程单元，每个物理编程单元包括多个位。 存储器管理方法包括：通过施加预定的读取电压来识别第一物理编程单元，其中第一物理编程单元被识别为完全擦除状态; 识别在第一物理编程单元之前编程的第二和第三物理编程单元; 获取第二和第三物理编程单元的状态数据; 计算第二和第三物理编程单元之间的状态数据的差异; 如果差异大于阈值，则在程序故障状态中识别第二物理编程单元。

公开(公告)号：US09312013B1

公开(公告)日：2016-04-12

申请号：US14693876

申请日：2015-04-23

Applicant: PHISON ELECTRONICS CORP.

Inventor： Wei Lin ,  Yu-Cheng Hsu ,  An-Cheng Liu ,  Siu-Tung Lam

IPC: G11C16/04 ,  G11C16/14 ,  G11C16/34

CPC classification number: G11C16/3495 ,  G11C16/0483 ,  G11C16/16 ,  G11C16/3445

Abstract: A configuration method of erase operation, a memory controlling circuit unit, and a memory storage device are provided. The method includes: determining whether a first use state of a first physical unit conforms to a first default state; and if the first use state conforms to the first default state, adjusting a first erase operation corresponding to the first physical unit from using a first mode to a second mode. Thereby, a threshold voltage distribution of memory cells in an erase state may be maintained in a proper range.

Abstract translation: 提供擦除操作的配置方法，存储器控制电路单元和存储器存储设备。 该方法包括：确定第一物理单元的第一使用状态是否符合第一默认状态; 并且如果第一使用状态符合第一默认状态，则调整与第一物理单元相对应的第一擦除操作，从第一模式到第二模式。 因此，可以将擦除状态的存储单元的阈值电压分布保持在适当的范围内。

公开(公告)号：US09286986B2

公开(公告)日：2016-03-15

申请号：US14257010

申请日：2014-04-21

Applicant: PHISON ELECTRONICS CORP.

Inventor： Chih-Kang Yeh ,  Wei Lin

IPC: G11C16/10 ,  G11C11/56 ,  G11C16/04 ,  G11C16/34 ,  G11C7/04 ,  G11C29/02 ,  G11C7/10

CPC classification number: G11C16/10 ,  G11C7/04 ,  G11C7/1006 ,  G11C11/5628 ,  G11C11/5671 ,  G11C16/0466 ,  G11C16/3418 ,  G11C16/3468 ,  G11C16/349 ,  G11C16/3495 ,  G11C29/028 ,  G11C2211/5621

Abstract: A data writing method for writing data into a memory cell of a rewritable non-volatile memory module, and a memory control circuit unit and a memory storage apparatus using the same area provided. The method includes recording a wear degree of the memory cell and detecting an operating temperature of the memory storage apparatus. The method further includes adjusting at least one predetermined operation parameter corresponding to the rewritable non-volatile memory module to generate at least one adjusted operation parameter corresponding to the rewritable non-volatile memory module and writing the data into the memory cell based on the at least one adjusted operation parameter if the operating temperature of the memory storage apparatus is larger than a predetermined temperature. Accordingly, the method can accurately store data into the rewritable non-volatile memory module, thereby lowing the operating temperature of the memory storage apparatus.

Abstract translation: 一种用于将数据写入可重写非易失性存储器模块的存储单元的数据写入方法，以及使用相同区域的存储器控​​制电路单元和存储器存储装置。 该方法包括记录存储单元的磨损程度并检测存储器存储装置的工作温度。 该方法还包括调整与可重写非易失性存储器模块相对应的至少一个预定操作参数，以生成与可重写非易失性存储器模块对应的至少一个经调整的操作参数，并至少基于至少一个数据写入存储器单元 如果存储器存储装置的工作温度大于预定温度，则调节操作参数。 因此，该方法可以将数据精确地存储到可重写非易失性存储器模块中，从而降低存储器存储装置的工作温度。