公开(公告)号：US07344994B2

公开(公告)日：2008-03-18

申请号：US11063108

申请日：2005-02-22

Applicant: John W. Krawczyk ,  Andrew L. McNees ,  Christopher J. Money ,  Girish S. Patil ,  David B. Rhine ,  Karthik Vaideeswaran

Inventor： John W. Krawczyk ,  Andrew L. McNees ,  Christopher J. Money ,  Girish S. Patil ,  David B. Rhine ,  Karthik Vaideeswaran

IPC: H01L21/302 ,  H01L21/461

CPC classification number: H01L21/0332 ,  B81B2203/0353 ,  B81C1/00531 ,  B81C1/00619 ,  B81C2201/0132 ,  B81C2201/014 ,  H01L21/0334 ,  H01L21/3081 ,  H01L21/3083

Abstract: A process for etching semiconductor substrates using a deep reactive ion etching process to produce through holes or slots (hereinafter “slots”) in the substrates. The process includes applying a first layer to a back side of a substrate as a first etch stop material. The first layer is a relatively soft etch stop material. A second layer is applied to the first layer on the back side of the substrate to provide a composite etch stop layer. The second layer is a relatively hard etch stop material. The substrate is etched from a side opposite the back side of the substrate to provide a slot in the substrate.

Abstract translation: 使用深反应离子蚀刻工艺蚀刻半导体衬底以在衬底中产生通孔或槽（以下称为“槽”）的工艺。 该方法包括将第一层作为第一蚀刻停止材料施加到衬底的背面。 第一层是相对软的蚀刻停止材料。 将第二层施加到衬底的背面上的第一层以提供复合蚀刻停止层。 第二层是相对硬的蚀刻停止材料。 从与衬底的背面相对的一侧蚀刻衬底，以在衬底中提供槽。

公开(公告)号：US20070119814A1

公开(公告)日：2007-05-31

申请号：US11627026

申请日：2007-01-25

Applicant: Satyadev Patel ,  Gregory Schaadt ,  Douglas MacDonald ,  Niles MacDonald ,  Hongqin Shi

Inventor： Satyadev Patel ,  Gregory Schaadt ,  Douglas MacDonald ,  Niles MacDonald ,  Hongqin Shi

IPC: C03C25/68 ,  G01L21/30 ,  H01L21/306 ,  H01L21/461 ,  B44C1/22

CPC classification number: H01J37/32963 ,  B81C1/00476 ,  B81C1/00587 ,  B81C99/0065 ,  B81C2201/0132 ,  B81C2201/0138 ,  H01J37/32449 ,  H01J37/32935

Abstract: Processes for the removal of a layer or region from a workpiece material by contact with a process gas in the manufacture of a microstructure are enhanced by the ability to accurately determine the endpoint of the removal step. A vapor phase etchant is used to remove a material that has been deposited on a substrate, with or without other deposited structure thereon. By creating an impedance at the exit of an etching chamber (or downstream thereof), as the vapor phase etchant passes from the etching chamber, a gaseous product of the etching reaction is monitored; and the endpoint of the removal process can be determined. The vapor phase etching process can be flow through, a combination of flow through and pulse, or recirculated back to the etching chamber

Abstract translation: 通过与制造微结构中的工艺气体接触从工件材料去除层或区域的工艺通过精确地确定去除步骤的终点的能力增强。 气相蚀刻剂用于去除已经沉积在基底上的材料，其上具有或不具有其它沉积结构。 通过在蚀刻室（或其下游）的出口处产生阻抗，当气相蚀刻剂从蚀刻室通过时，监测蚀刻反应的气态产物; 并且可以确定去除过程的终点。 气相蚀刻工艺可以流过，流过和脉冲的组合，或再循环回蚀刻室

公开(公告)号：US20070072428A1

公开(公告)日：2007-03-29

申请号：US11239259

申请日：2005-09-29

Applicant: Dan Chilcott

Inventor： Dan Chilcott

IPC: H01L21/311

CPC classification number: B81C1/00531 ,  B81B2203/033 ,  B81C2201/0132 ,  B81C2201/0142

Abstract: A technique for manufacturing a micro-electro-mechanical (MEM) structure includes a number of steps. Initially, a substrate is provided. Next, a plurality of trenches are etched into the substrate with a first etch. Then, a charging layer is formed at a bottom of each of the trenches to form undercut trenches. Finally, a second etch is provided into the undercut trenches. The charging layer causes the second etch to laterally etch foots in the substrate between the undercut trenches. The footers undercut the substrate to release a portion of the substrate for providing a movable structure between the undercut trenches and above the footers.

Abstract translation: 微机电（MEM）结构的制造技术包括多个步骤。 首先，提供基板。 接下来，通过第一蚀刻将多个沟槽蚀刻到衬底中。 然后，在每个沟槽的底部形成充电层以形成底切沟槽。 最后，在底切沟槽中提供第二蚀刻。 充电层导致第二蚀刻在底切沟槽之间横向蚀刻衬底中的脚。 脚底底切基板以释放基板的一部分，以在底切沟槽和页脚之上提供可移动结构。

公开(公告)号：US07189332B2

公开(公告)日：2007-03-13

申请号：US10269149

申请日：2002-10-11

Applicant: Satyadev R. Patel ,  Gregory P. Schaadt ,  Douglas B. MacDonald ,  Niles K. MacDonald ,  Hongqin Shi

Inventor： Satyadev R. Patel ,  Gregory P. Schaadt ,  Douglas B. MacDonald ,  Niles K. MacDonald ,  Hongqin Shi

IPC: C23F3/12

CPC classification number: H01J37/32963 ,  B81C1/00476 ,  B81C1/00587 ,  B81C99/0065 ,  B81C2201/0132 ,  B81C2201/0138 ,  H01J37/32449 ,  H01J37/32935

Abstract: Processes for the removal of a layer or region from a workpiece material by contact with a process gas in the manufacture of a microstructure are enhanced by the ability to accurately determine the endpoint of the removal step. A vapor phase etchant is used to remove a material that has been deposited on a substrate, with or without other deposited structure thereon. By creating an impedance at the exit of an etching chamber (or downstream thereof), as the vapor phase etchant passes from the etching chamber, a gaseous product of the etching reaction is monitored, and the endpoint of the removal process can be determined. The vapor phase etching process can be flow through, a combination of flow through and pulse, or recirculated back to the etching chamber.

Abstract translation: 通过与制造微结构中的工艺气体接触从工件材料去除层或区域的工艺通过精确地确定去除步骤的终点的能力增强。 气相蚀刻剂用于去除已经沉积在基底上的材料，其上具有或不具有其它沉积结构。 通过在蚀刻室（或其下游）的出口处产生阻抗，当气相蚀刻剂从蚀刻室通过时，监测蚀刻反应的气态产物，并且可以确定去除过程的终点。 气相蚀刻工艺可以流过，流过和脉冲的组合，或再循环回蚀刻室。

公开(公告)号：US07160751B2

公开(公告)日：2007-01-09

申请号：US11151680

申请日：2005-06-13

Applicant: Dan W. Chilcott

Inventor： Dan W. Chilcott

IPC: H01L21/00

CPC classification number: B81C1/00944 ,  B81C2201/0132

Abstract: A process for making a microelectromechanical device having a moveable component defined by a gap pattern in a semiconductor layer of a silicon-on-insulator wafer involves the use of a plurality of deep reactive ion etching steps at various etch depths that are used to allow a buried oxide layer of the silicon-on-insulator wafer to be exposed in selected areas before the entire moveable component of the resulting device is freed for movement. This method allows wet release techniques to be used to remove the buried oxide layer without developing stiction problems. This is achieved by utilizing deep reactive ion etching to free the moveable component after a selected portion of the buried oxide layer has been removed by wet etching.

Abstract translation: 用于制造具有由绝缘体上硅晶片的半导体层中的间隙图案限定的可移动部件的微机电装置的方法包括在各种蚀刻深度处使用多个深反应离子蚀刻步骤，所述蚀刻深度用于允许 绝缘体上硅晶片的掩埋氧化物层在所得器件的整个可移动部件被释放以移动之前被暴露在所选区域内。 该方法允许使用湿式释放技术去除掩埋氧化物层而不产生粘性问题。 这是通过利用深反应离子蚀刻来在通过湿法蚀刻去除掩埋氧化物层的选定部分之后释放可移动部件来实现的。

公开(公告)号：US07077007B2

公开(公告)日：2006-07-18

申请号：US10715758

申请日：2003-11-18

Applicant: David Boyd Rich ,  John C. Christenson

Inventor： David Boyd Rich ,  John C. Christenson

IPC: G01P15/00 ,  G01P15/125 ,  G01P15/14 ,  G01P9/00

CPC classification number: H01L21/67069 ,  B81B2201/025 ,  B81B2203/0118 ,  B81C1/00404 ,  B81C1/00587 ,  B81C2201/0132 ,  G01P15/0802 ,  G01P15/0888 ,  G01P15/125

Abstract: A process for forming a microelectromechanical system (MEMS) device by a deep reactive ion etching (DRIE) process during which a substrate overlying a cavity is etched to form trenches that breach the cavity to delineate suspended structures. A first general feature of the process is to define suspended structures with a DRIE process, such that the dimensions desired for the suspended structures are obtained. A second general feature is the proper location of specialized features, such as stiction bumps, vulnerable to erosion caused by the DRIE process. Yet another general feature is to control the environment surrounding suspended structures delineated by DRIE in order to obtain their desired dimensions. A significant problem identified and solved by the invention is the propensity for the DRIE process to etch certain suspended features at different rates. In addition to etching wider trenches more rapidly than narrower trenches, the DRIE process erodes suspended structures more rapidly at greater distances from anchor sites of the substrate being etched. At the masking level, the greater propensity for backside and lateral erosion of certain structures away from substrate anchor sites is exploited so that, at the completion of the etch process, suspended structures have acquired their respective desired widths.

公开(公告)号：US20060081929A1

公开(公告)日：2006-04-20

申请号：US11242824

申请日：2005-10-05

Applicant: Seok-whan Chung ,  Hyung Choi

Inventor： Seok-whan Chung ,  Hyung Choi

IPC: H01L21/84 ,  H01L27/12

CPC classification number: B81C1/00579 ,  B81C2201/0132

Abstract: A silicon-on-insulator (SOI) substrate including laminated layers of a substrate, an oxide layer, and a silicon layer in order. The oxide layer has an electrifying hole fluidly connected with the substrate and the electrifying hole is filled with a part of the silicon layer. A method for fabricating the floating structure is also disclosed which includes the steps of forming an oxide layer having a predetermined thickness on a substrate, forming one or more electrifying holes in an area of the oxide layer corresponding to an inner part of the floating structure, forming a silicon layer on the oxide layer including an electrification structure electrically connecting the silicon layer to the substrate, forming a pattern for the floating structure on the silicon layer, removing the oxide layer corresponding to an inner area of the pattern, forming a thermal oxide layer on a surface of the silicon layer, and removing the thermal oxide layer to form the floating structure.

Abstract translation: 一种绝缘体上硅（SOI）衬底，包括衬底，氧化物层和硅层的叠层。 氧化物层具有与基板流体连接的带电孔，并且充电孔填充有硅层的一部分。 还公开了一种用于制造浮动结构的方法，其包括在衬底上形成具有预定厚度的氧化物层的步骤，在与浮动结构的内部对应的氧化物层的区域中形成一个或多个通电孔， 在所述氧化物层上形成硅层，所述硅层包括将所述硅层电连接到所述衬底的带电结构，在所述硅层上形成所述浮动结构的图案，除去与所述图案的内部区域对应的所述氧化物层，形成热氧化物 层，并且去除热氧化物层以形成浮动结构。

公开(公告)号：US20060076312A1

公开(公告)日：2006-04-13

申请号：US11242916

申请日：2005-10-05

Applicant: Darrell McReynolds ,  Kia Silverbrook

Inventor： Darrell McReynolds ,  Kia Silverbrook

IPC: C23F1/00 ,  G01D15/00

CPC classification number: H01L21/02057 ,  B41J2/1412 ,  B41J2/1601 ,  B41J2/1623 ,  B41J2/1628 ,  B41J2/1631 ,  B41J2/164 ,  B81B2201/052 ,  B81B2203/033 ,  B81C1/00849 ,  B81C2201/0112 ,  B81C2201/0132

Abstract: A process for facilitating modification of an etched trench is provided. The process comprises: (a) providing a wafer comprising an etched trench, the trench having a photoresist plug at its base; and (b) removing a portion of the photoresist by subjecting the wafer to a biased oxygen plasma etch. The process is particularly suitable for preparing a trench for subsequent argon ion milling. Printhead integrated circuits fabricated by a process according to the invention have improved ink channel surface profiles and/or surface properties.

公开(公告)号：US20060057761A1

公开(公告)日：2006-03-16

申请号：US11256959

申请日：2005-10-25

Applicant: Xiaoyu Mi ,  Norinao Kouma ,  Osamu Tsuboi ,  Masafumi Iwaki ,  Hisao Okuda ,  Hiromitsu Soneda ,  Satoshi Ueda ,  Ippei Sawaki

Inventor： Xiaoyu Mi ,  Norinao Kouma ,  Osamu Tsuboi ,  Masafumi Iwaki ,  Hisao Okuda ,  Hiromitsu Soneda ,  Satoshi Ueda ,  Ippei Sawaki

IPC: H01L21/00

CPC classification number: B81C1/00547 ,  B81B2201/042 ,  B81B2203/0136 ,  B81C2201/0132 ,  B81C2201/0133 ,  G01P15/0802 ,  G02B26/0841

Abstract: A method of making a microstructure with thin wall portions (T1-T3) includes a step of performing a first etching process to a material substrate having a laminate structure including a first conductive layer (11) and a second conductive layer (12) having a thickness of the thin wall portions (T1-T3), where the etching is performed from the side of the first conductive layer (11) thereby forming in the second conductive layer (12) pre thin wall portions (T1′-T3′) which has a pair of side surfaces apart from each other in an in-plane direction of the second conductive layer (12) and contact the first conductive layer (11). The method also includes a step of performing a second etching process from the side of the first conductive layer (11) for removing part of the first conductive layer (11) contacting the pre thin wall portions (T1′-T3′) to form the thin wall portions.

Abstract translation: 制造具有薄壁部分（T 1 -T 3）的微结构的方法包括对具有包括第一导电层（11）和第二导电层（12）的层压结构的材料基板进行第一蚀刻工艺的步骤， 具有薄壁部分（T 1 -T 3）的厚度，其中从第一导电层（11）的侧面进行蚀刻，从而在第二导电层（12）中形成预薄壁部分（T 1' -T 3'），其在第二导电层（12）的面内方向上具有彼此分离的一对侧表面，并与第一导电层（11）接触。 该方法还包括从第一导电层（11）侧进行第二蚀刻处理以去除与预薄壁部分（T 1'-T 3'）接触的第一导电层（11）的一部分的步骤 形成薄壁部分。

公开(公告)号：US07012322B2

公开(公告)日：2006-03-14

申请号：US10746219

申请日：2003-12-22

Applicant: Jeffrey A. Ridley ,  James A. Neus

Inventor： Jeffrey A. Ridley ,  James A. Neus

IPC: H01L23/495

CPC classification number: B81C1/00698 ,  B81B2201/0271 ,  B81B2201/033 ,  B81C2201/0132

Abstract: Methods of fabricating comb drive devices utilizing one or more sacrificial etch-buffers are disclosed. An illustrative fabrication method may include the steps of etching a pattern onto a wafer substrate defining one or more comb drive elements and sacrificial etch-buffers, liberating and removing one or more sacrificial etch-buffers prior to wafer bonding, bonding the etched wafer substrate to an underlying support substrate, and etching away the wafer substrate. In some embodiments, the sacrificial etch-buffers are removed after bonding the wafer to the support substrate. The sacrificial etch-buffers can be provided at one or more selective regions to provide greater uniformity in etch rate during etching. A comb drive device in accordance with an illustrative embodiment can include a number of interdigitated comb fingers each having a more uniform profile along their length and/or at their ends, producing less harmonic distortion during operation.

Abstract translation: 公开了使用一个或多个牺牲蚀刻缓冲器制造梳状驱动装置的方法。 示例性的制造方法可以包括以下步骤：将图案蚀刻到限定一个或多个梳状驱动元件和牺牲蚀刻缓冲器的晶片衬底上，在晶片接合之前释放和去除一个或多个牺牲蚀刻缓冲器，将蚀刻的晶片衬底接合到 底层支撑衬底，并蚀刻掉晶片衬底。 在一些实施例中，在将晶片接合到支撑衬底之后去除牺牲蚀刻缓冲器。 可以在一个或多个选择性区域处提供牺牲蚀刻缓冲器，以在蚀刻期间提供更大的蚀刻速率均匀性。 根据说明性实施例的梳状驱动装置可以包括多个交叉指状梳，每个梳指在其长度和/或其端部具有更均匀的轮廓，在操作期间产生较少的谐波失真。