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    WIRING BOARD
    91.
    发明申请
    WIRING BOARD 有权
    接线板

    公开(公告)号：US20100128075A1

    公开(公告)日：2010-05-27

    申请号：US12625980

    申请日：2009-11-25

    Applicant: Toru YAMASHITA

    Inventor： Toru YAMASHITA

    IPC: B41J29/38 ,  H05K1/18 ,  H05K3/30

    CPC classification number: H05K1/181 ,  B41J2/04573 ,  B41J2/04581 ,  B41J2/04595 ,  B41J2/14233 ,  B41J2002/14491 ,  H05K1/111 ,  H05K1/189 ,  H05K2201/09227 ,  H05K2201/10674 ,  H05K2201/10689 ,  Y02P70/611 ,  Y10T29/4913

    Abstract: An FPC connected to a piezoelectric actuator has a board and two driver ICs mounted on the board. The board is provided with two wires for transmitting two kinds of mode selection signals respectively corresponding to two kinds of driving modes and with a selection pad selecting one from the two kinds of mode selection signals transmitted through the two wires and then outputting the selected signal to each driver IC.

    Abstract translation: 连接到压电致动器的FPC具有板和安装在板上的两个驱动器IC。 该电路板设有两条线，用于分别对应于两种驱动模式发送两种模式选择信号，并且具有从通过两条线路发送的两种模式选择信号中选择一个的选择板，然后将所选择的信号输出到 每个驱动IC。

    Integrated circuit die configuration for packaging
    92.
    发明授权
    Integrated circuit die configuration for packaging 有权
    集成电路管芯配置包装

    公开(公告)号：US07714427B2

    公开(公告)日：2010-05-11

    申请号：US11554528

    申请日：2006-10-30

    Applicant: Chee Wai Wong ,  Chee Hoo Lee

    Inventor： Chee Wai Wong ,  Chee Hoo Lee

    IPC: H01L23/48

    CPC classification number: H01L23/5286 ,  H01L23/49838 ,  H01L23/562 ,  H01L23/66 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/3511 ,  H05K1/181 ,  H05K2201/09227 ,  H05K2201/09418 ,  H05K2201/10719 ,  Y02P70/611 ,  H01L2924/00 ,  H01L2224/0401

    Abstract: Integrate circuit die terminal arrangements and configurations for mounting an integrate circuit die on a package substrate to reduce package transmission paths. In one embodiment, terminals for signals sensitive to trace length outside a die are arranged at the corners of the die. The die is mounted on a package substrate in an angle with respect to a package substrate to point the corners of the die at the edges of the package substrate to reduce trace length outside the die. The center of the die may or may not coincide with the center of the substrate. In one embodiment, when compare to a centered, non-rotated die mounting position, mounting a die with corners pointing at the edges of the package substrate does not cause significant differences in substrate warpage.

    Abstract translation: 集成电路管芯端子布置和配置，用于将集成电路管芯安装在封装衬底上，以减少封装传输路径。 在一个实施例中，对于在管芯外部的迹线长度敏感的信号的端子设置在管芯的角部。 模具相对于封装衬底以一定角度安装在封装衬底上，以将芯片的角部指向封装衬底的边缘，以减小管芯外部的迹线长度。 管芯的中心可以与衬底的中心重合或者不一致。 在一个实施例中，当与居中的未旋转的模具安装位置相比时，安装具有指向封装基板边缘的拐角的模具不会引起基板翘曲的显着差异。

    Ultra-thin alphanumeric display
    93.
    发明授权
    Ultra-thin alphanumeric display 失效
    超薄字母数字显示

    公开(公告)号：US07683384B2

    公开(公告)日：2010-03-23

    申请号：US11447300

    申请日：2006-06-06

    Applicant: David Fisher ,  Philip Heft ,  Rocco Vetro

    Inventor： David Fisher ,  Philip Heft ,  Rocco Vetro

    IPC: H01L27/15

    CPC classification number: G09F9/33 ,  G09F9/302 ,  G09F9/3023 ,  H05K1/141 ,  H05K3/321 ,  H05K2201/09227 ,  H05K2201/09363 ,  H05K2201/10106 ,  H05K2201/2054

    Abstract: An alphanumeric display includes a substrate that has top and bottom surfaces, a plurality of electrical contacts on the top surface, a plurality of light-emitting electronic devices mounted on the top surface, and a plurality of electrical pads on the bottom surface. The electrical contacts are connected to at least one light-emitting electronic device, and each of the light-emitting electronic devices is electrically connected with corresponding ones of the electrical contacts. The electrical pads are electrically connected to corresponding ones of the electrical contacts for communicating to the light-emitting electronic devices external sources of electrical power and control signals. The electrical pads on the bottom surface are arranged in a pattern to facilitate connections to the device using a conductive adhesive.

    Abstract translation: 字母数字显示器包括具有顶表面和底表面的基板，顶表面上的多个电触点，安装在顶表面上的多个发光电子器件以及底表面上的多个电焊盘。 电触点连接至少一个发光电子器件，并且每个发光电子器件与相应的电触点电连接。 电焊盘电连接到对应的电触头，用于与发光电子设备的外部电源和控制信号源通信。 底表面上的电焊盘以图案布置以便于使用导电粘合剂连接到装置。

    Matched-Impedance Connector Footprints
    94.
    发明申请
    Matched-Impedance Connector Footprints 有权
    匹配阻抗连接器脚印

    公开(公告)号：US20100041256A1

    公开(公告)日：2010-02-18

    申请号：US12604459

    申请日：2009-10-23

    Applicant: Danny L.C. Morlion ,  Stefaan Sercu ,  Winnie Heyvaert ,  Jan DeGeest

    Inventor： Danny L.C. Morlion ,  Stefaan Sercu ,  Winnie Heyvaert ,  Jan DeGeest

    IPC: H01R13/648

    CPC classification number: H05K1/114 ,  H05K1/0219 ,  H05K1/0237 ,  H05K2201/09227 ,  H05K2201/09236 ,  H05K2201/10189 ,  H05K2201/10734

    Abstract: Disclosed are methodologies for defining matched-impedance footprints on a substrate such as a printed circuit board, for example, that is adapted to receive an electrical component having an arrangement of terminal leads. Such a footprint may include an arrangement of electrically-conductive pads and an arrangement of electrically-conductive vias. The via arrangement may differ from the pad arrangement. The vias may be arranged to increase routing density, while limiting cross-talk and providing for matched impedance between the component and the substrate. The via arrangement may be altered to achieve a desired routing density on a layer of the board. Increasing the routing density may decrease the number of board layers, which tends to decrease capacitance and thereby increase impedance. Ground vias and signal vias may be arranged with respect to one another in such a manner as to affect impedance. Thus, the via arrangement may be altered to achieve an impedance that matches the impedance of the component. The via arrangement may be also be altered to limit cross-talk among neighboring signal conductors. Thus, the via arrangement may be defined to balance the impedance, cross-talk, and routing density requirements of the system.

    Abstract translation: 公开了用于在诸如印刷电路板的基板上定义匹配阻抗覆盖区的方法，例如适于接收具有端子引线布置的电气部件。 这种覆盖区可以包括导电焊盘的布置和导电通孔的布置。 通孔布置可以不同于衬垫布置。 通孔可以被布置成增加布线密度，同时限制串扰并且提供组件和基板之间的匹配阻抗。 可以改变通孔布置以在板的层上实现期望的布线密度。 增加布线密度可能会减少电路板层数，这往往会降低电容，从而增加阻抗。 接地通路和信号通孔可以以影响阻抗的方式相对于彼此布置。 因此，可以改变通孔布置以实现与部件的阻抗匹配的阻抗。 也可以改变通孔装置以限制相邻信号导体之间的串扰。 因此，可以定义通孔布置以平衡系统的阻抗，串扰和布线密度要求。

    Through-hole arrangement for a ball grid array package
    95.
    发明授权
    Through-hole arrangement for a ball grid array package 有权
    球栅阵列封装的通孔布置

    公开(公告)号：US07655872B2

    公开(公告)日：2010-02-02

    申请号：US11440009

    申请日：2006-05-25

    Applicant: Chun-Hung Chen ,  Yi-Hsin Peng

    Inventor： Chun-Hung Chen ,  Yi-Hsin Peng

    IPC: H01R12/04 ,  H05K1/11

    CPC classification number: H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/50 ,  H01L2924/0002 ,  H05K1/0203 ,  H05K1/0263 ,  H05K1/114 ,  H05K2201/09227 ,  H05K2201/10734 ,  H01L2924/00

    Abstract: The through holes in an array manner in the signal layer within the chip-interposed region on a substrate of a BGA package comprise a ball pads array having a plurality of ball pads and a vias array. The vias array has a plurality of vias located interlaces with the ball pads array. The outermost portions of the chip-interposed region are designed in such a manner to have at least two rings of vias for signal transmission and power connection. The interval between every two adjacent vias in the ring is not less than twice of the distance of two ball pads. Upon such an arrangement, the BGA package can have a plurality of dissipation channels that can increase dissipation space, dissipate quickly the heat generated from the IC, and transmit well for signal and power.

    Abstract translation: 在BGA封装的衬底上的芯片插入区域内的信号层中的阵列方式的通孔包括具有多个球焊盘和通孔阵列的球垫阵列。 通孔阵列具有与球垫阵列交织的多个通孔。 芯片插入区域的最外部分被设计成具有至少两个用于信号传输和电力连接的通孔环。 环中每两个相邻通孔之间的间隔不小于两个球垫距离的两倍。 在这样的布置中，BGA封装可以具有多个耗散通道，其可以增加耗散空间，快速消散由IC产生的热量，并且传输良好的信号和功率。

    Sub-mount, light emitting device including sub-mount and methods of manufacturing such sub-mount and/or light emitting device
    96.
    发明申请
    Sub-mount, light emitting device including sub-mount and methods of manufacturing such sub-mount and/or light emitting device 有权
    子安装式发光器件，包括副安装座以及制造这种子座和/或发光器件的方法

    公开(公告)号：US20090316409A1

    公开(公告)日：2009-12-24

    申请号：US12457803

    申请日：2009-06-22

    Applicant: Yu-Sik Kim ,  Woo-Sung Han

    Inventor： Yu-Sik Kim ,  Woo-Sung Han

    IPC: F21S4/00 ,  F21V19/00 ,  H01J9/24

    CPC classification number: H05K1/0295 ,  H01L25/0753 ,  H01L2224/16225 ,  H05K2201/09227 ,  H05K2201/09254 ,  H05K2201/09318 ,  H05K2201/0949 ,  H05K2201/09663 ,  H05K2201/09954 ,  H05K2201/10106 ,  H05K2203/173

    Abstract: A sub-mount adapted for AC and DC operation of devices mountable thereon, the sub-mount including a base substrate including a first surface and a second surface different from the first surface, a conductive pattern on the first surface, a first pair and a second pair of first and second electrodes on the second surface, and vias extending through the base substrate between the first and second surfaces, wherein the conductive pattern includes a first set of mounting portions and two via portions along a first electrical path between the first pair of first and second electrodes, and a second set of mounting portions and two via portions along a second electrical path between the second pair of first and second electrodes, the via portions connecting respective portions of the conductive pattern to respective electrodes of the first and second pair of first and second electrodes through the vias.

    Abstract translation: 一种用于可安装在其上的装置的AC和DC操作的子安装座，所述子安装件包括基底基板，所述基底基板包括第一表面和与所述第一表面不同的第二表面，所述第一表面上的导电图案， 在第二表面上的第二对第一和第二电极以及在第一和第二表面之间延伸通过基底基板的通孔，其中导电图案包括第一组安装部分和沿着第一对之间的第一电路径的两个通孔部分 的第一和第二电极，以及第二组安装部分和沿着第二对电极之间的第二电气路径的两个通孔部分，所述通孔部分将导电图案的各个部分连接到第一和第二电极的相应电极 一对第一和第二电极穿过通孔。

    PACKAGING SUBSTRATE HAVING PATTERN-MATCHED METAL LAYERS
    99.
    发明申请
    PACKAGING SUBSTRATE HAVING PATTERN-MATCHED METAL LAYERS 失效
    包装与图案匹配的金属层的衬底

    公开(公告)号：US20090114429A1

    公开(公告)日：2009-05-07

    申请号：US11935834

    申请日：2007-11-06

    Applicant: Sri M. Sri-Jayantha ,  Hien P. Dang ,  Vijayeshwar D. Khanna ,  Arun Sharma

    Inventor： Sri M. Sri-Jayantha ,  Hien P. Dang ,  Vijayeshwar D. Khanna ,  Arun Sharma

    IPC: H05K1/03 ,  G06F17/50 ,  H05K3/00

    CPC classification number: H05K1/0271 ,  H01L23/49833 ,  H01L23/49838 ,  H01L2924/0002 ,  H05K3/0005 ,  H05K3/4644 ,  H05K2201/09136 ,  H05K2201/09227 ,  H05K2203/1572 ,  Y10T29/49004 ,  Y10T29/49155 ,  H01L2924/00

    Abstract: A pattern matched pair of a front metal interconnect layer and a back metal interconnect layer having matched thermal expansion coefficients are provided for a reduced warp packaging substrate. Metal interconnect layers containing a high density of wiring and complex patterns are first developed so that interconnect structures for signal transmission are optimized for electrical performance. Metal interconnect layers containing a low density wiring and relatively simple patterns are then modified to match the pattern of a mirror image metal interconnect layer located on the opposite side of the core and the same number of metal interconnect layer away from the core. During this pattern-matching process, the contiguity of electrical connection in the metal layers with a low density wiring may become disrupted. The disruption is healed by an additional design step in which the contiguity of the electrical connection in the low density is reestablished.

    Abstract translation: 提供具有匹配的热膨胀系数的前金属互连层和背金属互连层的图案匹配对，用于经缩短的经向包装基板。 首先开发了包含高密度布线和复杂图案的金属互连层，使得用于信号传输的互连结构被优化用于电性能。 然后修改包含低密度布线和相对简单图案的金属互连层，以匹配位于芯的相对侧上的镜像金属互连层的图案和与芯相距相同数量的金属互连层。 在这种模式匹配过程中，具有低密度布线的金属层中的电连接的连续性可能会被破坏。 通过额外的设计步骤来治愈中断，其中重新建立低密度电连接的邻接性。

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