公开(公告)号：US20080165515A1

公开(公告)日：2008-07-10

申请号：US11970112

申请日：2008-01-07

Applicant: Shih-Ping Hsu ,  Kan-Jung Chia

Inventor： Shih-Ping Hsu ,  Kan-Jung Chia

IPC: H05K7/00

CPC classification number: H05K1/185 ,  H01L23/50 ,  H01L23/5389 ,  H01L24/19 ,  H01L2224/04105 ,  H01L2224/20 ,  H01L2224/73267 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/15787 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H05K1/053 ,  H05K1/162 ,  H05K3/4608 ,  H05K2201/09509 ,  H05K2201/09763 ,  H05K2201/10674 ,  H01L2924/00

Abstract: The present invention provides a circuit board having electronic components integrated therein, including a carrier board having an metallic oxide layer formed on each two surfaces of a metal layer, and having at least one through cavity; at least a semiconductor chip hold in the opening; at least a capacitor disposed on one surface of the carrier board, wherein the surface with the capacitor disposed thereon is at the same side with the active surface of the semiconductor chip. The capacitor is constituted of a first electrode plate disposed on partial surface of one side of the carrier board, a high dielectric material layer disposed on the surface of the first electrode plate, and a second electrode plate, paralleling and corresponding to the first electrode plate, disposed on the surface of the high dielectric material. The metal layer and the oxidation layer of the carrier board can enhance rigidity as well as tenacity and also integrate semiconductor chips and capacitors in the circuit board structure.

Abstract translation: 本发明提供了一种集成有电子部件的电路板，包括：载体板，其具有在金属层的每两个表面上形成的金属氧化物层，并具有至少一个通孔; 至少一个半导体芯片保持在开口中; 至少设置在所述载板的一个表面上的电容器，其中设置有所述电容器的所述表面与所述半导体芯片的有源表面处于同一侧。 电容器由设置在载板的一侧的部分表面上的第一电极板，设置在第一电极板的表面上的高介电材料层和与第一电极板相对应的第二电极板 ，设置在高电介质材料的表面上。 载体板的金属层和氧化层可以提高刚性和强度，并且还将半导体芯片和电容器集成在电路板结构中。

公开(公告)号：US07375022B2

公开(公告)日：2008-05-20

申请号：US11317403

申请日：2005-12-23

Applicant: Kiyoshi Oi ,  Noriyoshi Shimizu ,  Tomoo Yamasaki

Inventor： Kiyoshi Oi ,  Noriyoshi Shimizu ,  Tomoo Yamasaki

IPC: H01L21/4763

CPC classification number: H05K1/162 ,  H01L23/49822 ,  H01L23/50 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K1/113 ,  H05K3/20 ,  H05K3/4644 ,  H05K2201/096 ,  H05K2201/09763 ,  H05K2201/10674 ,  H05K2203/016 ,  H05K2203/0733 ,  H01L2924/00

Abstract: A method of manufacturing a wiring board is disclosed. The wiring board has: a capacitor, having multiple electrode layers which oppose each other with a dielectric layer in between, that is connected to a semiconductor chip; one or more via wirings which pierce the electrode layers and which are connected to the semiconductor chip, and pattern wirings connected to the via wirings. The method includes: forming the electrode layers, each having one or more through holes which the via wirings pierce, and the dielectric layer, and forming the capacitor; installing the capacitor such that the capacitor opposes the pattern wirings over an insulating layer; forming one or more via holes which reach the pattern wirings from the through holes; and forming the via wiring in the via hole.

Abstract translation: 公开了一种制造布线板的方法。 布线板具有：电容器，具有多个彼此相对的电极层，中间具有介电层，并连接到半导体芯片; 一个或多个穿透电极层并且连接到半导体芯片的通孔布线以及连接到通孔布线的图案布线。 该方法包括：形成各自具有通孔布线穿过的一个或多个通孔的电极层和电介质层，并形成电容器; 安装电容器使得电容器与绝缘层上的图案布线相对; 形成从通孔到达图案布线的一个或多个通孔; 以及在通孔中形成通孔布线。

公开(公告)号：US20080100986A1

公开(公告)日：2008-05-01

申请号：US11907563

申请日：2007-10-15

Applicant: Seung Hyun Sohn ,  Yul Kyo Chung ,  Sung Taek Lim ,  Hyung Mi Jung

Inventor： Seung Hyun Sohn ,  Yul Kyo Chung ,  Sung Taek Lim ,  Hyung Mi Jung

IPC: H01G4/00 ,  H01L21/20

CPC classification number: H01G4/33 ,  H01G4/228 ,  H05K1/162 ,  H05K3/388 ,  H05K3/4069 ,  H05K3/4652 ,  H05K2201/0179 ,  H05K2201/035 ,  H05K2201/09509 ,  H05K2201/09763

Abstract: Provided is a method of manufacturing a capacitor embedded printed circuit board. In the method, a laminated body is prepared, including a laminated plate having first and second copper films on both sides thereof, where at least one bottom electrode is provided on at least one side. A dielectric layer is formed on the at least one bottom electrode. A metal layer is formed on a top surface of the dielectric layer where a capacitor is to be formed. A conductive paste layer is formed on at least one region of a top surface of the metal layer, where the conductive paste layer and the metal layer is provided as a top electrode. An insulation resin layers are formed on both sides of the laminated plate, respectively. A conductive via is formed in the insulation resin layer such that it is connected to the conductive paste layer.

Abstract translation: 提供一种制造电容器嵌入式印刷电路板的方法。 在该方法中，制备层压体，其包括其两侧具有第一和第二铜膜的层压板，其中在至少一侧上设置有至少一个底部电极。 在所述至少一个底部电极上形成介电层。 在要形成电容器的电介质层的顶表面上形成金属层。 在金属层的顶表面的至少一个区域上形成导电浆料层，其中导电浆料层和金属层设置为顶部电极。 绝缘树脂层分别形成在层压板的两侧。 导电通孔形成在绝缘树脂层中，使其与导电糊层连接。

公开(公告)号：US20080030968A1

公开(公告)日：2008-02-07

申请号：US11882646

申请日：2007-08-03

Applicant: Naohiro Mashino

Inventor： Naohiro Mashino

IPC: H05K7/02 ,  H01G13/00

CPC classification number: H01L23/50 ,  H01G4/236 ,  H01G4/33 ,  H01G4/38 ,  H01L21/486 ,  H01L23/49827 ,  H01L23/642 ,  H01L2224/16225 ,  H01L2224/16268 ,  H01L2224/81192 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19103 ,  H05K1/162 ,  H05K2201/0367 ,  H05K2201/09763 ,  H05K2201/10378 ,  Y10T29/435

Abstract: A capacitor built-in interposer of the present invention, includes a base resin layer, a capacitor first electrode provided to pass through the base resin layer and having projection portions projected from both surface sides of the base resin layer respectively whereby the projection portion on one surface side of the base resin layer serves as a connection portion, a capacitor dielectric layer for covering the projection portion of the first electrode on other surface side of the base resin layer, and a capacitor second electrode for covering the dielectric layer, wherein a plurality of capacitors each constructed by the first electrode, the dielectric layer, and the second electrode are arranged and aligned in a lateral direction in a state that the capacitors are passed through the base resin layer.

Abstract translation: 本发明的电容器内置插入件包括基底树脂层，设置成穿过基底树脂层并具有从基底树脂层的两个表面侧突出的突出部分的电容器第一电极，其中突出部分在一个 基础树脂层的表面侧用作连接部分，用于覆盖基础树脂层的另一表面侧上的第一电极的突出部分的电容器电介质层和用于覆盖电介质层的电容器第二电极，其中多个 每个由第一电极，电介质层和第二电极构成的电容器在电容器通过基础树脂层的状态下沿横向排列和排列。

公开(公告)号：US20080010798A1

公开(公告)日：2008-01-17

申请号：US11486837

申请日：2006-07-14

Applicant: William J. Borland ,  Patrick Daniels ,  Dean W. Face ,  Jon Fredrick Ihlefeld ,  Jon-Paul Maria

Inventor： William J. Borland ,  Patrick Daniels ,  Dean W. Face ,  Jon Fredrick Ihlefeld ,  Jon-Paul Maria

IPC: H01G7/00 ,  H01G4/06 ,  H01L21/20 ,  H05K3/10

CPC classification number: H01G4/1218 ,  H01G4/005 ,  H05K1/162 ,  H05K3/1291 ,  H05K2201/0355 ,  H05K2201/09763 ,  H05K2203/1126 ,  Y10T29/435 ,  Y10T29/49155

Abstract: Methods of making capacitors are disclosed that comprise forming a dielectric layer over a substrate with a first electrode or a bare metallic foil, depositing a top conductive layer over the dielectric layer, and annealing the dielectric layer and the top conductive layer wherein the foil or first electrode, the dielectric, and the conductive layer form a capacitor.

Abstract translation: 公开了制造电容器的方法，其包括用第一电极或裸金属箔在衬底上形成介电层，在电介质层上沉积顶部导电层，以及退火介电层和顶部导电层，其中箔或第一 电极，电介质和导电层形成电容器。

公开(公告)号：US07314780B2

公开(公告)日：2008-01-01

申请号：US11145924

申请日：2005-06-07

Applicant: Noriyoshi Shimizu ,  Akio Rokugawa ,  Takahiro Iijima

Inventor： Noriyoshi Shimizu ,  Akio Rokugawa ,  Takahiro Iijima

IPC: H01L23/48

CPC classification number: H05K1/162 ,  H01L23/49822 ,  H01L23/49833 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/15312 ,  H05K1/112 ,  H05K3/4602 ,  H05K2201/0187 ,  H05K2201/0209 ,  H05K2201/09763 ,  H05K2203/135 ,  H01L2224/05599

Abstract: A semiconductor package, provided with a multilayer interconnect structure, for mounting a semiconductor chip on its top surface, wherein a topmost stacked structure of the multilayer interconnect structure includes a capacitor structure, the capacitor structure having a dielectric layer comprised of a mixed electrodeposited layer of high dielectric constant inorganic filler and insulating resin and including chip connection pads for directly connecting top electrodes and bottom electrodes with electrodes of the semiconductor chip, whereby greater freedom in design of interconnect patterns can be secured, the degree of proximity of the capacitor and semiconductor chip can be greatly improved, and the package can be made smaller and lighter in weight, a method of production of the same, and a semiconductor device using this semiconductor package.

Abstract translation: 一种半导体封装，其具有多层互连结构，用于将半导体芯片安装在其顶表面上，其中所述多层互连结构的最上层堆叠结构包括电容器结构，所述电容器结构具有介电层，所述电介质层由混合电沉积层 高介电常数无机填料和绝缘树脂，并且包括用于直接连接具有半导体芯片电极的顶电极和底电极的芯片连接焊盘，从而可以确保互连图案设计的更大自由度，电容器和半导体芯片的接近程度 可以大大改善，并且可以使包装重量更小更轻，其制造方法以及使用该半导体封装的半导体器件。

公开(公告)号：US07310238B2

公开(公告)日：2007-12-18

申请号：US11498070

申请日：2006-08-03

Applicant: Kiyotaka Tsukada

Inventor： Kiyotaka Tsukada

IPC: H05K1/18

CPC classification number: H01G4/33 ,  H01G4/008 ,  H01G4/1218 ,  H05K1/162 ,  H05K3/025 ,  H05K3/143 ,  H05K3/4614 ,  H05K3/462 ,  H05K3/4652 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/0317 ,  H05K2201/0355 ,  H05K2201/068 ,  H05K2201/09763

Abstract: The present invention provides a thin-film embedded capacitance having a substantial electrostatic capacity per unit area, and a method for manufacturing thereof.A thin film embedded capacitance comprising: a metallic thin-film for wiring made of a metallic material in a non-yield state; the first electrode formed on the film for wiring; a dielectric material layer formed on the first electrode and the film for wiring, at a temperature not lower than ordinary room temperature to lower than a yield temperature of the film for wiring, having a coefficient of thermal expansion lower than that the film for wiring; and the second electrode formed on the dielectric material layer, and a method for manufacturing thereof.

Abstract translation: 本发明提供了具有每单位面积的显着静电容量的薄膜嵌入式电容及其制造方法。 一种薄膜嵌入式电容器，包括：用于非金属材料制成的布线的金属薄膜; 形成在用于布线的膜上的第一电极; 在不低于普通室温至低于布线用膜的屈服温度的温度下形成的第一电极和布线用电介质材料层，其热膨胀系数低于布线用膜; 和形成在电介质材料层上的第二电极及其制造方法。

公开(公告)号：US20070244267A1

公开(公告)日：2007-10-18

申请号：US11401150

申请日：2006-04-10

Applicant: Thomas Dueber ,  John Summers ,  William Borland ,  Olga Renovales ,  Diptarka Majumdar ,  Daniel Amey

Inventor： Thomas Dueber ,  John Summers ,  William Borland ,  Olga Renovales ,  Diptarka Majumdar ,  Daniel Amey

IPC: C08L63/00

CPC classification number: H05K1/162 ,  C08G59/24 ,  C08G59/621 ,  H05K2201/0187 ,  H05K2201/0355 ,  H05K2201/09763

Abstract: Compositions comprising: an epoxy containing cyclic olefin resin with a water absorption of 2% or less; one or more phenolic resins with water absorption of less than 2% or less; an epoxy catalyst; optionally one or more of an electrically insulated filler, a defoamer and a colorant and one or more organic solvents. The compositions are useful as encapsulants and have a cure temperature of 190° C. or less.

Abstract translation: 组合物，其包含：含有环氧树脂的环状烯烃树脂，其吸水率为2％以下; 一种或多种吸水率小于2％的酚醛树脂; 环氧催化剂; 任选地一种或多种电绝缘填料，消泡剂和着色剂以及一种或多种有机溶剂。 该组合物可用作密封剂并具有190℃或更低的固化温度。

公开(公告)号：US20070158818A1

公开(公告)日：2007-07-12

申请号：US11323312

申请日：2005-12-30

Applicant: John Tang ,  Xiang Zeng ,  Jiangqi He ,  Ding Hai

Inventor： John Tang ,  Xiang Zeng ,  Jiangqi He ,  Ding Hai

IPC: H01L23/52

CPC classification number: H01L21/4857 ,  H01L23/49822 ,  H01L23/50 ,  H01L24/48 ,  H01L24/49 ,  H01L24/81 ,  H01L24/85 ,  H01L2224/05553 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/32225 ,  H01L2224/48472 ,  H01L2224/49 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81801 ,  H01L2224/83102 ,  H01L2224/85 ,  H01L2224/92125 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01068 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/10162 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/19041 ,  H05K1/111 ,  H05K1/113 ,  H05K1/162 ,  H05K3/28 ,  H05K2201/0187 ,  H05K2201/09436 ,  H05K2201/09763 ,  H05K2201/10674 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00

Abstract: An article includes a top electrode that is embedded in a solder mask. An article includes a top electrode that is on a core structure. A process of forming the top electrode includes reducing the solder mask thickness and forming the top electrode on the reduced-thickness solder mask. A process of forming the top electrode includes forming the top electrode over a high-K dielectric that is in a patterned portion of the core structure.

Abstract translation: 一种物品包括埋在焊接掩模中的顶部电极。 一种物品包括在核心结构上的顶部电极。 形成顶部电极的工艺包括减小焊接掩模厚度并在厚度较薄的焊接掩模上形成顶部电极。 形成顶部电极的工艺包括在位于芯结构的图案化部分中的高K电介质上形成顶部电极。

公开(公告)号：US20070146941A1

公开(公告)日：2007-06-28

申请号：US11679061

申请日：2007-02-26

Applicant: EDWIN HARRIS ,  Tushar Vyas ,  Timothy Pachla

Inventor： EDWIN HARRIS ,  Tushar Vyas ,  Timothy Pachla

IPC: H02H9/00

CPC classification number: H01C7/12 ,  H01G2/14 ,  H02H9/044 ,  H05K1/0257 ,  H05K1/0259 ,  H05K1/0298 ,  H05K1/0393 ,  H05K1/167 ,  H05K3/28 ,  H05K2201/0738 ,  H05K2201/09763

Abstract: A first voltage variable material (“VVM”) includes an insulative binder, first conductive particles with a core and a shell held in the insulating binder and second conductive particles without a shell held in the insulating binder; a second VVM includes an insulating binder, first conductive particles with a core and a shell held in the insulating binder, second conductive particles without a shell held in the insulating binder, and semiconductive particles with a core and a shell held in the insulating binder; a third VVM includes only first conductive particles with a core and a shell held in the insulating binder.

Abstract translation: 第一电压可变材料（“VVM”）包括绝缘粘合剂，具有芯和保持在绝缘粘合剂中的壳的第一导电颗粒和没有保持在绝缘粘合剂中的壳的第二导电颗粒; 第二VVM包括绝缘粘合剂，具有芯和保持在绝缘粘合剂中的壳的第一导电颗粒，没有保持在绝缘粘合剂中的壳的第二导电颗粒和保持在绝缘粘合剂中的芯和壳的半导体颗粒; 第三VVM仅包括具有芯和保持在绝缘粘合剂中的壳的第一导电颗粒。