中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

509 records (took 0.026 seconds)

    Simultaneous and selective partitioning of via structures using plating resist
    93.
    发明授权
    Simultaneous and selective partitioning of via structures using plating resist 有权
    使用电镀抗蚀剂同时选择性地分配通孔结构

    公开(公告)号：US08222537B2

    公开(公告)日：2012-07-17

    申请号：US12483223

    申请日：2009-06-11

    Applicant: George Dudnikov, Jr. ,  Franz Gisin

    Inventor： George Dudnikov, Jr. ,  Franz Gisin

    IPC: H05K1/11

    CPC classification number: H05K3/429 ,  H05K1/0257 ,  H05K1/0259 ,  H05K1/116 ,  H05K1/167 ,  H05K3/184 ,  H05K3/422 ,  H05K2201/0187 ,  H05K2201/0738 ,  H05K2201/096 ,  H05K2201/09645 ,  H05K2201/09718 ,  H05K2201/09881 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49139 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165

    Abstract: Systems and methods for simultaneously partitioning a plurality of via structures into electrically isolated portions by using plating resist within a PCB stackup are disclosed. Such via structures are made by selectively depositing plating resist in one or more locations in a sub-composite structure. A plurality of sub-composite structures with plating resist deposited in varying locations are laminated to form a PCB stackup of a desired PCB design. Through-holes are drilled through the PCB stackup through conductive layers, dielectric layers and through the plating resist. Thus, the PCB panel has multiple through-holes that can then be plated simultaneously by placing the PCB panel into a seed bath, followed by immersion in an electroless copper bath. Such partitioned vias increase wiring density and limit stub formation in via structures. Such partitioned vias allow a plurality of electrical signals to traverse each electrically isolated portion without interference from each other.

    Abstract translation: 公开了通过在PCB堆叠中使用电镀抗蚀剂将多个通孔结构同时分隔成电隔离部分的系统和方法。 通过在子复合结构中的一个或多个位置选择性地沉积电镀抗蚀剂来制造这种通孔结构。 具有在不同位置沉积的电镀抗蚀剂的多个亚复合结构层压以形成期望的PCB设计的PCB堆叠。 通过PCB堆叠穿过导电层，电介质层和通过电镀抗蚀剂钻穿孔。 因此，PCB面板具有多个通孔，然后可以通过将PCB面板放置在种子池中，然后浸入无电解铜浴中而同时进行电镀。 这种分隔的通孔增加布线密度并限制通孔结构中的短截线形成。 这种分隔的通孔允许多个电信号穿过每个电隔离部分而没有彼此的干扰。

    Printed circuit board having electromagnetic bandgap structure
    97.
    发明申请
    Printed circuit board having electromagnetic bandgap structure 有权
    具有电磁带隙结构的印刷电路板

    公开(公告)号：US20110067917A1

    公开(公告)日：2011-03-24

    申请号：US12654526

    申请日：2009-12-22

    Applicant: Dae-Hyun Park ,  Han Kim ,  Kang-Wook Bong

    Inventor： Dae-Hyun Park ,  Han Kim ,  Kang-Wook Bong

    IPC: H05K9/00

    CPC classification number: H05K1/0236 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H05K1/0231 ,  H05K1/024 ,  H05K2201/0187 ,  H05K2201/09627 ,  H05K2201/09881 ,  H01L2924/00014

    Abstract: Disclosed is a printed circuit board including an electromagnetic bandgap structure. The electromagnetic bandgap structure, which includes a first dielectric material for interlayer insulation and is for blocking a noise, is inserted into the printed circuit board. The electromagnetic bandgap structure can include a first conductive plate, a second conductive plate arranged on a planar surface that is different from that of the first conductive plate, a third conductive plate arranged on a same planar surface as the first conductive plate, and a stitching via unit configured to connect the first conductive plate and the third conductive plate through the planar surface on which the second conductive plate is arranged. A second dielectric material having a permittivity that is different from that of the first dielectric material is interposed between any two of the first conductive plate, the second conductive plate, and the third conductive plate.

    Abstract translation: 公开了一种包括电磁带隙结构的印刷电路板。 包括用于层间绝缘并用于阻挡噪声的第一介电材料的电磁带隙结构被插入到印刷电路板中。 电磁带隙结构可以包括第一导电板，布置在与第一导电板不同的平面上的第二导电板，布置在与第一导电板相同的平坦表面上的第三导电板，以及缝合 通孔单元被配置为通过其上布置有第二导电板的平面连接第一导电板和第三导电板。 具有不同于第一介电材料的介电常数的第二介电材料插入在第一导电板，第二导电板和第三导电板中的任何两个之间。

    Method for forming a wire bonding substrate
    98.
    发明授权
    Method for forming a wire bonding substrate 失效
    用于形成引线接合基板的方法

    公开(公告)号：US07877873B2

    公开(公告)日：2011-02-01

    申请号：US12109307

    申请日：2008-04-24

    Applicant: Meng-Han Lee ,  Hung-En Hsu ,  Wei-Wen Lan ,  Yun-Hsiang Pai

    Inventor： Meng-Han Lee ,  Hung-En Hsu ,  Wei-Wen Lan ,  Yun-Hsiang Pai

    IPC: H01K3/10

    CPC classification number: H05K3/243 ,  H01L2224/16 ,  H01L2924/01078 ,  H01L2924/01079 ,  H05K3/28 ,  H05K3/42 ,  H05K2201/09881 ,  H05K2203/0723 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49144 ,  Y10T29/49165

    Abstract: A method for forming a wire bonding substrate is disclosed. A substrate comprising a first surface and a second surface is provided. A through hole is formed in the substrate. A conductive layer is formed on the first surface and the second surface of the substrate and covers a sidewall of the through hole. The conductive layer on the first surface of the substrate is patterned to form at least a first conductive pad, and the conductive layer on the second surface of the substrate is patterned to form at least a second conductive pad. An insulating layer is formed on the first surface and the second surface of the substrate and covers the first conductive pad and the second conductive pad. The insulating layer is recessed until top surfaces of the first conductive pad and the second conductive pad are exposed. A first metal layer is electroplated on the first conductive pad by applying current from the second conductive pad to the first conductive pad through the conductive layer passing the through hole.

    Abstract translation: 公开了一种用于形成引线键合衬底的方法。 提供了包括第一表面和第二表面的基底。 在基板上形成通孔。 在基板的第一表面和第二表面上形成导电层并且覆盖通孔的侧壁。 将衬底的第一表面上的导电层图案化以形成至少第一导电焊盘，并且将衬底的第二表面上的导电层图案化以形成至少第二导电焊盘。 在基板的第一表面和第二表面上形成绝缘层，并覆盖第一导电焊盘和第二导电焊盘。 绝缘层凹入，直到第一导电焊盘和第二导电焊盘的顶表面露出。 通过通过通孔的导电层将来自第二导电焊盘的电流施加到第一导电焊盘，使第一金属层电镀在第一导电焊盘上。

    Metal core multi-LED SMD package and method of producing the same
    99.
    发明授权
    Metal core multi-LED SMD package and method of producing the same 失效
    金属芯多LED SMD封装及其制造方法

    公开(公告)号：US07868347B2

    公开(公告)日：2011-01-11

    申请号：US12404309

    申请日：2009-03-15

    Applicant: Lijun Cui

    Inventor： Lijun Cui

    IPC: H01L33/62

    CPC classification number: H05K3/202 ,  H01L33/486 ,  H01L2924/0002 ,  H05K3/06 ,  H05K2201/09118 ,  H05K2201/09881 ,  H05K2201/09972 ,  H05K2201/10106 ,  H05K2203/0369 ,  H05K2203/1476 ,  H01L2924/00

    Abstract: A new SMD (surface mount devices) package design for efficiently removing heat from LED Chip(s) is involved in this invention. Different from the regular SMD package, which electrical isolated materials like Alumina or AlN are used, the substrate material here is metal like Copper, Aluminum and so on. Also, different from regular design, which most time only has one LED chip inside, current design will at least have two or more LED chips (or chip groups) in one package. All chips are electrical connected via metal blocks, traces or wire-bond. This type of structure is generally fabricated via chemical etching and then filled with dielectric material inside to form a strong package. Because the thermal conductivity of the metal is much higher than the ceramics, the package thermal resistance is much lower than the ceramics based package. Also, the cost of the package is much lower than ceramics package. Moreover, emitting area in one package is much larger than the current arts.

    Abstract translation: 本发明涉及用于有效地从LED芯片去除热量的新的SMD（表面贴装器件）封装设计。 与常规SMD封装不同，使用了诸如氧化铝或AlN的电隔离材料，这里的基板材料是金属如铜，铝等。 此外，与常规设计不同的是，大多数时间内只有一个LED芯片，目前的设计将至少在一个封装中有两个或更多个LED芯片（或芯片组）。 所有芯片通过金属块，迹线或线接电连接。 这种类型的结构通常通过化学蚀刻制造，然后在其内填充介电材料以形成强封装。 由于金属的导热率远高于陶瓷，所以封装的热阻远低于陶瓷封装。 此外，封装的成本远低于陶瓷封装。 此外，一个封装中的发光面积远远大于当前的技术。

Patent Agency Ranking