公开(公告)号：US08963675B2

公开(公告)日：2015-02-24

申请号：US13644964

申请日：2012-10-04

Applicant: Chipbond Technology Corporation

Inventor： Chih-Ming Kuo ,  You-Ming Hsu

IPC: H01F5/00 ,  H01F27/28 ,  H05K1/16 ,  H05K3/46

CPC classification number: H01F5/00 ,  H01F5/003 ,  H05K1/165 ,  H05K3/465 ,  H05K2201/097 ,  Y10T29/4902 ,  Y10T29/49069 ,  Y10T29/49071 ,  Y10T29/49073 ,  Y10T29/49155

Abstract: A method for fabricating a carrier with a three-dimensional inductor comprises the steps of providing a substrate having a protective layer; forming a first photoresist layer on the protective layer; patterning the first photoresist layer to form a second opening and a plurality of disposing slots; forming a first metal layer in second opening and disposing slots; removing the first photoresist layer; forming a first dielectric layer on the protective layer; forming a second photoresist layer on the first dielectric layer; patterning the second photoresist layer to form a plurality of slots; forming a second metal layer in slots to form a plurality of inductive portions; removing the second photoresist layer; forming a second dielectric layer on the first dielectric layer; forming a third photoresist layer on the second dielectric layer; patterning the third photoresist layer to form a plurality of slots; and forming a third metal layer in slots.

Abstract translation: 一种制造具有三维电感器的载体的方法包括以下步骤：提供具有保护层的衬底; 在保护层上形成第一光致抗蚀剂层; 图案化第一光致抗蚀剂层以形成第二开口和多个布置槽; 在第二开口中形成第一金属层并设置槽; 去除第一光致抗蚀剂层; 在所述保护层上形成第一介电层; 在所述第一介电层上形成第二光致抗蚀剂层; 图案化第二光致抗蚀剂层以形成多个槽; 在槽中形成第二金属层以形成多个感应部分; 去除所述第二光致抗蚀剂层; 在所述第一电介质层上形成第二电介质层; 在所述第二介电层上形成第三光致抗蚀剂层; 图案化第三光致抗蚀剂层以形成多个狭缝; 以及在槽中形成第三金属层。

公开(公告)号：US08877629B2

公开(公告)日：2014-11-04

申请号：US13743450

申请日：2013-01-17

Applicant: Chipbond Technology Corporation

Inventor： Cheng-Hung Shih ,  Yung-Wei Hsieh ,  Kai-Yi Wang

IPC: H01L21/44 ,  H01L23/498 ,  H01L21/768 ,  H01L23/00

CPC classification number: H01L23/562 ,  H01L23/3171 ,  H01L23/3192 ,  H01L23/48 ,  H01L23/49811 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0361 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05166 ,  H01L2224/05558 ,  H01L2224/05572 ,  H01L2224/0558 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2924/00014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01074 ,  H01L2924/014

Abstract: A semiconductor manufacturing process includes the following steps of providing a silicon substrate having at least one connection pad and a protection layer, forming a first seed layer having at least one first section and at least one second section, forming a first photoresist layer, forming a first buffer layer having a coupling portion and a cladding portion, removing the first photoresist layer, removing the second section of the first seed layer to form a first under bump metallurgy layer, forming a support layer on the protection layer and the first buffer layer, the first under bump metallurgy layer has a first ring wall, the first buffer layer has a second ring wall, wherein the first ring wall, the second ring wall and the cladding portion are cladded by the support layer, and forming a connection portion and covering the coupling portion with the connection portion.

Abstract translation: 半导体制造方法包括以下步骤：提供具有至少一个连接焊盘和保护层的硅衬底，形成具有至少一个第一部分和至少一个第二部分的第一种子层，形成第一光致抗蚀剂层，形成第 第一缓冲层，具有耦合部分和包层部分，去除第一光致抗蚀剂层，去除第一种子层的第二部分以形成第一凸块下金属层，在保护层和第一缓冲层上形成支撑层， 所述第一凸块下金属层具有第一环壁，所述第一缓冲层具有第二环壁，所述第一环壁，所述第二环壁和所述包层部由所述支撑层包覆，并且形成连接部和覆盖层 与连接部分的联接部分。

公开(公告)号：US08841767B2

公开(公告)日：2014-09-23

申请号：US13852663

申请日：2013-03-28

Applicant: Chipbond Technology Corporation

Inventor： Chin-Tang Hsieh ,  Chih-Ming Kuo

IPC: H01L23/48 ,  H01L23/52 ,  H01L23/00 ,  H05K1/11 ,  H01L23/498 ,  H01L21/48

CPC classification number: H05K1/111 ,  H01L21/4846 ,  H01L23/3192 ,  H01L23/49811 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0347 ,  H01L2224/03912 ,  H01L2224/03914 ,  H01L2224/0401 ,  H01L2224/05147 ,  H01L2224/05541 ,  H01L2224/05547 ,  H01L2224/05556 ,  H01L2224/05557 ,  H01L2224/05565 ,  H01L2224/05567 ,  H01L2224/05578 ,  H01L2224/05583 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05687 ,  H01L2224/1147 ,  H01L2224/11912 ,  H01L2224/13005 ,  H01L2224/13006 ,  H01L2224/13017 ,  H01L2224/13018 ,  H01L2224/13022 ,  H01L2224/13083 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13565 ,  H01L2224/13687 ,  H01L2924/00014 ,  H01L2924/301 ,  H01L2924/384 ,  Y10T428/12396 ,  H01L2924/00012 ,  H01L2924/05042 ,  H01L2924/05442 ,  H01L2924/058 ,  H01L2224/05552

Abstract: A bumping process comprises steps of forming a metal layer with copper on a substrate, and the metal layer with copper comprises a plurality of first zones and second zones; forming a photoresist layer on the metal layer with copper; patterning the photoresist layer to form a plurality of openings; forming a plurality of copper bumps within the openings, each of the copper bumps covers the first zones and comprises a first top surface; forming a connection layer on the first top surface; removing the photoresist layer; removing the second zones and enabling each of the first zones to form an under bump metallurgy layer, wherein the under bump metallurgy layer, the copper bump, and the connection layer possess their corresponded peripheral walls, and covering sections of a first protective layer formed on the connection layer may cover those peripheral walls to prevent ionization phenomenon.

Abstract translation: 凸起工艺包括在基底上形成具有铜的金属层的步骤，并且具有铜的金属层包括多个第一区域和第二区域; 用铜在金属层上形成光致抗蚀剂层; 图案化光致抗蚀剂层以形成多个开口; 在所述开口内形成多个铜凸块，每个所述铜凸块覆盖所述第一区域并且包括第一顶表面; 在所述第一顶表面上形成连接层; 去除光致抗蚀剂层; 去除所述第二区域并且使得所述第一区域中的每一个形成凸起下冶金层，其中所述凸起下的冶金层，所述铜凸块和所述连接层具有其对应的周壁，以及覆盖在第一区上形成的第一保护层的覆盖部分 连接层可以覆盖那些外围壁以防止电离现象。

公开(公告)号：US20140097540A1

公开(公告)日：2014-04-10

申请号：US13677518

申请日：2012-11-15

Applicant: CHIPBOND TECHNOLOGY CORPORATION

Inventor： Hsiang-Chin Chiu ,  Sheng-Ming Wu ,  Kuang-Hao Yang ,  Kung-An Lin ,  Chen-Yu Wang

IPC: H01L23/373 ,  H01L23/482

CPC classification number: H01L23/3735 ,  H01L21/6836 ,  H01L23/36 ,  H01L23/3736 ,  H01L23/4827 ,  H01L24/05 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/04026 ,  H01L2224/05083 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05639 ,  H01L2924/10253

Abstract: A semiconductor structure includes a silicon substrate, a titanium layer, a nickel layer, a silver layer and a metallic adhesion layer, wherein the silicon substrate comprises a back surface, and the titanium layer comprises an upper surface. The titanium layer is formed on the back surface, the nickel layer is formed on the upper surface, the silver layer is formed on the nickel layer, and the metallic adhesion layer is formed between the nickel layer and the silver layer.

Abstract translation: 半导体结构包括硅衬底，钛层，镍层，银层和金属粘合层，其中硅衬底包括背面，并且钛层包括上表面。 钛层形成在背面，镍层形成在上表面，银层形成在镍层上，并且金属粘合层形成在镍层和银层之间。

公开(公告)号：US08476159B2

公开(公告)日：2013-07-02

申请号：US13644882

申请日：2012-10-04

Applicant: Chipbond Technology Corporation

Inventor： Chin-Tang Hsieh

IPC: H01L21/44

CPC classification number: H01L24/14 ,  H01L21/4853 ,  H01L23/49811 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05027 ,  H01L2224/05562 ,  H01L2224/11618 ,  H01L2224/1182 ,  H01L2224/13013 ,  H01L2224/13017 ,  H01L2224/13022 ,  H01L2224/13027 ,  H01L2224/13144 ,  H01L2224/1319 ,  H01L2224/13541 ,  H01L2224/13551 ,  H01L2224/13562 ,  H01L2224/13566 ,  H01L2224/136 ,  H01L2224/1411 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2924/00014 ,  H01L2924/15787 ,  H01L2924/15788 ,  H05K1/11 ,  H05K3/4007 ,  H05K2201/0367 ,  H01L2924/00015 ,  H01L2924/00012 ,  H01L2224/05552 ,  H01L2924/00

Abstract: A substrate structure with compliant bump comprises a substrate, a plurality of bumps, and a metallic layer, wherein the substrate comprises a surface, a trace layer, and a protective layer. The trace layer comprises a plurality of conductive pads, and each of the conductive pads comprises an upper surface. The protective layer comprises a plurality of openings. The bumps are formed on the surface, and each of the bumps comprises a top surface, an inner surface and an outer surface and defines a first body and a second body. The first body is located on the surface. The second body is located on top of the first body. The metallic layer is formed on the top surface, the inner surface, and the upper surface.

公开(公告)号：US20130127578A1

公开(公告)日：2013-05-23

申请号：US13739210

申请日：2013-01-11

Applicant: Chipbond Technology Corporation

Inventor： Chih-Ming Kuo ,  You-Ming Hsu

IPC: H01F5/00

CPC classification number: H01L23/48 ,  H01F5/00 ,  H01F5/003 ,  H01F17/0033 ,  H01F41/046 ,  H01L28/10

Abstract: A method for fabricating a inductor carrier comprises the steps of providing a substrate with a protective layer; forming a first photoresist layer on protective layer; patterning the first photoresist layer to form a first opening and first apertures; forming a first metal layer within first opening and first apertures; removing the first photoresist layer; forming a first dielectric layer on protective layer; forming a second photoresist layer on first dielectric layer; patterning the second photoresist layer to form a second aperture and a plurality of third apertures; forming a second metal layer within second aperture and third apertures; removing the second photoresist layer; forming a second dielectric layer on first dielectric layer; forming a third photoresist layer on second dielectric layer; patterning the third photoresist layer to form a fifth aperture and sixth apertures; forming a third metal layer within fifth aperture and sixth apertures.

公开(公告)号：US20250142719A1

公开(公告)日：2025-05-01

申请号：US18909469

申请日：2024-10-08

Applicant: Chipbond Technology Corporation

Inventor： Chiu-Hong Lai ,  Wen Ping Hsu ,  Yi Ling Hsieh ,  Dong-Sheng Li ,  Yi Ren Chian ,  San Lee ,  Pei-Ying Lee ,  Ting-Yi Kuo

IPC: H05K1/02 ,  H05K1/09 ,  H05K1/18

Abstract: A flexible circuit board designed for chip integration is provided. The flexible circuit board includes an insulating substrate, a conductive copper layer, a first tin layer, a second tin layer, and a first solder resist layer. The first tin layer has a first tin thickness, and the second tin layer has a greater second tin thickness. A first tin surface of the first tin layer and a second tin surface of the second tin layer are substantially level.

公开(公告)号：US12224734B2

公开(公告)日：2025-02-11

申请号：US17856036

申请日：2022-07-01

Applicant: CHIPBOND TECHNOLOGY CORPORATION

Inventor： Cheng-Hung Shih ,  Cheng-Fan Lin

IPC: H03H3/08 ,  H03H9/02 ,  H03H9/05 ,  H03H9/145 ,  H10N30/87

Abstract: A surface acoustic wave device includes a piezoelectric substrate, a supportive layer, a cover layer and a pillar bump. The supportive layer is disposed on the piezoelectric substrate and around a transducer, the cover layer covers the supportive layer, and the pillar bump is located in a lower via hole of the supportive layer and an upper via hole of the cover layer. The upper via hole has a lateral opening located on a lateral surface of the cover layer, and the pillar bump in the cover layer protrudes from the lateral surface of the cover layer via the lateral opening.

公开(公告)号：US12224183B2

公开(公告)日：2025-02-11

申请号：US17896171

申请日：2022-08-26

Applicant: CHIPBOND TECHNOLOGY CORPORATION

Inventor： Shrane-Ning Jenq ,  Wen-Cheng Hsu ,  Chen-Yu Wang ,  Chih-Ming Kuo ,  Chwan-Tyaw Chen ,  Lung-Hua Ho

IPC: H01L21/48 ,  C23C18/54 ,  C23C28/02 ,  C25D7/12 ,  H01L21/311 ,  H01L21/3213 ,  H01L23/498 ,  H01L23/00

Abstract: A package including a first carrier, a seed layer, wires, a die and a molding material is provided. The first carrier is removed to expose the seed layer after disposing a second carrier on the molding material, then the seed layer is removed to expose the wires, and a gold layer is deposited on each of the wires by immersion gold plating, finally a semiconductor device is obtained. The gold layer is provided to protect the wires from oxidation and improve solder joint reliability.

公开(公告)号：US20240371741A1

公开(公告)日：2024-11-07

申请号：US18614963

申请日：2024-03-25

Applicant: CHIPBOND TECHNOLOGY CORPORATION

Inventor： Hou-Chang Kuo ,  Wen-Ping Hsu ,  Ting-Yi Kuo ,  Yi-Ling Hsieh

IPC: H01L23/498

Abstract: A layout structure of a flexible circuit board includes a flexible substrate, a circuit layer and a dummy circuit layer which are arranged on the flexible substrate. The circuit layer includes first inner leads, second inner leads, an inverted U-shape connection line and a horizontal inner lead. A first distance between the first inner leads is less than a second distance between the second inner leads. One of dummy leads of the dummy circuit layer is located between the first and second inner leads, another dummy lead is located between the second inner leads. The dummy leads are provided to allow lead spaces on both sides of the inverted U-shape connection line is the same. Thus, etching solution will not flow laterally in an etching space between the inverted U-shape connection line and the horizontal inner lead.