公开(公告)号：US06287885B1

公开(公告)日：2001-09-11

申请号：US09306381

申请日：1999-05-06

Applicant: Hiroshi Muto ,  Tsuyoshi Fukada ,  Masakazu Terada ,  Hiroshige Sugito ,  Masakazu Kanosue ,  Shinji Yoshihara ,  Shoji Ozoe ,  Seiji Fujino ,  Minekazu Sakai ,  Minoru Murata ,  Yukihiro Takeuchi ,  Seiki Aoyama ,  Toshio Yamamoto ,  Kazushi Asami

Inventor： Hiroshi Muto ,  Tsuyoshi Fukada ,  Masakazu Terada ,  Hiroshige Sugito ,  Masakazu Kanosue ,  Shinji Yoshihara ,  Shoji Ozoe ,  Seiji Fujino ,  Minekazu Sakai ,  Minoru Murata ,  Yukihiro Takeuchi ,  Seiki Aoyama ,  Toshio Yamamoto ,  Kazushi Asami

IPC: H01L21302

CPC classification number: B81C1/00936 ,  B81B3/0005 ,  B81B2201/0235 ,  B81B2201/025 ,  B81B2203/0136 ,  B81B2203/033 ,  B81B2203/04 ,  B81C2201/0132 ,  B81C2201/053 ,  B81C2201/112 ,  G01P15/0802 ,  G01P15/125 ,  G01P2015/0814 ,  G01P2015/084

Abstract: In a method for manufacturing a semiconductor acceleration sensor, a movable portion including a mass portion and movable electrodes is formed in a single crystal silicon thin film provided on a silicon wafer through an insulation film by etching both the single crystal silicon thin film and the silicon wafer. In this case, the movable portion is finally defined at a movable portion defining step that is carried out in a vapor phase atmosphere. Accordingly, the movable portion is prevented from sticking to other regions due to etchant during the manufacture thereof.

公开(公告)号：US5847454A

公开(公告)日：1998-12-08

申请号：US310336

申请日：1994-09-22

Applicant: Kevin A. Shaw ,  Z. Lisa Zhang ,  Noel C. MacDonald

Inventor： Kevin A. Shaw ,  Z. Lisa Zhang ,  Noel C. MacDonald

IPC: C23F4/00 ,  B81B3/00 ,  G01P15/08 ,  G01P15/125 ,  H01L21/302 ,  H01L21/3065 ,  H01L29/82 ,  H01L29/84 ,  H01L23/48 ,  B44C1/22 ,  H01L23/52

CPC classification number: B81C1/00619 ,  B81C1/00142 ,  B81C1/0015 ,  B81C1/00626 ,  G01P15/0802 ,  G01P15/125 ,  B81C2201/0112 ,  B81C2201/0132 ,  B81C2201/053 ,  G01P2015/0814 ,  G01P2015/0817 ,  G01P2015/0828 ,  Y10S148/05 ,  Y10S73/01

Abstract: A single mask, low temperature reactive ion etching process for fabricating high aspect ratio, released single crystal microelectromechanical structures independently of crystal orientation.

Abstract translation: 用于制造高纵横比的单一掩模，低温反应离子蚀刻工艺，独立于晶体取向释放单晶微机电结构。

公开(公告)号：US5731229A

公开(公告)日：1998-03-24

申请号：US495273

申请日：1995-06-27

Applicant: Makiko Kato ,  Yasukazu Iwasaki ,  Makoto Uchiyama

Inventor： Makiko Kato ,  Yasukazu Iwasaki ,  Makoto Uchiyama

IPC: B81B3/00 ,  B05D7/22

CPC classification number: B81C1/00896 ,  B81C2201/053 ,  B81C2201/056

Abstract: A method of producing a device having a minute structure such as a semiconductor element. The producing method comprises the following steps: (a) forming a film of liquid containing a sublimable material on a surface of a product of the device, the sublimable material being solid ordinary temperature and at normal pressure, the minute structure being formed at the surface of the product; (b) improving a wettability of at least one of the minute structure and a region surrounding the minute structure by the liquid film of the sublimable material; (c) converting the liquid film into a state containing the sublimable material in solid phase so as to form a protective film; and (d) vaporizing the protective film to be removed.

Abstract translation: 一种具有半导体元件等微结构的元件的制造方法。 该制造方法包括以下步骤：（a）在装置的产品的表面上形成含有可升华材料的液体，升华材料为常温常压，微细结构形成在表面 的产品; （b）通过升华材料的液膜改善微小结构和微小结构周围区域中的至少一个的润湿性; （c）将液膜转化成固相含有可升华材料的状态，形成保护膜; 和（d）蒸发要除去的保护膜。

公开(公告)号：US5316979A

公开(公告)日：1994-05-31

申请号：US38879

申请日：1993-03-29

Applicant: Noel C. MacDonald ,  Zuoying L. Zhang

Inventor： Noel C. MacDonald ,  Zuoying L. Zhang

IPC: B81B3/00 ,  B81C1/00 ,  H01H1/00 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/44 ,  H01L21/48 ,  H01L21/90

CPC classification number: B81C1/0015 ,  B81C1/00619 ,  H01H1/0036 ,  H01L21/3065 ,  H01L21/3081 ,  B81C2201/0132 ,  B81C2201/053 ,  Y10S148/05 ,  Y10S148/051

Abstract: A reactive ion etching process is used for the fabrication of submicron, single crystal silicon, movable mechanical structures and capacitive actuators. The reactive ion etching process gives excellent control of lateral dimensions while maintaining a large vertical depth in the formation of high aspect-ratio freely suspended single crystal silicon structures. The silicon etch process is independent of crystal orientation and produces controllable vertical profiles.

Abstract translation: 反应离子蚀刻工艺用于制造亚微米，单晶硅，可移动机械结构和电容式致动器。 在形成高纵横比自由悬浮的单晶硅结构时，反应离子蚀刻工艺提供了横向尺寸的优异控制，同时保持了较大的垂直深度。 硅蚀刻工艺独立于晶体取向并产生可控垂直分布。

公开(公告)号：US4978421A

公开(公告)日：1990-12-18

申请号：US435216

申请日：1989-11-13

Applicant: Ernest Bassous ,  Joseph M. Blum ,  Kevin K. Chan ,  Angela C. Lamberti ,  Constantino Lapadula ,  Istvan Lovas ,  Alan D. Wilson

Inventor： Ernest Bassous ,  Joseph M. Blum ,  Kevin K. Chan ,  Angela C. Lamberti ,  Constantino Lapadula ,  Istvan Lovas ,  Alan D. Wilson

IPC: B81B3/00 ,  G01L9/00 ,  G03F1/22 ,  H01L21/027 ,  H01L29/84

CPC classification number: B81C1/00158 ,  G01L9/0042 ,  G03F1/22 ,  B81C2201/0104 ,  B81C2201/0136 ,  B81C2201/053 ,  B81C2203/019 ,  Y10S438/977

Abstract: The method of fabrication of a monolithic silicon membrane structure in which the membrane and its supporting framework are constructed from a single ultra thick body of silicon. The fabrication sequence includes the steps of providing a doped membrane layer on the silicon body, forming an apertured mask on the silicon body, and removal of an unwanted silicon region by mechanical grinding and chemical etching to provide a well opening in the silicon body terminating in the doped membrane.

公开(公告)号：US12060266B2

公开(公告)日：2024-08-13

申请号：US17248799

申请日：2021-02-08

Applicant: Infineon Technologies AG

Inventor： Andre Brockmeier ,  Markus Bergmeister ,  Bernhard Goller ,  Daniel Pieber ,  Sokratis Sgouridis

IPC: B81C1/00

CPC classification number: B81C1/00896 ,  B81C1/00047 ,  B81C1/00119 ,  B81C2201/053

Abstract: A method for producing MEMS components comprises generating a carrier having a plurality of recesses. An adhesive structure is arranged on the carrier and in the recesses. A semiconductor wafer is generated, which has a plurality of MEMS structures arranged at the first main surface of the semiconductor wafer. The adhesive structure is attached to the first main surface of the semiconductor wafer, with the recesses being arranged above the MEMS structures and the adhesive structure not contacting the MEMS structures. The semiconductor wafer is singulated into a plurality of MEMS components by applying a mechanical dicing process.

公开(公告)号：US10035701B2

公开(公告)日：2018-07-31

申请号：US15305799

申请日：2014-11-05

Applicant: ADVANCED SEMICONDUCTOR MANUFACTURING CO. LTD

Inventor： Yuanjun Xu ,  Yilin Yan ,  Weijia Xue

IPC: B81B7/02 ,  B81C1/00

CPC classification number: B81B7/02 ,  B81B2201/0257 ,  B81B2203/0127 ,  B81B2203/0315 ,  B81C1/00158 ,  B81C1/00396 ,  B81C2201/0132 ,  B81C2201/0133 ,  B81C2201/019 ,  B81C2201/0198 ,  B81C2201/053

Abstract: There is provided a method for forming a composite cavity and a composite cavity formed using the method. The method comprises the following steps: providing a silicon substrate (101); forming an oxide layer on the front side thereof; patterning the oxide layer to form one or more grooves (103), the position of the groove (103) corresponding to the position of small cavity (109) to be formed; providing a bonding wafer (104), which is bonded to the patterned oxide layer to form one or more closed micro-cavity structures (105) between the silicon substrate (101) and the bonding wafer (104); forming a protective film (106) over the bonding wafer (104) and forming a masking layer (107) on the back side of the silicon substrate (101); patterning the masking layer (107), the pattern of the masking layer (107) corresponding to the position of a large cavity (108) to be formed; using the masking layer (107) as a mask, etching the silicon substrate (101) from the back side until the oxide layer at the front side thereof to form the large cavity (108) in the silicon substrate (101); and using the masking layer (107) and the oxide layer as a mask, etching the bonding wafer (104) from the back side through the silicon substrate (101) until the protective film (106) thereover to form one or more small cavities (109) in the bonding wafer (104). The uniformity of thickness of the semiconductor medium layer where the small cavity (109) in the composite cavity is located is well controlled by the present invention.

公开(公告)号：US20180201504A1

公开(公告)日：2018-07-19

申请号：US15923599

申请日：2018-03-16

Applicant: Infineon Technologies AG

Inventor： Alfons Dehe ,  Stephan Pindl ,  Bernhard Knott ,  Carsten Ahrens

IPC: B81C1/00 ,  H04R31/00 ,  H04R19/00 ,  H04R19/04

CPC classification number: B81C1/00825 ,  B81B2201/0235 ,  B81B2201/0257 ,  B81B2201/0264 ,  B81C1/00873 ,  B81C2201/017 ,  B81C2201/053 ,  H04R19/005 ,  H04R19/04 ,  H04R31/00 ,  H04R2201/003

Abstract: A method for manufacturing a MEMS device is disclosed. Moreover a MEMS device and a module including a MEMS device are disclosed. An embodiment includes a method for manufacturing MEMS devices includes forming a MEMS stack over a first main surface of a substrate, forming a polymer layer over a second main surface of the substrate and forming a first opening in the polymer layer and the substrate such that the first opening abuts the MEMS stack.

公开(公告)号：US09998843B2

公开(公告)日：2018-06-12

申请号：US15018625

申请日：2016-02-08

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Jung-Huei Peng ,  Chia-Hua Chu ,  Chun-wen Cheng ,  Chin-Yi Cho ,  Li-Min Hung ,  Yao-Te Huang

IPC: H04R31/00 ,  B81C1/00 ,  H04R19/00 ,  H04R19/04

CPC classification number: H04R31/003 ,  B81C1/00158 ,  B81C2201/0125 ,  B81C2201/013 ,  B81C2201/053 ,  B81C2203/036 ,  H04R19/005 ,  H04R19/04 ,  H04R31/006 ,  H04R2201/003 ,  H04R2307/027

Abstract: The present disclosure provides one embodiment of an integrated microphone structure. The integrated microphone structure includes a first silicon substrate patterned as a first plate. A silicon oxide layer formed on one side of the first silicon substrate. A second silicon substrate bonded to the first substrate through the silicon oxide layer such that the silicon oxide layer is sandwiched between the first and second silicon substrates. A diaphragm secured on the silicon oxide layer and disposed between the first and second silicon substrates such that the first plate and the diaphragm are configured to form a capacitive microphone.

公开(公告)号：US09981843B2

公开(公告)日：2018-05-29

申请号：US15138313

申请日：2016-04-26

Applicant: Infineon Technologies AG

Inventor： Dominic Maier ,  Alfons Dehe ,  Thomas Kilger ,  Markus Menath ,  Franz Xaver Muehlbauer ,  Daniel Porwol ,  Juergen Wagner

IPC: H01L29/84 ,  B81C1/00

CPC classification number: B81C1/00896 ,  B81C1/00269 ,  B81C1/00801 ,  B81C2201/0194 ,  B81C2201/053

Abstract: A method of producing a chip package is described. A plurality of chips is provided on a first wafer. Each chip has a cavity which opens to a first main face of the chip. The cavities are filled or covered temporarily. The chips are then singulated. The singulated chips are embedded in an encapsulation material, and then the cavities are re-exposed.