公开(公告)号：US4404059A

公开(公告)日：1983-09-13

申请号：US382407

申请日：1982-05-26

Applicant: Vladimir I. Livshits ,  Vladimir I. Golovin ,  Vladimir I. Meshkov

Inventor： Vladimir I. Livshits ,  Vladimir I. Golovin ,  Vladimir I. Meshkov

IPC: H05K3/40 ,  H05K3/46 ,  C23F1/02 ,  B44C1/22 ,  C03C15/00 ,  C03C25/06

CPC classification number: H05K3/4092 ,  H05K3/4685 ,  H05K2201/0361 ,  H05K2203/0152 ,  H05K2203/0369 ,  H05K2203/0376 ,  H05K2203/0726 ,  Y10T29/49155

Abstract: The herein disclosed process comprises forming conductors of desired shape on a substrate comprised of a metal that is selectively etchable with respect to the metal of conductors, such that the conductors are formed on both sides of the substrate and that the conductors have at least one constricted portion at the substrate side opposite to that on which a base will be laminated. Then, the panel base is laminated onto the appropriate side of the substrate, and the substrate metal is etched selectively with respect to the conductor metal through the entire thickness of the substrate until the metal of the latter is fully removed from under the constricted portions only.

Abstract translation: 本文公开的方法包括在由相对于导体金属可选择性地蚀刻的金属构成的衬底上形成所需形状的导体，使得导体形成在衬底的两侧上，并且导体具有至少一个收缩的 在与基底层叠相反的基底侧的部分。 然后，将面板基板层叠到基板的适当侧上，并且通过基板的整个厚度相对于导体金属选择性地蚀刻基板金属，直到基板金属仅在缩小部分下完全去除 。

公开(公告)号：US3859177A

公开(公告)日：1975-01-07

申请号：US29035772

申请日：1972-09-19

Applicant: THOMSON CSF

Inventor： GIGOUX CLAUDE

IPC: H05K3/06 ,  H05K3/00 ,  H05K3/20 ,  H05K3/42 ,  H05K3/46 ,  C23B5/48

CPC classification number: H05K3/42 ,  H05K3/0064 ,  H05K3/205 ,  H05K3/46 ,  H05K2201/0361 ,  H05K2203/0376 ,  H05K2203/1184

Abstract: A novel method of manufacturing ''''printed circuits'''' arrangements, with one or several layers of conductors, is provided. By successive operations of photogravure and metal deposition using electrolysis, there is constructed, without any mechanical procedure, a structure comprising a temporary skeleton and conductors arranged at different layers and interconnected by conductive eyelets. The metal constituting the temporary structure is selectively attacked and replaced by resin to constitute a new insulating structure.

公开(公告)号：US20130119012A1

公开(公告)日：2013-05-16

申请号：US13661888

申请日：2012-10-26

Applicant: TESSERA INTERCONNECT MATERIALS, INC.

Inventor： Kimitaka Endo

IPC: H01R43/02

CPC classification number: H01R43/0256 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/13609 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01322 ,  H05K1/185 ,  H05K3/06 ,  H05K3/4007 ,  H05K3/4015 ,  H05K3/4614 ,  H05K2201/0355 ,  H05K2201/0361 ,  H05K2201/10674 ,  H05K2203/0384 ,  H05K2203/0542 ,  H01L2224/05599

Abstract: An interconnection element and method for making same is disclosed. The interconnection element may include a plurality of metal conductors, a plurality of solid metal bumps and a low melting point (LMP) metal layer. The solid metal bumps overly and project in a first direction away from respective ones of the conductors. Each bump has at least one edge bounding the bump in at least a second direction transverse to the first direction. The low melting point (LMP) metal layer has a first face joined to the respective ones of the conductors and bounded in the second direction by at least one edge and a second face joined to the bumps. The edges of the bumps and the LMP layer are aligned in the first direction, and the LMP metal layer has a melting temperature substantially lower than the conductors.

Abstract translation: 公开了互连元件及其制造方法。 互连元件可以包括多个金属导体，多个固体金属凸块和低熔点（LMP）金属层。 固体金属凸起并且远离相应导体的第一方向突出。 每个凸块具有至少一个沿至少一个横向于第一方向的第二方向限定凸块的边缘。 低熔点（LMP）金属层具有通过至少一个边缘和与凸块接合的第二面连接到各个导体并沿第二方向限定的第一面。 凸块和LMP层的边缘在第一方向上对齐，并且LMP金属层的熔化温度基本上低于导体。

公开(公告)号：US08299368B2

公开(公告)日：2012-10-30

申请号：US12317707

申请日：2008-12-23

Applicant: Kimitaka Endo

Inventor： Kimitaka Endo

IPC: H05K1/11

CPC classification number: H01R43/0256 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/13609 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01322 ,  H05K1/185 ,  H05K3/06 ,  H05K3/4007 ,  H05K3/4015 ,  H05K3/4614 ,  H05K2201/0355 ,  H05K2201/0361 ,  H05K2201/10674 ,  H05K2203/0384 ,  H05K2203/0542 ,  H01L2224/05599

Abstract: An interconnection element and method for making same is disclosed. The interconnection element may include a plurality of metal conductors, a plurality of solid metal bumps and a low melting point (LMP) metal layer. The solid metal bumps overly and project in a first direction away from respective ones of the conductors. Each bump has at least one edge bounding the bump in at least a second direction transverse to the first direction. The low melting point (LMP) metal layer has a first face joined to the respective ones of the conductors and bounded in the second direction by at least one edge and a second face joined to the bumps. The edges of the bumps and the LMP layer are aligned in the first direction, and the LMP metal layer has a melting temperature substantially lower than the conductors.

Abstract translation: 公开了互连元件及其制造方法。 互连元件可以包括多个金属导体，多个固体金属凸块和低熔点（LMP）金属层。 固体金属凸起并且远离相应导体的第一方向突出。 每个凸块具有至少一个沿至少一个横向于第一方向的第二方向限定凸块的边缘。 低熔点（LMP）金属层具有连接到各个导体的第一面，并且通过至少一个边缘和与凸块相连的第二面沿第二方向限定。 凸块和LMP层的边缘在第一方向上对齐，并且LMP金属层的熔化温度基本上低于导体。

公开(公告)号：US08152953B2

公开(公告)日：2012-04-10

申请号：US12365279

申请日：2009-02-04

Applicant: Hideaki Yoshimura ,  Takashi Nakagawa ,  Kenji Fukuzono ,  Takashi Kanda ,  Tomohisa Yagi

Inventor： Hideaki Yoshimura ,  Takashi Nakagawa ,  Kenji Fukuzono ,  Takashi Kanda ,  Tomohisa Yagi

IPC: B32B37/12

CPC classification number: H05K3/321 ,  H05K3/20 ,  H05K3/4069 ,  H05K3/4602 ,  H05K3/4614 ,  H05K3/4641 ,  H05K3/4644 ,  H05K2201/0218 ,  H05K2201/0323 ,  H05K2201/0361 ,  H05K2201/10378 ,  H05K2201/10674 ,  H05K2203/0156 ,  H05K2203/061

Abstract: The first support body is pressed against the second support body in response to the softening of the adhesive sheet. The fillers are allowed to reliably contact with one another between the first electrically-conductive land and the second electrically-conductive land. The fillers melt after the adhesive sheet has been softened. The intermetallic compounds are formed between the fillers and the electrically-conductive lands and between the fillers. Electrical connection is in this manner established between the first electrically-conductive land and the second electrically-conductive land. The matrix material and the adhesive sheet are then cured. The first support body and the second support body are firmly bonded to each other.

Abstract translation: 响应于粘合片的软化，第一支撑体被压靠在第二支撑体上。 允许填料在第一导电焊盘和第二导电焊盘之间彼此可靠地接触。 粘合片软化后，填料熔化。 金属间化合物形成在填料和导电性焊盘之间以及填料之间。 电连接以这种方式建立在第一导电焊盘和第二导电焊盘之间。 然后将基质材料和粘合片固化。 第一支撑体和第二支撑体彼此牢固地接合。

公开(公告)号：US08138423B2

公开(公告)日：2012-03-20

申请号：US11719803

申请日：2005-11-18

Applicant: Mitsuhiro Watanabe ,  Kinji Saijo ,  Shinji Ohsawa ,  Kazuo Yoshida ,  Koji Nanbu

Inventor： Mitsuhiro Watanabe ,  Kinji Saijo ,  Shinji Ohsawa ,  Kazuo Yoshida ,  Koji Nanbu

IPC: H05K1/03

CPC classification number: H05K3/427 ,  H05K1/0265 ,  H05K1/116 ,  H05K3/062 ,  H05K3/20 ,  H05K3/4658 ,  H05K2201/0352 ,  H05K2201/0355 ,  H05K2201/0361 ,  H05K2201/0376 ,  H05K2201/09509 ,  H05K2201/09736 ,  H05K2203/0361 ,  H05K2203/0384 ,  H05K2203/1476 ,  Y10T156/10

Abstract: A printed wiring board and a method for manufacturing the printed wiring board in which widths of a first and a second circuit are close to each other and substantial miniaturization can be achieved. In order to achieve this object, a first circuit and a second circuit having different thicknesses are formed in the same reference plane by etching a metal-clad laminate including a conductive layer and an insulating layer. The thicker of the circuits has a clad-like configuration in which three layers, a first copper layer/a different kind of metal layer/a second copper layer, are sequentially stacked. The manufacture of the printed wiring board includes a clad composite material in which three layers of a first copper layer/a different kind of metal layer/a second copper layer are sequentially stacked as a start material, and selective etching characteristics between the layers are utilized.

Abstract translation: 一种印刷电路板和用于制造印刷电路板的方法，其中第一和第二电路的宽度彼此接近并且可以实现实质的小型化。 为了实现该目的，通过蚀刻包括导电层和绝缘层的覆金属层压体，在相同的参考平面中形成具有不同厚度的第一电路和第二电路。 较厚的电路具有包层状构造，其中依次层叠有三层，第一铜层/不同种类的金属层/第二铜层。 印刷电路板的制造包括其中依次层叠有三层第一铜层/不同种类的金属层/第二铜层作为起始材料的覆层复合材料，并且利用层之间的选择性蚀刻特性 。

公开(公告)号：US20100065852A1

公开(公告)日：2010-03-18

申请号：US12559181

申请日：2009-09-14

Applicant: Chieh-Wen LIN ,  Chih-Chieh WANG ,  Sheng-Wen CHANG ,  Te-Chang WAN

Inventor： Chieh-Wen LIN ,  Chih-Chieh WANG ,  Sheng-Wen CHANG ,  Te-Chang WAN

IPC: H01L33/00

CPC classification number: H05K3/06 ,  G02F1/1345 ,  G02F1/13458 ,  H05K2201/0361 ,  H05K2203/1184

Abstract: A system for displaying images and fabricating method thereof are provided. The system includes a thin film transistor substrate including a substrate having a display area and a pad area. The thin film transistor substrate further includes a conductive line disposed on the substrate in the display area. The conductive line includes a lower metal line, an upper metal line and a middle metal line therebetween. The width of the middle metal line is narrower than that of the upper metal line.

Abstract translation: 提供一种用于显示图像的系统及其制造方法。 该系统包括薄膜晶体管基板，其包括具有显示区域和焊盘区域的基板。 薄膜晶体管基板还包括布置在显示区域中的基板上的导线。 导线包括下金属线，上金属线和中间金属线。 中间金属线的宽度比上金属线的宽度窄。

公开(公告)号：US20090314650A1

公开(公告)日：2009-12-24

申请号：US12422432

申请日：2009-04-13

Applicant: Tzyy-Jang Tseng ,  Chung W. Ho

Inventor： Tzyy-Jang Tseng ,  Chung W. Ho

IPC: C25D5/00 ,  B05D5/12

CPC classification number: H05K1/0206 ,  H01L21/486 ,  H01L23/13 ,  H01L23/142 ,  H01L23/145 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L33/486 ,  H01L33/60 ,  H01L2224/48227 ,  H01L2924/15311 ,  H05K3/06 ,  H05K3/20 ,  H05K3/429 ,  H05K3/44 ,  H05K3/445 ,  H05K3/4652 ,  H05K2201/0338 ,  H05K2201/0361 ,  H05K2201/09554 ,  H05K2201/096 ,  H05K2201/10106 ,  H05K2203/0384

Abstract: A process of a package substrate is provided. A plurality of metal layers stacked in sequence is used as a foundation structure. A thick heat conductive core is fabricated from one of the metal layers for providing high heat dissipation capability, and a plurality of pads is fabricated from another one of the metal layers for electrically connecting an electronic package at the next level.

Abstract translation: 提供封装基板的工艺。 将多个依次层叠的金属层用作基础结构。 由金属层之一制造厚的导热芯，以提供高的散热能力，并且由另一个金属层制造多个焊盘，用于将电子封装电连接在下一层。

公开(公告)号：US20090008141A1

公开(公告)日：2009-01-08

申请号：US12230564

申请日：2008-09-02

Applicant: Hidehiro Nakamura ,  Akishi Nakaso ,  Shigeharu Arike ,  Fumio Inoue ,  Tetsuya Enomoto ,  Norio Moriike ,  Kousuke Hiroki

Inventor： Hidehiro Nakamura ,  Akishi Nakaso ,  Shigeharu Arike ,  Fumio Inoue ,  Tetsuya Enomoto ,  Norio Moriike ,  Kousuke Hiroki

IPC: H05K1/11 ,  H05K1/16

CPC classification number: H05K3/4617 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/3128 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01327 ,  H01L2924/15183 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K3/0097 ,  H05K3/06 ,  H05K3/244 ,  H05K3/4038 ,  H05K3/4623 ,  H05K3/4632 ,  H05K3/4647 ,  H05K2201/0141 ,  H05K2201/0195 ,  H05K2201/0355 ,  H05K2201/0361 ,  H05K2201/096 ,  H05K2201/10378 ,  H05K2203/0152 ,  H05K2203/0156 ,  H05K2203/0384 ,  H05K2203/0733 ,  H05K2203/1536 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49147 ,  Y10T29/49165 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: The present invention provides a connection board that is formed by an insulating resin composition layer made of one layer or two or more layers and a connection conductor that is formed so as to pass through the insulating resin composition layer in its thickness direction at a position where a conductor circuit is connected, and a multi-layer wiring board, a substrate for semiconductor package and a semiconductor package using the connection board, and methods for manufacturing them.

Abstract translation: 本发明提供一种由一层或两层以上的绝缘树脂组合物层形成的连接板，以及形成为在其绝缘树脂组合物层的厚度方向上形成的连接导体， 连接导体电路，并且使用多层布线板，半导体封装用基板和使用该连接基板的半导体封装，以及其制造方法。

公开(公告)号：US20080128886A1

公开(公告)日：2008-06-05

申请号：US11606771

申请日：2006-11-30

Applicant: Teck-Gyu Kang ,  Jae M. Park ,  Yoichi Kubota

Inventor： Teck-Gyu Kang ,  Jae M. Park ,  Yoichi Kubota

IPC: H01L23/48 ,  H01L21/00

CPC classification number: H01L23/4985 ,  B81B7/007 ,  B81B2207/097 ,  H01L23/057 ,  H01L23/49861 ,  H01L24/48 ,  H01L27/14678 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/16195 ,  H01L2924/3025 ,  H05K1/118 ,  H05K1/189 ,  H05K2201/0361 ,  H05K2201/0367 ,  H05K2201/2009 ,  H05K2203/0169 ,  H05K2203/1327 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: Substrates having integrated rigid and flexible regions and methods of fabricating such substrates are disclosed. The substrates may advantageously be used for mounting semiconductor chips used in flexible microelectronic assemblies.

Abstract translation: 公开了具有集成的刚性和柔性区域的基板以及制造这种基板的方法。 衬底可以有利地用于安装用于柔性微电子组件中的半导体芯片。