公开(公告)号：US20120162928A1

公开(公告)日：2012-06-28

申请号：US12910020

申请日：2010-10-22

Applicant: Rabindra N. Das ,  Frank D. Egitto ,  Voya R. Markovich

Inventor： Rabindra N. Das ,  Frank D. Egitto ,  Voya R. Markovich

IPC: H05K7/00 ,  H05K3/40 ,  H05K3/46

CPC classification number: H01L23/49833 ,  H01L23/488 ,  H01L23/49827 ,  H01L23/5389 ,  H01L2224/16225 ,  H05K1/111 ,  H05K1/144 ,  H05K3/06 ,  H05K3/368 ,  H05K3/4007 ,  H05K7/00 ,  H05K2201/0373 ,  H05K2201/042 ,  H05K2201/09745 ,  H05K2201/10378 ,  H05K2203/047 ,  H05K2203/1572 ,  H05K2203/176 ,  Y10T29/49155

Abstract: An electronic package with two circuitized substrates which sandwich an interposer therebetween, the interposer electrically interconnecting the substrates and also including an opening therein in which is positioned at least one electrical component, such as a semiconductor chip, coupled to the lower or base substrate. A second component may also be mounted on and electrically coupled to the upper surface of the top or cover circuitized substrate. A method of making such a package is also provided.

Abstract translation: 具有夹在其间的插入件的两个电路化基板的电子封装件，所述插入器将所述基板电连接并且还包括其中的开口，所述开口位于耦合到所述下基板或基底基板的至少一个电部件（例如半导体芯片）。 第二部件也可以安装在顶部或盖子电路化基板的上表面上并电耦合到顶部或盖子电路化基板的上表面。 还提供了制造这种包装的方法。

公开(公告)号：US08174017B2

公开(公告)日：2012-05-08

申请号：US11505201

申请日：2006-08-16

Applicant: Markondeya Raj Pulugurtha ,  Devarajan Balaraman ,  Isaac R. Abothu ,  Rao Tummala ,  Farrokh Ayazi

Inventor： Markondeya Raj Pulugurtha ,  Devarajan Balaraman ,  Isaac R. Abothu ,  Rao Tummala ,  Farrokh Ayazi

IPC: H01L27/108

CPC classification number: H01L27/1203 ,  H01G4/1227 ,  H01G4/33 ,  H01L21/84 ,  H01L28/55 ,  H01L28/91 ,  H05K1/162 ,  H05K3/243 ,  H05K2201/0175 ,  H05K2201/0355 ,  H05K2201/0373 ,  H05K2203/0315

Abstract: Disclosed are three-dimensional dielectric structures on high surface area electrodes and fabrication methods. Exemplary structures comprise a copper foil substrate, trench electrodes or high surface area porous electrode structures formed on the substrate, a insulating thin film formed on the surface and laminating the foil on a organic substrate. A variety of materials may be used to make the films including perovksite ceramics such as barium titanate, strontium titanate, barium strontium titanate (BST), lead zirconate titanate (PZT); other intermediate dielectric constant films such as zinc oxide, aluminum nitride, silicon nitride; typical paraelectrics such as tantalum oxide, alumina, and titania. The films may be fabricated using sol-gel, hydrothermal synthesis, anodization or vapor deposition techniques.

Abstract translation: 公开了高表面电极上的三维电介质结构和制造方法。 示例性结构包括铜箔衬底，形成在衬底上的沟槽电极或高表面积多孔电极结构，在表面上形成的绝缘薄膜，并将箔层压在有机衬底上。 可以使用各种材料来制造包括钛酸钡，钛酸锶，钛酸锶钡（BST），锆钛酸铅（PZT）等周波陶瓷的膜。 其它中间介电常数膜如氧化锌，氮化铝，氮化硅; 典型的顺电介质如氧化钽，氧化铝和二氧化钛。 可以使用溶胶 - 凝胶，水热合成，阳极氧化或气相沉积技术来制造膜。

公开(公告)号：US20120074210A1

公开(公告)日：2012-03-29

申请号：US13270655

申请日：2011-10-11

Applicant: Franc DUGAL

Inventor： Franc DUGAL

IPC: B23K1/20 ,  B23K35/14

CPC classification number: B23K35/0244 ,  B23K35/38 ,  H05K3/341 ,  H05K3/3478 ,  H05K2201/0373 ,  H05K2201/09163 ,  H05K2203/0415

Abstract: A soldering preform for soldering in a reducing atmosphere is substantially disc-shaped and has two soldering surfaces each for being in contact with an object to be soldered, respectively, and with at least one recess on at least one soldering surfaces for constituting a channel open to a surface of the object.

Abstract translation: 用于在还原气氛中焊接的焊接预成型件基本上是圆盘形的，并且具有分别与待焊接物体接触的两个焊接表面，并且在至少一个焊接表面上具有用于构成通道开口的至少一个凹部 到物体的表面。

公开(公告)号：US20120073868A1

公开(公告)日：2012-03-29

申请号：US13314641

申请日：2011-12-08

Applicant: Yoshinori TAKENAKA ,  Takeshi NAKAMURA

Inventor： Yoshinori TAKENAKA ,  Takeshi NAKAMURA

IPC: H05K1/09 ,  H05K1/02

CPC classification number: H05K3/465 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L2221/68345 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/3011 ,  H05K2201/0373 ,  H05K2201/0949 ,  H05K2201/09736 ,  H05K2201/10674 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A method for manufacturing a multilayer printed wiring board includes preparing a first resin insulative material having a first conductive circuit on or in the first resin insulative material, forming a second resin insulative material on the first resin insulative material and the first conductive circuit, forming on a surface of the second resin insulative material a first concave portion to be filled with a conductive material for formation of a second conductive circuit, forming on the surface of the second resin insulative material a pattern having a second concave portion and post portions to be filled with the conductive material for formation of a plane conductor, and filling the conductive material in the first concave portion and the second concave portion such that the second conductive circuit and the plane conductor are formed.

Abstract translation: 一种多层印刷电路板的制造方法，其特征在于，在第一树脂绝缘材料上或第一树脂绝缘材料上制备具有第一导电电路的第一树脂绝缘材料，在第一树脂绝缘材料和第一导电电路上形成第二树脂绝缘材料，形成第 所述第二树脂绝缘材料的表面具有要填充用于形成第二导电电路的导电材料的第一凹部，在所述第二树脂绝缘材料的表面上形成具有第二凹部的图案和待填充的柱部分 用于形成平面导体的导电材料，并且在第一凹部和第二凹部中填充导电材料，使得形成第二导电电路和平面导体。

公开(公告)号：US20120067619A1

公开(公告)日：2012-03-22

申请号：US13375670

申请日：2010-05-18

Applicant: Masamichi Yamamoto ,  Kyouichirou Nakatsugi ,  Takashi Yamaguchi ,  Shigeki Kawakami ,  Michihiro Kimura

Inventor： Masamichi Yamamoto ,  Kyouichirou Nakatsugi ,  Takashi Yamaguchi ,  Shigeki Kawakami ,  Michihiro Kimura

IPC: H01B5/00 ,  B23K1/20 ,  B32B37/14 ,  B32B37/12 ,  B23K31/02

CPC classification number: H05K3/361 ,  C23F11/149 ,  H01L2924/0002 ,  H05K3/282 ,  H05K3/305 ,  H05K3/323 ,  H05K3/3431 ,  H05K3/4007 ,  H05K2201/0248 ,  H05K2201/0373 ,  H05K2201/094 ,  H05K2201/10977 ,  H05K2201/10992 ,  H05K2203/308 ,  Y10T156/10 ,  H01L2924/00

Abstract: [Object] Provided are a connection method and an electronic device, in which the manufacturing process can be simplified, and a connection structure using an adhesive can be produced at low cost.[Solution] A connection method according to the present invention includes a step (a1) of preparing base materials 10 and 21 each including an electrode for connection using an adhesive, a step (b1) of covering electrodes 12 and 22 for connection using an adhesive with organic films 15 configured to prevent oxidation, the electrodes 12 and 22 being located on the base materials, a step (c1) of removing or thinning the organic films, and after the step (c1), a step (d1) of bonding the electrodes for connection using an adhesive to each other with an adhesive 30 mainly containing a thermosetting resin to establish electrical connection.

Abstract translation: 提供了一种连接方法和电子设备，其中可以简化制造过程，并且可以以低成本生产使用粘合剂的连接结构。 [解决方案]根据本发明的连接方法包括制备基材10和21的步骤（a1），每个基材10和21各自包括使用粘合剂连接的电极，用于使用粘合剂连接的覆盖电极12和22的步骤（b1） 配置有防止氧化的有机膜15，电极12和22位于基材上，除去或变薄有机膜的步骤（c1），在步骤（c1）之后，将 用于使用主要包含热固性树脂的粘合剂30使用粘合剂彼此连接以建立电连接的电极。

公开(公告)号：US08134225B2

公开(公告)日：2012-03-13

申请号：US12164152

申请日：2008-06-30

Applicant: John J. Maloney ,  Robert M. Smith ,  Charles H. Wilson

Inventor： John J. Maloney ,  Robert M. Smith ,  Charles H. Wilson

IPC: H01L23/495

CPC classification number: H01L23/49548 ,  H01L23/3107 ,  H01L23/49503 ,  H01L23/49582 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/73265 ,  H01L2924/01028 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15747 ,  H01L2924/181 ,  H05K3/341 ,  H05K2201/0367 ,  H05K2201/0373 ,  H05K2201/10689 ,  H05K2201/10727 ,  H05K2201/10969 ,  H05K2201/2036 ,  Y02P70/613 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A QFN package with improved joint solder thickness for improved second level attachment fatigue life. The copper leadframe of a QFN chip carrier is provided with rounded protrusions in both the chip attach pad region and the surrounding lead regions before second level attachment. The rounded stand-off protrusions are formed from the copper itself of the copper of the leadframe. This may be achieved by punching dimples into one surface of the copper plate of the leadframe before plating to form protrusions on the opposing surface. This method of forming the rounded protrusions simplifies the process of forming stand-offs. The protrusions provide a structure that increases wetting area and allows the use of a larger quantity of solder for increased solder joint thickness and better die paddle solder joint area coverage. As a result of the increased solder joint thickness, second level fatigue life is significantly improved. As a result of the improved die paddle solder joint area coverage, improved thermal performance of the chip carrier is also significantly improved.

Abstract translation: QFN封装，具有改进的焊点厚度，可提高二级附着疲劳寿命。 QFN芯片载体的铜引线框架在第二级附接之前在芯片连接焊盘区域和周围的引线区域中设置有圆形突起。 圆形的突出突起由引线框架的铜的铜本身形成。 这可以通过在电镀之前将凹坑冲压到引线框架的铜板的一个表面中以在相对表面上形成突起来实现。 形成圆形突起的这种方法简化了形成支座的过程。 突起提供了增加润湿面积的结构，并且允许使用更大量的焊料以增加焊接接​​头厚度和更好的焊盘焊接区域覆盖。 由于焊接接头厚度的增加，二级疲劳寿命显着提高。 由于焊盘焊接区域覆盖率的提高，芯片载体的热性能也得到了显着提高。

公开(公告)号：US20120013545A1

公开(公告)日：2012-01-19

申请号：US12838181

申请日：2010-07-16

Applicant: Harald Philipp

Inventor： Harald Philipp

IPC: G06F3/041 ,  H05K3/12 ,  H01B7/00

CPC classification number: H05K1/11 ,  G06F3/041 ,  G06F2203/04103 ,  H05K1/09 ,  H05K2201/0326 ,  H05K2201/0329 ,  H05K2201/0373

Abstract: Disclosed examples of electrode structures and methods of manufacture thereof may provide one or more advantages relating to enhanced conductivity, for example, while providing optically clear conductors.

Abstract translation: 公开的电极结构的实例及其制造方法可以提供与提高导电性相关的一个或多个优点，例如，同时提供光学清晰的导体。

公开(公告)号：US08026603B2

公开(公告)日：2011-09-27

申请号：US11408072

申请日：2006-04-21

Applicant: Yung-Yu Hsu ,  Chih-Yuan Cheng ,  Shyi-Ching Liau ,  Min-Lin Lee ,  Ra-Min Tain ,  Rong-Chang Feng

Inventor： Yung-Yu Hsu ,  Chih-Yuan Cheng ,  Shyi-Ching Liau ,  Min-Lin Lee ,  Ra-Min Tain ,  Rong-Chang Feng

IPC: H01L23/52

CPC classification number: H01L24/12 ,  H01L23/49811 ,  H01L24/11 ,  H01L24/16 ,  H01L24/90 ,  H01L2224/1147 ,  H01L2224/11902 ,  H01L2224/13099 ,  H01L2224/1411 ,  H01L2224/16105 ,  H01L2224/16106 ,  H01L2224/16237 ,  H01L2224/81193 ,  H01L2224/81194 ,  H01L2224/81385 ,  H01L2224/81899 ,  H01L2924/01006 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/351 ,  H05K3/326 ,  H05K2201/0373 ,  H05K2201/209 ,  H01L2924/00

Abstract: An interconnect structure of an integrated circuit and manufacturing method therefore are provided, relating to an interconnect structure of flexible packaging. The interconnect structure includes a first and a second conductive pads. A plurality of tiny and conductive first pillars is respectively formed on the first and second pads. With different densities and thicknesses of the first and second pillars, a contact strength can be generated when the pillars interconnecting with each other, such that the pillars are connected closely. Furthermore, the interconnect structure can also be used to connect with fibers made of conductive materials. Moreover, the higher the density of the pillars, the stronger the contact strength. And, electronic substrates and active or passive electronic elements can be stuck on the other side of each pad. Therefore, the interconnect structure can maintain flexibility and have high reliability without being enhanced by any thermosetting polymer.

Abstract translation: 因此，提供了与柔性包装的互连结构相关的集成电路和制造方法的互连结构。 互连结构包括第一和第二导电焊盘。 多个微小且导电的第一支柱分别形成在第一和第二垫上。 当第一和第二支柱具有不同的密度和厚度时，当支柱互相连接时，可以产生接触强度，使得支柱紧密连接。 此外，互连结构也可以用于与由导电材料制成的纤维连接。 此外，支柱的密度越高，接触强度越强。 并且，电子基板和有源或无源电子元件可以卡在每个垫的另一侧上。 因此，互连结构可以保持柔性并且具有高可靠性，而不会被任何热固性聚合物增强。

公开(公告)号：US07964971B2

公开(公告)日：2011-06-21

申请号：US12346566

申请日：2008-12-30

Applicant: Warren M. Farnworth

Inventor： Warren M. Farnworth

IPC: H01L29/40

CPC classification number: H01L24/12 ,  H01L24/11 ,  H01L2224/05022 ,  H01L2224/05573 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/1147 ,  H01L2224/11472 ,  H01L2224/13011 ,  H01L2224/13012 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H05K3/243 ,  H05K3/326 ,  H05K3/4007 ,  H05K3/4092 ,  H05K2201/0367 ,  H05K2201/0373 ,  H01L2224/13099 ,  H01L2224/05099

Abstract: A flexible column interconnect for a microelectronic substrate includes a plurality of conductive columns extending from a bond pad or other conductive terminal in substantially mutually parallel arrangement, providing redundant current paths between the bond pad and a common cap in the form of a contact pad to which they are all joined. The flexibility of the interconnect may be varied by controlling the column dimensions, height, aspect ratio, number of columns, column material and by applying a supporting layer of dielectric material to a controlled depth about the base of the columns. A large number of interconnects may be formed on a wafer, partial wafer, single die, interposer, circuit board, or other substrate.

Abstract translation: 用于微电子衬底的柔性柱互连件包括从接合焊盘或其它导电端子以基本上相互平行布置的方式延伸的多个导电柱，在接合焊盘和接触焊盘的形式的公共盖之间提供冗余的电流路径， 他们都加入了。 互连的灵活性可以通过控制柱尺寸，高度，纵横比，列数，柱材料以及通过将介电材料的支撑层施加到围绕柱的底部的受控深度来改变。 可以在晶片，部分晶片，单芯片，插入器，电路板或其它基板上形成大量互连。

公开(公告)号：US20110122481A1

公开(公告)日：2011-05-26

申请号：US12949488

申请日：2010-11-18

Applicant: Masafumi Ide ,  Toru Takizawa ,  Kaoru Yoda

Inventor： Masafumi Ide ,  Toru Takizawa ,  Kaoru Yoda

IPC: G02F1/35 ,  H01L33/50

CPC classification number: H05K3/32 ,  G02B6/12007 ,  G02B6/4215 ,  G02B6/4232 ,  G02F2001/3505 ,  H01L24/83 ,  H01L2924/14 ,  H01L2924/351 ,  H01S5/02248 ,  H01S5/02272 ,  H01S5/02276 ,  H05K1/0274 ,  H05K1/0306 ,  H05K1/111 ,  H05K2201/0373 ,  H05K2201/09745 ,  H05K2201/10121 ,  H05K2201/10674 ,  H05K2203/0369 ,  H05K2203/095 ,  Y02P70/611 ,  H01L2924/00

Abstract: An integrated device includes an optical element and an electrical element that are implemented on a substrate. The optical element and the electrical element are bonded by surface-activated bonding technology to a bonding portion that is formed on the substrate and made of metal material.

Abstract translation: 集成器件包括实现在衬底上的光学元件和电子元件。 光学元件和电气元件通过表面激活键合技术结合到形成在基板上并由金属材料制成的接合部分。