公开(公告)号：US20120048703A1

公开(公告)日：2012-03-01

申请号：US12923098

申请日：2010-09-01

Applicant: Michael Kotson ,  Eric Sidle ,  Gregory Harold Thamm

Inventor： Michael Kotson ,  Eric Sidle ,  Gregory Harold Thamm

IPC: H01H13/76 ,  H05K1/11

CPC classification number: H05K1/115 ,  G06F3/0202 ,  H01H2239/004 ,  H01H2239/018 ,  H05K1/0218 ,  H05K2201/0715 ,  H05K2201/09481 ,  H05K2201/09609 ,  H05K2201/10053

Abstract: A printed circuit board, especially for a computer keypad, and method for avoiding electromagnetic interference include conductive signal traces positioned on a surface of one of a nonconductive layer that is other than the outward facing surface of an outer nonconductive layer, and vertical interconnect accesses extending through the outer nonconductive layer and connecting the signal traces to the outward facing surface of the outer nonconductive layer, wherein each vertical interconnect access includes a conductive portion on the outward facing surface of the outer nonconductive layer, and the conductive portion has an area no greater than 1/10 the area of the asociated signal trace. Keys selectively connect pairs of vertical interconnect accesses.

Abstract translation: 特别是用于计算机键盘的印刷电路板以及用于避免电磁干扰的方法包括定位在非导电层之一的非导电层之外的导电信号迹线，该非导电层不是外部非导电层的面向外的表面，并且垂直互连通路延伸 通过外部非导电层并将信号迹线连接到外部非导电层的面向外的表面，其中每个垂直互连通路包括在外部非导电层的面向外的表面上的导电部分，并且导电部分的面积不大 超过1/10的相关信号迹线的面积。 键选择性地连接垂直互连接口对。

公开(公告)号：US20120048603A1

公开(公告)日：2012-03-01

申请号：US13117159

申请日：2011-05-27

Applicant: FENG-YAN HUANG

Inventor： FENG-YAN HUANG

IPC: H05K1/09 ,  H05K3/10 ,  H05K1/11

CPC classification number: H05K1/0259 ,  H05K1/0218 ,  H05K3/281 ,  H05K3/323 ,  H05K2201/029 ,  H05K2201/0715

Abstract: A printed circuit board comprises a circuit substrate, an electrically conductive cloth structure, and a shielding structure. The circuit substrate comprises a base layer, a grounded circuit layer, and a connecting pad formed on the grounded circuit layer. The cloth structure comprises an anisotropic conductive adhesive connected to the connecting pad, an insulating layer, and a metallic deposition layer arranged between the anisotropic conductive adhesive and the insulating layer. The shielding structure comprises a shielding metal layer, an adhesive matrix, and a number of electrically conductive particles electrically connected to the shielding metal layer. The insulating layer defines a number of through holes corresponding to the particles, the particles is arranged in the through holes respectively and electrically connected the metallic deposition layer and the shielding metal layer. A method for manufacturing the above PCB is also provided.

Abstract translation: 印刷电路板包括电路基板，导电布结构和屏蔽结构。 电路基板包括形成在接地电路层上的基极层，接地电路层和连接焊盘。 布结构包括连接到连接垫的各向异性导电粘合剂，绝缘层和布置在各向异性导电粘合剂和绝缘层之间的金属沉积层。 屏蔽结构包括屏蔽金属层，粘合剂基质和电连接到屏蔽金属层的多个导电颗粒。 绝缘层限定了与颗粒相对应的多个通孔，颗粒分别布置在通孔中并电连接金属沉积层和屏蔽金属层。 还提供了制造上述PCB的方法。

公开(公告)号：US08125289B2

公开(公告)日：2012-02-28

申请号：US12384943

申请日：2009-04-10

Applicant: Mohammad Tabatabai

Inventor： Mohammad Tabatabai

IPC: H01P3/08

CPC classification number: H01P3/026 ,  H05K1/024 ,  H05K1/0245 ,  H05K2201/0191 ,  H05K2201/0715 ,  H05K2201/09236 ,  H05K2201/09318

Abstract: According to one exemplary embodiment, a circuit board for reducing dielectric loss, conductor loss, and insertion loss includes a pair of transmission lines. The pair of transmission lines has sufficient thickness to cause substantial broadside electromagnetic coupling between the pair of transmission lines, where the pair of transmission lines is sufficiently separated from a ground plane of the circuit board so as to cause negligible electromagnetic coupling to the ground plane relative to the substantial broadside electromagnetic coupling. The pair of transmission lines thereby reduce dielectric loss, conductor loss, and insertion loss for signals traversing through the transmission line pair. The pair of transmission lines can be separated from the ground plane by, for example, at least 50.0 mils.

Abstract translation: 根据一个示例性实施例，用于降低介质损耗，导体损耗和插入损耗的电路板包括一对传输线。 这对传输线具有足够的厚度，以在一对传输线之间产生实质的宽边电磁耦合，其中一对传输线与电路板的接地平面充分分离，从而使接地平面的电磁耦合可以忽略不计 到实质的宽边电磁耦合。 这对传输线因此减少了穿过传输线对的信号的介质损耗，导体损耗和插入损耗。 这对传输线可以通过例如至少50.0密耳从地平面分离。

公开(公告)号：US20120023744A1

公开(公告)日：2012-02-02

申请号：US13192474

申请日：2011-07-28

Applicant: HUI ZENG

Inventor： HUI ZENG

IPC: H05K3/36

CPC classification number: H05K3/4635 ,  H05K3/0097 ,  H05K2201/055 ,  H05K2201/0715 ,  Y10T29/49126

Abstract: In a method for manufacturing multilayer PCBs having n circuit layers, a double-sided flexible substrate strip is provided. The strip comprises a number of PCB units, each comprising m segments, wherein m=n/2 if n represents an even integer, and m=(n+1)/2 if n represents an odd integer. Each segment includes two foil portions. In a reel to reel process, the strip is treated to form n−2 foil portions of each PCB unit into traces, further remove one foil portion if n represents an odd integer. The other two foil portions are left untreated. Then the strip is cut to separate the PCB units from each other. The PCB unit is folded in such a manner that the traces are arranged between the other two foil portions. The folded PCB unit is laminated to form a multilayer substrate and traces are formed in the two foil portions.

Abstract translation: 在具有n个电路层的多层PCB的制造方法中，提供双面柔性衬底条。 条带包括多个PCB单元，每个PCB单元包括m个段，其中如果n表示偶数整数，则m = n / 2，如果n表示奇整数，则m =（n + 1）/ 2。 每个片段包括两个箔片部分。 在卷轴到卷轴处理中，处理条带以将每个PCB单元的n-2个箔部分形成迹线，如果n表示奇整数则进一步去除一个箔部分。 另外两个箔片部分未经处理。 然后切割条带以将PCB单元彼此分开。 PCB单元以使得迹线布置在另外两个箔部分之间的方式折叠。 折叠的PCB单元被层压以形成多层基板，并且在两个箔部分中形成迹线。

公开(公告)号：US08084695B2

公开(公告)日：2011-12-27

申请号：US11651338

申请日：2007-01-10

Applicant: Hsiuan-ju Hsu ,  Richard Walter Ziolkowski

Inventor： Hsiuan-ju Hsu ,  Richard Walter Ziolkowski

IPC: H05K1/11 ,  H05K1/14

CPC classification number: H05K1/115 ,  H01L2924/0002 ,  H05K1/0222 ,  H05K1/0251 ,  H05K3/429 ,  H05K3/4652 ,  H05K2201/0715 ,  H05K2201/09809 ,  Y10T29/49155 ,  H01L2924/00

Abstract: The embodiment of the invention is about a novel via structure which can be incorporated into printed circuit boards, integrated circuit packages, and integrated circuits in order to reduce crosstalk, to improve signal integrity and to achieve EM emission compliance. A 4-layer (2 signal layers and 2 power layers or 2 signal layers and 2 ground layers) circuit board assembly was used for demonstrating the effect of the novel via structure. The same concept can be applied to any multi-layer circuit board. Layers that have an electrical property can be added above, under, or within the basic 4-layer circuit board to achieve a multi-layer circuit board. For 2-layer and 3-layer circuit boards, a deformed version of the proposed via structure based upon the same concept will be needed for a coplanar waveguide configuration.

Abstract translation: 本发明的实施例涉及一种新颖的通孔结构，其可并入印刷电路板，集成电路封装和集成电路中，以便减少串扰，提高信号完整性并实现EM发射顺应性。 使用4层（2个信号层和2个功率层或2个信号层和2个接地层）电路板组件来证明新型通孔结构的效果。 相同的概念可以应用于任何多层电路板。 具有电性能的层可以添加到基本4层电路板的上方，下面或内部，以实现多层电路板。 对于2层和3层电路板，对于共面波导配置，将需要基于相同概念的所提出的通孔结构的变形形式。

公开(公告)号：US08014162B2

公开(公告)日：2011-09-06

申请号：US11905913

申请日：2007-10-05

Applicant: Hideki Kusamitsu

Inventor： Hideki Kusamitsu

IPC: H05K7/02 ,  H05K7/06 ,  H05K7/08 ,  H05K7/10

CPC classification number: H05K3/281 ,  H05K1/0218 ,  H05K1/024 ,  H05K1/0393 ,  H05K2201/0116 ,  H05K2201/029 ,  H05K2201/0715

Abstract: A flexible printed circuit board wherein the insulative substrate 34 having a plurality of conductive layers 36b covered with a protective layer 38 is encircled by a mesh-cloth member 32.

Abstract translation: 柔性印刷电路板，其中具有覆盖有保护层38的多个导电层36b的绝缘基板34被网状布构件32包围。

公开(公告)号：US08013254B2

公开(公告)日：2011-09-06

申请号：US12866981

申请日：2008-11-21

Applicant: Yong Goo Lee ,  Kyoung il Kang

Inventor： Yong Goo Lee ,  Kyoung il Kang

IPC: H05K1/00

CPC classification number: H05K1/0253 ,  H05K1/0224 ,  H05K2201/0715 ,  H05K2201/09681 ,  H05K2201/0969 ,  H05K2201/09781

Abstract: The present disclosure provides a printed circuit board (PCB) comprising a first ground layer extended in one direction a first dielectric layer laminated on the first ground layer and extended in the same direction as that of the first ground layer; a signal transmission line laminated on the first dielectric layer and extended in the same direction as that of the first dielectric layer; and a plurality of first ground patterns formed by etching a surface of the first ground layer in an axial direction thereof at a predetermined interval in a line, wherein the plurality of first ground patterns expose the first dielectric layer.

Abstract translation: 本公开提供一种印刷电路板（PCB），其包括在一个方向上延伸的第一电介质层，所述第一接地层层叠在所述第一接地层上并沿与所述第一接地层相同的方向延伸的第一电介质层; 层叠在所述第一电介质层上并沿与所述第一电介质层相同的方向延伸的信号传输线; 以及多个第一接地图案​​，其通过以一定的间隔在一条线上沿其轴向蚀刻第一接地层的表面而形成，其中多个第一接地图案​​暴露第一介电层。

公开(公告)号：US20110128100A1

公开(公告)日：2011-06-02

申请号：US12674221

申请日：2008-07-24

Applicant: Risato Ohhira

Inventor： Risato Ohhira

IPC: H01P3/08

CPC classification number: H05K1/0219 ,  H01L23/66 ,  H01L2223/6616 ,  H01L2223/6627 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/01019 ,  H01L2924/09701 ,  H01L2924/15192 ,  H01L2924/15313 ,  H01L2924/15323 ,  H01L2924/16195 ,  H01L2924/19033 ,  H01L2924/3011 ,  H01P1/047 ,  H01P3/08 ,  H05K1/0253 ,  H05K1/0298 ,  H05K2201/0715 ,  H05K2201/093 ,  H05K2201/09363 ,  H05K2201/09618 ,  H05K2201/09663 ,  H01L2924/00014 ,  H01L2924/00

Abstract: The high-frequency wiring board of the present invention includes: first coplanar lines provided with a first signal line and a first planar ground pattern formed on the same wiring layer as the first signal line; second coplanar lines provided with a second signal line formed on a different wiring layer than the first signal line and a second planar ground pattern formed on the same wiring layer as the second signal line; and a first ground pattern formed on the same wiring layer as the first coplanar lines. The first coplanar lines and the second coplanar lines are connected. At least the first ground pattern and the first planar ground pattern are separated in a region following the second signal line from the connection of the first signal line and the second signal line.

Abstract translation: 本发明的高频布线基板包括：第一共面线，设置有与第一信号线在同一布线层上形成的第一信号线和第一平面接地图案; 第二共面线设置有形成在与第一信号线不同的布线层上的第二信号线和形成在与第二信号线相同的布线层上的第二平面接地图案; 以及形成在与第一共面线相同的布线层上的第一接地图案​​。 第一共面线和第二共面线被连接。 至少第一接地图案​​和第一平面接地图案在第二信号线之后的区域中与第一信号线和第二信号线的连接分开。

公开(公告)号：US20110110052A1

公开(公告)日：2011-05-12

申请号：US12995514

申请日：2009-05-22

Applicant: Tadahiro Ohmi ,  Shigetoshi Sugawa ,  Hiroshi Imai ,  Akinobu Teramoto

Inventor： Tadahiro Ohmi ,  Shigetoshi Sugawa ,  Hiroshi Imai ,  Akinobu Teramoto

IPC: H05K1/18 ,  H05K1/00

CPC classification number: H05K1/0218 ,  H01L23/66 ,  H01L2223/6616 ,  H01L2223/6627 ,  H01L2223/6688 ,  H01L2924/0002 ,  H01L2924/19032 ,  H01L2924/3011 ,  H05K1/025 ,  H05K1/0265 ,  H05K3/4652 ,  H05K2201/0191 ,  H05K2201/0352 ,  H05K2201/0715 ,  H05K2201/096 ,  H05K2201/09618 ,  H05K2201/09727 ,  H05K2201/09972 ,  H01L2924/00

Abstract: A multilayer wiring board 100 comprises a first wiring region 101 where wirings 103a and insulating layers 104a and 104b are alternately laminated, and a second wiring region 102 where a thickness H2 of an insulating layer 104 is twice or more a thickness H1 of the insulating layer in the first wiring region 101 and a width W2 of a wiring 103b is twice or more a width W1 of the wiring in the first wiring region 101. The first wiring region 101 and the second wiring region 102 are integrally formed on the same board.

Abstract translation: 多层布线基板100包括：布线103a和绝缘层104a，104b交替层叠的第一布线区域101和绝缘层104的厚度H2为绝缘层的厚度H1的两倍以上的第二布线区域102 在第一布线区域101中，布线103b的宽度W2是第一布线区域101中的布线的宽度W1的两倍或更多倍。第一布线区域101和第二布线区域102一体地形成在同一个板上。

公开(公告)号：US07921403B2

公开(公告)日：2011-04-05

申请号：US12101455

申请日：2008-04-11

Applicant: John Richard Dangler ,  Matthew Stephen Doyle

Inventor： John Richard Dangler ,  Matthew Stephen Doyle

IPC: G06F17/50 ,  H03K17/693 ,  H05K1/00 ,  H05K1/09

CPC classification number: H05K1/024 ,  G06F17/5018 ,  H01P11/003 ,  H05K1/0298 ,  H05K3/0005 ,  H05K2201/0191 ,  H05K2201/0715 ,  H05K2201/09881 ,  H05K2203/063

Abstract: Impedance control, and the uniformity of electrical and mechanical characteristics in electronic packaging are becoming more important as chip and bus speeds increase and manufacturing processes evolve. Current state of the art design and manufacture processes inherently introduce physical dielectric thickness variations into PCB cross sections. These thickness variations between the ground reference plane(s) and the signal layer(s) inject undesirable characteristic impedance variations and undesirable mechanical variations in thickness and surface topology. Therefore a process of generating equalization data and a design structure for multilayer electronic structures is presented.

Abstract translation: 阻抗控制以及电子封装中电气和机械特性的均匀性越来越重要，因为芯片和总线速度的增加和制造过程的演变。 当前的现有技术设计和制造工艺本身将物理电介质厚度变化引入PCB横截面。 接地参考平面与信号层之间的这些厚度变化引起了不需要的特性阻抗变化和厚度和表面拓扑结构中不期望的机械变化。 因此，提出了产生均衡数据的过程和用于多层电子结构的设计结构。