公开(公告)号：US20100201462A1

公开(公告)日：2010-08-12

申请号：US12762168

申请日：2010-04-16

Applicant: James Leroy Blair ,  Oswin M. Schreiber ,  Jeffrey Thomas Smith

Inventor： James Leroy Blair ,  Oswin M. Schreiber ,  Jeffrey Thomas Smith

IPC: H01P3/08

CPC classification number: H05K1/0219 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/15311 ,  H01P3/006 ,  H01P3/08 ,  H05K1/0237 ,  H05K1/0393 ,  H05K1/147 ,  H05K3/222 ,  H05K2201/09236 ,  H05K2201/09318 ,  H05K2201/09618 ,  H05K2201/09727 ,  H05K2201/10492 ,  H05K2201/10734 ,  H01L2924/00

Abstract: A high speed flexible interconnect cable for an electronic assembly includes a number of conductive layers and a number of dielectric layers. Conductive signal traces, located on the conductive layers, combine with the dielectric layers to form one or more high speed electrical transmission line structures. The cable can be coupled to electronic components using a variety of connection techniques. The cable can also be terminated with any number of known or standardized connector packages.

Abstract translation: 用于电子组件的高速柔性互连电缆包括多个导电层和多个电介质层。 位于导电层上的导电信号迹线与电介质层结合形成一个或多个高速电传输线结构。 电缆可以使用各种连接技术耦合到电子元件。 电缆也可以用任何数量的已知或标准的连接器封装端接。

公开(公告)号：US20100201459A1

公开(公告)日：2010-08-12

申请号：US12671304

申请日：2008-08-01

Applicant: Toshiyuki Kawaguchi ,  Kazutoki Tahara ,  Tsutomu Saga

Inventor： Toshiyuki Kawaguchi ,  Kazutoki Tahara ,  Tsutomu Saga

IPC: H01P1/20

CPC classification number: H01P3/08 ,  H05K1/0234 ,  H05K1/167 ,  H05K2201/09236 ,  H05K2201/09318 ,  H05K2201/09336 ,  H05K2201/09672

Abstract: The invention provides a transmission noise suppressing structure and a wiring board capable of suppressing a transmission noise transferred through a power supply line, stabilizing a power supply voltage, and reducing signal transmission line cross talk transmitted through the power supply line or a ground layer without being affected by a resistive layer. A transmission noise suppressing structure includes a power supply line and a signal transmission line arranged apart from each other on the same surface; a ground layer arranged apart from the power supply line and the signal transmission line; and a resistive layer arranged apart from the power supply line and the ground layer. The resistive layer has an area (I) which faces the power supply line and an area (II) which does not face the power supply line. The resistive layer and the signal transmission line are apart from each other.

Abstract translation: 本发明提供一种传输噪声抑制结构和布线板，其能够抑制通过电源线传输的传输噪声，稳定电源电压，以及减少通过电源线或接地层传输的信号传输线串扰，而不会 受电阻层影响。 传输噪声抑制结构包括在同一表面上彼此分开布置的电源线和信号传输线; 与电源线和信号传输线分开设置的接地层; 以及与电源线和接地层分开布置的电阻层。 电阻层具有面向电源线的区域（I）和不面向电源线的区域（II）。 电阻层和信号传输线彼此分开。

公开(公告)号：US07746657B2

公开(公告)日：2010-06-29

申请号：US12075375

申请日：2008-03-11

Applicant: Dorin Oprea ,  Steven Driediger

Inventor： Dorin Oprea ,  Steven Driediger

IPC: H05K7/00

CPC classification number: H05K1/0218 ,  H05K2201/09236 ,  H05K2201/093 ,  H05K2201/09618 ,  H05K2201/0969 ,  H05K2201/10121

Abstract: The present invention is a specially designed PCB that allows XFP compliant transceiver modules and EMI gaskets to be used in a manner specified in the XFP standard and results in an integrated solution that is compliant with the XFP standard. Various geometric features are incorporated into the PCB to achieve improvements that in combination result in an integrated solution meeting the XFP standard. Some of these improved features include: specific thickness of prepreg and other layering of the PCB, specific spacing, dimensions and weights for certain components of the PCB, an opening on the first layer XFP cage ground shield connecting to the EMI gasket, guard ground traces in the second layer surrounding the differential pair signal traces, openings in the copper of the third layer beneath the XFP cage ground shield and XFP connector pads, and ground vias at the XFP connector and PHY connector pads.

Abstract translation: 本发明是专门设计的PCB，其允许以XFP标准中规定的方式使用符合XFP标准的收发器模块和EMI垫片，并产生符合XFP标准的集成解决方案。 各种几何特征被并入到PCB中以实现改进，其结合形成满足XFP标准的集成解决方案。 其中一些改进的特征包括：预浸料坯的特定厚度和PCB的其他分层，PCB的某些部件的特定间距，尺寸和重量，第一层上的开口XFP笼式接地屏蔽层连接到EMI垫片，保护接地迹线 在围绕差分对信号迹线的第二层中，XFP笼式接地屏蔽和XFP连接器焊盘下方第三层铜的开口，以及XFP连接器和PHY连接器焊盘处的接地通孔。

公开(公告)号：US07732913B2

公开(公告)日：2010-06-08

申请号：US11701767

申请日：2007-02-02

Applicant: Tsung-Tien Hsieh ,  Wen-Jung Chiang ,  Yu-Po Wang ,  Cheng-Hsu Hsiao ,  Sen-Yen Yang

Inventor： Tsung-Tien Hsieh ,  Wen-Jung Chiang ,  Yu-Po Wang ,  Cheng-Hsu Hsiao ,  Sen-Yen Yang

IPC: H01L23/04

CPC classification number: H01L23/49827 ,  H01L23/64 ,  H01L2223/6638 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K1/0245 ,  H05K1/0251 ,  H05K1/114 ,  H05K3/429 ,  H05K2201/09236 ,  H05K2201/09636 ,  H05K2201/09718 ,  H01L2924/00

Abstract: A semiconductor package substrate is provided, which includes a substrate body having a plurality of conductive through holes formed therein, wherein at least two adjacent conductive through holes are formed as a differential pair, each of which has a ball pad formed at an end thereof; and at least one electrically integrated layer formed in the substrate body, and having an opening corresponding to the two adjacent conductive through holes formed as the differential pair and the ball pads thereof. Thus, the spacing between the conductive through holes and the electrically integrated layer and the spacing between the ball pads can be enlarged by the opening, so as to balance the impedance match.

Abstract translation: 提供了一种半导体封装基板，其包括其中形成有多个导电通孔的基板主体，其中至少两个相邻的导电通孔形成为差分对，每个导体通孔在其一端形成有球垫; 以及形成在所述基板主体中的至少一个电气集成层，并且具有与形成为所述差动对的两个相邻的导电通孔对应的开口及其球垫。 因此，可以通过开口来扩大导电通孔和电气集成层之间的间隔以及球垫之间的间隔，从而平衡阻抗匹配。

公开(公告)号：US20100136835A1

公开(公告)日：2010-06-03

申请号：US12698390

申请日：2010-02-02

Applicant: Amid Hashim ,  Julian Robert Pharney

Inventor： Amid Hashim ,  Julian Robert Pharney

IPC: H01R13/66

CPC classification number: H01R13/6466 ,  H01R13/7195 ,  H01R24/64 ,  H05K1/0228 ,  H05K1/0237 ,  H05K1/0298 ,  H05K1/162 ,  H05K1/165 ,  H05K2201/09236 ,  H05K2201/10189 ,  Y10S439/941

Abstract: A connector is provided for simultaneously improving both the NEXT high frequency performance when low crosstalk plugs are used and the NEXT low frequency performance when high crosstalk plugs are used. The connector includes a first compensation structure provided on an inner metalized layer of the PCB at a first stage area of the PCB, and a second compensation structure, provided at a second stage area of the PCB, for increasing compensation capacitance with increasing frequency.

Abstract translation: 提供连接器，用于当使用低串扰插头时同时提高NEXT高频性能，并且当使用高串扰插头时NEXT低频性能。 连接器包括在PCB的第一级区域设置在PCB的内部金属化层上的第一补偿结构和设置在PCB的第二级区域的第二补偿结构，用于以增加的频率增加补偿电容。

公开(公告)号：US07726018B2

公开(公告)日：2010-06-01

申请号：US11670668

申请日：2007-02-02

Applicant: Jack E. Caveney ,  Scott M. Lesniak

Inventor： Jack E. Caveney ,  Scott M. Lesniak

IPC: H01R43/20

CPC classification number: H01R4/2416 ,  H01R4/2433 ,  H01R13/6466 ,  H01R13/6469 ,  H01R13/665 ,  H01R13/6658 ,  H01R24/64 ,  H05K1/0228 ,  H05K1/162 ,  H05K1/165 ,  H05K2201/09236 ,  H05K2201/09672 ,  H05K2201/10189 ,  Y10S439/941 ,  Y10S439/942 ,  Y10T29/49201 ,  Y10T29/49202 ,  Y10T29/49204 ,  Y10T29/49208

Abstract: A method for reducing crosstalk between a plurality of wires in a network cable using a network cable jack that includes a printed circuit board (PCB) for balancing both inductive and capacitive coupling. The method includes using two distinct inductance zones separated by a neutral zone. Significant gains in degrees of freedom are achieved for designing PCB trace patterns in which a pair of inductive coupling zones jointly offset the inductive coupling caused by a specification plug and the jack contacts, both in magnitude and phase angle. Further, using distinct inductance zones offers more freedom regarding the placement of capacitive plates for use in capacitance balancing as well as the placement of terminals and insulation displacement contacts. Although the magnitude of a capacitive coupling is determined by the length of the capacitor plates parallel to current carrying traces, the approach allows capacitive and inductive coupling to be balanced independently.

Abstract translation: 一种用于使用包括用于平衡感应和电容耦合的印刷电路板（PCB）的网络电缆插孔来减少网络电缆中的多根电线之间的串扰的方法。 该方法包括使用由中性区隔开的两个不同的电感区。 实现自由度的显着提高，用于设计PCB迹线图案，其中一对电感耦合区域在幅度和相位角度上共同抵消由指定插头和插座触点引起的电感耦合。 此外，使用不同的电感区域可以提供更多的自由度，用于电容平板的放置以及端子和绝缘位移触点的放置。 虽然电容耦合的大小由与载流轨迹平行的电容器板的长度确定，但该方法允许电容和电感耦合独立平衡。

公开(公告)号：US07723618B2

公开(公告)日：2010-05-25

申请号：US12193298

申请日：2008-08-18

Applicant: Tao Liang ,  Stephen H. Hall ,  Howard Heck ,  Gary A. Brist ,  Bryce Horine

Inventor： Tao Liang ,  Stephen H. Hall ,  Howard Heck ,  Gary A. Brist ,  Bryce Horine

IPC: H05K1/03

CPC classification number: H05K1/0245 ,  H05K1/0366 ,  H05K2201/029 ,  H05K2201/09236

Abstract: An article of manufacture includes a circuit board and a pair of traces on or in the circuit board. The pair of traces includes a first trace and a second trace. The first trace includes a first segment and a second segment continuously joined to the first segment. The first segment coincides with a first longitudinal axis. The second trace includes a first segment that runs alongside the first segment of the first trace. The second trace also includes a second segment that runs alongside the second segment of the first trace. The second segment of the second trace is continuously joined to the first segment of the second trace. The second segment of the second trace coincides with the first longitudinal axis.

Abstract translation: 制造品包括电路板和电路板上或电路板中的一对迹线。 该对轨迹包括第一轨迹和第二轨迹。 第一迹线包括连续地连接到第一段的第一段和第二段。 第一段与第一纵向轴线重合。 第二个跟踪包括与第一个跟踪的第一个段一起运行的第一个段。 第二轨迹还包括与第一轨迹的第二段一起运行的第二段。 第二迹线的第二段连续地连接到第二迹线的第一段。 第二轨迹的第二段与第一纵向轴线重合。

公开(公告)号：US20100116540A1

公开(公告)日：2010-05-13

申请号：US12611261

申请日：2009-11-03

Applicant: Jun ISHII ,  Toshiki NAITOU ,  Mitsuru HONJO

Inventor： Jun ISHII ,  Toshiki NAITOU ,  Mitsuru HONJO

IPC: H05K1/11 ,  B05D5/12

CPC classification number: H05K3/4685 ,  G11B5/484 ,  G11B5/486 ,  H05K1/0228 ,  H05K1/0245 ,  H05K1/025 ,  H05K1/0265 ,  H05K1/056 ,  H05K3/06 ,  H05K2201/09236 ,  H05K2201/09254 ,  H05K2201/09509 ,  H05K2201/09554 ,  H05K2201/09627 ,  H05K2201/0979 ,  H05K2203/0323 ,  Y10T29/49155

Abstract: An end of a first line and an end of a second line of a first write wiring pattern are arranged on both sides of a third line of a second write wiring pattern. Circular connection portions are provided at the ends of the first line and the second line. In addition, through holes are formed in respective portions of a base insulating layer below the connection portions. Each connection portion comes in contact with a connecting region of a suspension body within the through hole.

Abstract translation: 第一写入布线图案的第一行的一端和第二行的末端布置在第二写入布线图案的第三行的两侧。 圆形连接部设置在第一线和第二线的端部。 此外，在连接部分下方的基底绝缘层的各个部分中形成通孔。 每个连接部分与通孔内的悬架体的连接区域接触。

公开(公告)号：US07677931B2

公开(公告)日：2010-03-16

申请号：US12413865

申请日：2009-03-30

Applicant: Robert A. Aekins

Inventor： Robert A. Aekins

IPC: H01R24/00

CPC classification number: H01R13/6466 ,  H01R13/6625 ,  H01R13/7195 ,  H05K1/0228 ,  H05K1/162 ,  H05K2201/09236 ,  H05K2201/10189

Abstract: Methods are provided for reducing port to port crosstalk on a multiport assembly. Steps of the method include placing at least one BEMI in at least one compensation region, disposed on a PCB. The BEMI reduces port to port crosstalk noise by generating an opposite polarity signal to an unwanted noise signal generated through port to port adjacency. The PCB includes a plurality of ports, at least including adjacent first and second ports, each of which is an RJ45 jack port. Each port of the plurality of ports includes a plurality of modular insert pins, and is associated with an IDC pin group. The at least one compensation region includes one or more regions for generating noise compensation with respect to crosstalk noise resulting from coupling between respective modular insert pins of, or IDC pins associated with, the first and second ports, respectfully.

Abstract translation: 提供了用于减少多端口组件上的端口到端口串扰的方法。 该方法的步骤包括将至少一个BEMI放置在布置在PCB上的至少一个补偿区域中。 BEMI通过产生与通过端口到端口邻接产生的不需要的噪声信号相反的极性信号来减少端口到端口的串扰噪声。 PCB包括多个端口，至少包括相邻的第一和第二端口，每个端口是RJ45插座端口。 多个端口的每个端口包括多个模块化插入引脚，并且与IDC引脚组相关联。 所述至少一个补偿区域包括一个或多个区域，用于相对于由与第一和第二端口相关联的IDC引脚的相应模块化插入引脚之间的耦合产生的串扰噪声产生噪声补偿。

公开(公告)号：US07671450B2

公开(公告)日：2010-03-02

申请号：US12060387

申请日：2008-04-01

Applicant: Ellis E. Nease ,  Ashley Rebelo ,  Christopher J. Wittensoldner

Inventor： Ellis E. Nease ,  Ashley Rebelo ,  Christopher J. Wittensoldner

IPC: H01L23/50

CPC classification number: H05K1/0251 ,  H01L23/49827 ,  H01L23/66 ,  H01L2223/6616 ,  H01L2223/6638 ,  H01L2924/0002 ,  H01L2924/19051 ,  H01L2924/3011 ,  H05K1/0245 ,  H05K1/115 ,  H05K2201/09236 ,  H05K2201/09627 ,  H05K2201/09636 ,  H05K2201/09727 ,  H01L2924/00

Abstract: An integrated circuit package having a multi-segment transmission line transformer for impedance matching a packaged integrated circuit, such as a driver or receiver, to a printed circuit board (PCB) transmission line to which the packaged chip is attached by, for example, solder balls. In one exemplary embodiment, a three-segment transmission line transformer provides improved broadband performance with the advantage of having a middle segment with a flexible length for easier routing. The length of each end segment of the three-segment transformer is adjusted to provide at least partial cancellation of reflections between the PCB and the transformer, and between the transformer and a circuit on the integrated circuit, respectively. Further, the inductive reactance of the solder balls and via wiring may be cancelled out by the transformed chip impedance to provide a non-inductive termination to the PCB transmission line at approximately one-half the highest data rate of the channel.

Abstract translation: 一种具有多段传输线变压器的集成电路封装，用于将封装集成电路（例如驱动器或接收器）与包装芯片通过例如焊料连接到的印刷电路板（PCB）传输线进行阻抗匹配 球。 在一个示例性实施例中，三段式传输线变压器提供了改进的宽带性能，其优点在于具有具有灵活长度的中间段以便于路由。 三段式变压器的每个端段的长度被调整以分别提供PCB和变压器之间以及变压器与集成电路上的电路之间的反射的至少部分消除。 此外，焊球和通孔布线的感抗可能被转换的芯片阻抗抵消，以便以通道的最高数据速率的大约一半提供对PCB传输线的非感性端接。