公开(公告)号：US08049116B2

公开(公告)日：2011-11-01

申请号：US12175720

申请日：2008-07-18

Applicant: Pao-Nan Lee ,  Chi-Tsung Chiu

Inventor： Pao-Nan Lee ,  Chi-Tsung Chiu

IPC: H05K1/16 ,  H01F21/00

CPC classification number: H05K1/165 ,  H01F41/045 ,  H05K1/0237 ,  H05K1/029 ,  H05K3/28 ,  H05K2201/09254 ,  H05K2201/09336 ,  H05K2201/09727 ,  H05K2201/0989 ,  H05K2203/107 ,  H05K2203/171 ,  H05K2203/173 ,  H05K2203/175 ,  Y10T29/4902 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/49156

Abstract: A circuit substrate including a laminated layer, an embedded electronic device, at least a circuit structure, and a solder mask layer is provided. The embedded electronic device is disposed within the laminated layer. The circuit structure is disposed on a surface of the laminated layer and is connected between a reference plane and the embedded electronic device. In addition, the solder mask layer is disposed on the surface of the laminated layer and exposes a portion of the circuit structure. The circuit structure has a specific layout by which a circuit trace with an adjustable length can be formed by disconnecting or connecting the exposed portion of the circuit structure.

Abstract translation: 提供了包括层压层，嵌入式电子器件，至少电路结构和焊料掩模层的电路基板。 嵌入式电子设备设置在层叠层内。 电路结构设置在层叠层的表面上，并且连接在参考平面和嵌入式电子设备之间。 此外，焊料掩模层设置在层压层的表面上并暴露电路结构的一部分。 电路结构具有通过断开或连接电路结构的暴露部分可以形成具有可调节长度的电路迹线的特定布局。

公开(公告)号：US20110169148A1

公开(公告)日：2011-07-14

申请号：US13069520

申请日：2011-03-23

Applicant: Dong-Han Kim

Inventor： Dong-Han Kim

IPC: H01L23/495

CPC classification number: H01L23/4985 ,  H01L23/552 ,  H01L24/49 ,  H01L2224/05553 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/01079 ,  H05K1/0216 ,  H05K1/111 ,  H05K1/189 ,  H05K2201/09254 ,  H05K2201/09781 ,  H05K2201/10674 ,  Y02P70/611 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A tape wiring substrate may have dispersion wiring patterns. The dispersion wiring patterns may be provided between input/output wiring pattern groups to compensate for the intervals therebetween. Connecting wiring patterns may be configured to connect the dispersion wiring patterns to a first end of the adjacent input/output wiring pattern.

Abstract translation: 带状布线基板可以具有分散布线图案。 可以在输入/输出布线图案组之间设置色散布线图案，以补偿它们之间的间隔。 连接布线图案可以被配置为将色散布线图案连接到相邻输入/输出布线图案的第一端。

公开(公告)号：US20110094790A1

公开(公告)日：2011-04-28

申请号：US12694550

申请日：2010-01-27

Applicant: Gwun-Jin Lin ,  Chih-Heng Chuo ,  Kuo-Fu Su

Inventor： Gwun-Jin Lin ,  Chih-Heng Chuo ,  Kuo-Fu Su

IPC: H05K9/00 ,  H05K1/00

CPC classification number: H05K1/028 ,  H05K1/144 ,  H05K2201/043 ,  H05K2201/09063 ,  H05K2201/09109 ,  H05K2201/09254 ,  H05K2201/10598

Abstract: A flexible flat circuit cable includes first and second flexible circuit substrates extending in an extension direction. The first flexible circuit substrate has a first surface forming a first conductor layer and an insulation layer, and the second flexible circuit substrate has a first surface forming a second conductor layer and an insulation layer. A bonding material layer is applied at a predetermined section between the first flexible circuit substrate and the second flexible circuit substrate to bond the first and second flexible circuit substrates together in such a way to maintain a predetermined spacing distance between the first and second flexible circuit substrate and forming a gapped segment at sections where no bonding material is applied. The first and second flexible circuit substrates form a cluster section within the gapped segment, which has opposite ends respectively forming first and second connected sections each of which forms a connection plug or is provided with a connector.

Abstract translation: 柔性扁平电路电缆包括沿延伸方向延伸的第一和第二柔性电路基板。 第一柔性电路基板具有形成第一导体层和绝缘层的第一表面，第二柔性电路基板具有形成第二导体层和绝缘层的第一表面。 在第一柔性电路基板和第二柔性电路基板之间的预定部分处施加接合材料层，以将第一和第二柔性电路基板接合在一起，以便保持第一和第二柔性电路基板之间的预定间隔距离 并且在不施加接合材料的部分形成间隙段。 第一和第二柔性电路基板在间隙段内形成集束部分，其具有分别形成第一和第二连接部分的相对端部，每个部分形成连接插头或设置有连接器。

公开(公告)号：US07842611B2

公开(公告)日：2010-11-30

申请号：US12343740

申请日：2008-12-24

Applicant: Yoshiaki Shimizu

Inventor： Yoshiaki Shimizu

IPC: H01L21/768

CPC classification number: H05K3/242 ,  H01L2224/11 ,  H05K1/114 ,  H05K3/0038 ,  H05K3/0047 ,  H05K3/429 ,  H05K2201/09254 ,  H05K2201/09627 ,  H05K2201/10734 ,  H05K2203/0242 ,  H05K2203/175

Abstract: According to the present invention, on a double-sided substrate 1, a plurality of through-holes 2 connected to one wire 6 for plating as well as wiring are collectively arranged within a narrow range close to the connection portion. After a plating process, a penetrating hole 12 is formed and the connection potion is cut off. Thus, the wire 6 for plating and the collectively arranged through-holes 2 are made independent of one another so that no electric conduction occurs among the wire 6 for plating and the through-holes 2.

Abstract translation: 根据本发明，在双面基板1上，与连接部分附近的窄范围内共同配置多个与电镀用布线6连接的通孔2以及配线。 电镀处理后，形成贯通孔12，切断连接部。 因此，用于电镀的导线6和共同设置的通孔2彼此独立，使得在用于电镀的导线6和通孔2之间不​​会发生导电。

公开(公告)号：US20100284187A1

公开(公告)日：2010-11-11

申请号：US12663072

申请日：2008-05-21

Applicant: Hans Layer ,  Bertrand Jannon

Inventor： Hans Layer ,  Bertrand Jannon

IPC: F21S4/00

CPC classification number: H05K1/181 ,  F21K9/00 ,  F21Y2105/10 ,  F21Y2115/10 ,  H05K1/0386 ,  H05K1/056 ,  H05K2201/0284 ,  H05K2201/09254 ,  H05K2201/09318 ,  H05K2201/0949 ,  H05K2201/10106 ,  Y02P70/611

Abstract: Planar illumination device comprise light-emitting illumination elements arranged on a carrier, containing an electrically conductive layer and an insulating 5 layer (LEDs). The light-emitting illumination elements are connected to current feed lines in the form of a conductor path. The light-emitting illumination elements are arranged as a succession of identical units on a continuous conductor path, in each case on the electrically insulating layer of the carrier. The current discharge from the light-emitting illumination elements is represented by a conductor discharging the current and by means of a connection to the electrically conductive layer of the carrier. The planar illumination device has any number of units extending in the longitudinal and transverse direction. Cutting zones, along which any units or groups of units can be separated off or separated out, are arranged between the units.

Abstract translation: 平面照明装置包括布置在载体上的发光照明元件，其包含导电层和绝缘5层（LED）。 发光照明元件以导体路径的形式连接到电流馈电线。 发光照明元件在连续的导体路径上排列成相同的单元，每种情况都在载体的电绝缘层上。 来自发光照明元件的电流放电由导体排出电流并通过与载体的导电层的连接来表示。 平面照明装置具有在纵向和横向方向上延伸的任何数量的单元。 任何单位或一组单位可以分离或分离的切割区域布置在单元之间。

公开(公告)号：US07816795B2

公开(公告)日：2010-10-19

申请号：US12342742

申请日：2008-12-23

Applicant: Toru Hayashi ,  Motoo Suwa ,  Kazuo Murakami

Inventor： Toru Hayashi ,  Motoo Suwa ,  Kazuo Murakami

IPC: H01L23/58

CPC classification number: H05K1/181 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K1/0237 ,  H05K1/0298 ,  H05K2201/09254 ,  H05K2201/10159 ,  Y02P70/611 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: Synchronization between command and address signals commonly coupled to a plurality of memory devices to be operated in parallel and a clock signal coupled to the memory devices is achieved, while suppressing an increase in the clock wiring length. A semiconductor device has a data processing device mounted on a wiring substrate and a plurality of memory devices accessed in parallel by the data processing device. The data processing device outputs the command and address signals as a first frequency from command and address terminals, and outputs a clock signal as a second frequency from a clock terminal. The second frequency is set to multiple times of the first frequency, and an output timing equal to or earlier than a cycle starting phase of the clock signal output from the clock terminal can be selected to the command and address signals output from the command and address terminals.

Abstract translation: 在抑制时钟布线长度的增加的同时，实现了共同耦合到要并行操作的多个存储器件的命令和地址信号与耦合到存储器件的时钟信号之间的同步。 半导体器件具有安装在布线基板上的数据处理装置和由数据处理装置并行访问的多个存储器件。 数据处理装置从命令和地址端子输出作为第一频率的命令和地址信号，并从时钟端子输出作为第二频率的时钟信号。 第二频率被设置为第一频率的多倍，并且可以选择等于或早于从时钟端子输出的时钟信号的周期开始相位的输出定时到从命令和地址输出的命令和地址信号 终端。

公开(公告)号：US20100157547A1

公开(公告)日：2010-06-24

申请号：US12578719

申请日：2009-10-14

Applicant: EN LIANG SHEN ,  MENG HSIA HU

Inventor： EN LIANG SHEN ,  MENG HSIA HU

IPC: H05K7/00

CPC classification number: H05K1/181 ,  H05K1/023 ,  H05K2201/09254 ,  H05K2201/10106 ,  H05K2201/10636 ,  Y02P70/611

Abstract: An electronic device module comprises a carrier and first and second device regions. The first device region comprises a plurality of serially-connected devices deposited on the carrier, and the second device region is adjacent to the first device region and comprises a plurality of serially-connected devices. The voltage potential of the plurality of the serially-connected devices in the first device region is substantially the same as that of the plurality of the serially-connected devices in the second device region whereby damage due to short circuit of the adjacent plurality of serially-connected devices is avoided.

Abstract translation: 电子设备模块包括载体和第一和第二设备区域。 第一器件区域包括沉积在载体上的多个串联连接的器件，并且第二器件区域与第一器件区域相邻并且包括多个串联连接器件。 第一器件区域中的多个串联连接的器件的电压电位与第二器件区域中的多个串联连接的器件的电压电位基本相同，由此相邻的多个串联连接器件的短路造成的损坏， 避免连接的设备。

公开(公告)号：US20100116537A1

公开(公告)日：2010-05-13

申请号：US12611985

申请日：2009-11-04

Applicant: Jun ISHII ,  Toshiki NAITOU ,  Mitsuru HONJO

Inventor： Jun ISHII ,  Toshiki NAITOU ,  Mitsuru HONJO

IPC: H05K1/11 ,  H05K3/10

CPC classification number: H05K3/4685 ,  G11B5/484 ,  G11B5/4853 ,  G11B5/486 ,  H05K1/0228 ,  H05K1/0237 ,  H05K1/0265 ,  H05K1/056 ,  H05K2201/09236 ,  H05K2201/09254 ,  H05K2201/09627 ,  H05K2201/0979 ,  Y10T29/49155

Abstract: An end of a first line and an end of a second line of a first write wiring pattern are arranged on both sides of a third line of a second write wiring pattern. Circular connection portions are provided at the ends of the first line and the second line. Through holes are formed in portions of a cover insulating layer above the connection portions, respectively. First connecting layers made of copper, for example, are formed to fill the through holes of the cover insulating layer. A substantially rectangular second connecting layer made of copper, for example, is formed to integrally cover upper ends of the connecting layers. This causes the first and second lines to be electrically connected to each other through the first and second connecting layers.

Abstract translation: 第一写入布线图案的第一行的一端和第二行的末端布置在第二写入布线图案的第三行的两侧。 圆形连接部设置在第一线和第二线的端部。 分别在连接部分上方的覆盖绝缘层的部分形成通孔。 例如，由铜制成的第一连接层形成为填充覆盖绝缘层的通孔。 例如，由铜构成的大致矩形的第二连接层形成为一体地覆盖连接层的上端。 这使得第一和第二线通过第一和第二连接层彼此电连接。

公开(公告)号：US07697332B2

公开(公告)日：2010-04-13

申请号：US12000489

申请日：2007-12-13

Applicant: Pingyu Qu ,  Barrie Patrick Gahan

Inventor： Pingyu Qu ,  Barrie Patrick Gahan

IPC: G11C16/06

CPC classification number: G11C5/025 ,  G06F11/1044 ,  G11C5/04 ,  H05K1/181 ,  H05K2201/09254 ,  H05K2201/10159 ,  Y02P70/611 ,  Y10T29/49002

Abstract: A printed circuit board may include a memory controller, a plurality of synchronous data memory devices, each synchronous memory device including at least one data pin and at least one address/command pin, an ECC memory device including at least one ECC data pin and at least one ECC address/command pin, and at least one surface. The plurality of synchronous data memory devices may be arranged around a central location on the at least one surface and each synchronous data memory device may be oriented such that the at least one data pin is further from the memory controller than the at least one address/command pin.

Abstract translation: 印刷电路板可以包括存储器控制器，多个同步数据存储器件，每个同步存储器件包括至少一个数据引脚和至少一个地址/命令引脚，ECC存储器件包括至少一个ECC数据引脚和 至少一个ECC地址/命令引脚和至少一个表面。 多个同步数据存储器件可以布置在至少一个表面上的中心位置周围，并且每个同步数据存储器件可以被定向为使得至少一个数据引脚比存储器控制器更远，而不是至少一个地址/ 指令针。

公开(公告)号：US20100078211A1

公开(公告)日：2010-04-01

申请号：US12461799

申请日：2009-08-25

Applicant: Dohyung Kim ,  Jung-Mo Yang ,  Hyunjung Yoo ,  Dong-Yoon Seo

Inventor： Dohyung Kim ,  Jung-Mo Yang ,  Hyunjung Yoo ,  Dong-Yoon Seo

IPC: H05K1/11

CPC classification number: H05K1/115 ,  H05K1/0245 ,  H05K1/181 ,  H05K2201/09236 ,  H05K2201/09254 ,  H05K2201/09627 ,  H05K2201/10159

Abstract: Provided is a module having a symmetric topology. The module may include a pair of diverging via bodies configured to receive complementary signals. The pair of diverging via bodies may be further configured to diverge the complementary signals in at least three pairs of diverged complementary signals. The module may further include at least three pairs of connecting via bodies configured to receive the at least three pairs of diverged complementary signals from the pair of diverging via bodies and configured to transmit the at least three pairs of diverged complementary signals to components.

Abstract translation: 提供了具有对称拓扑的模块。 模块可以包括配置成接收互补信号的一对发散通路体。 发散通路体的一对可进一步配置成在至少三对发散互补信号中发散互补信号。 所述模块还可以包括至少三对连接通孔体，所述至少三对连接通孔体经配置以从所述一对发散通路体接收所述至少三对发散互补信号，并且被配置为将所述至少三对发散互补信号传送到组件。