公开(公告)号：US20120326272A1

公开(公告)日：2012-12-27

申请号：US13523301

申请日：2012-06-14

Applicant: Shinji ROKUHARA

Inventor： Shinji ROKUHARA

IPC: H01L27/08

CPC classification number: H01G4/33 ,  H01G4/228 ,  H01G4/385 ,  H01L23/50 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/48227 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/30107 ,  H01L2924/3011 ,  H05K1/025 ,  H05K1/162 ,  H05K2201/09345 ,  H05K2201/09663 ,  H01L2924/00

Abstract: A thin-film capacitor with first capacitative elements each having an electrode layer with a first polarity on an upper surface of a dielectric layer and an electrode layer with a second polarity on a lower surface of the dielectric layer; second capacitative elements each having an electrode layer with the second polarity on the upper surface and an electrode layer with the first polarity on the lower surface and arranged around a specific position alternately with the first capacitative elements; a single common connection hole at the specific position connecting all electrode layers with the first polarity of the first and second capacitative elements; and individual connection holes around the common connection hole connecting each electrode layer with the second polarity of the adjacent and second capacitative elements.

Abstract translation: 一种具有第一电容元件的薄膜电容器，每个电介质层在电介质层的上表面上具有第一极性的电极层和在介电层的下表面上具有第二极性的电极层; 第二电容元件各自具有在上表面上具有第二极性的电极层和在下表面上具有第一极性的电极层，并且与第一电容元件交替地布置在特定位置周围; 在所述第一和第二电容元件的第一极性连接所有电极层的特定位置处的单个公共连接孔; 以及连接每个电极层与相邻和第二电容元件的第二极性的公共连接孔周围的各个连接孔。

公开(公告)号：US08158461B2

公开(公告)日：2012-04-17

申请号：US12490872

申请日：2009-06-24

Applicant: Francesco Preda ,  Lloyd A. Walls

Inventor： Francesco Preda ,  Lloyd A. Walls

IPC: H01L21/50

CPC classification number: H01L23/50 ,  H01L23/5383 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/0253 ,  H05K1/0298 ,  H05K1/181 ,  H05K2201/09336 ,  H05K2201/09345 ,  H05K2201/10522 ,  H05K2201/10674 ,  Y02P70/611 ,  H01L2924/00 ,  H01L2224/0401

Abstract: A mechanism for continuously referencing signals over multiple layers in laminate packages provides a continuous path for signals from one layer to another while using the ideal voltage reference for all areas of the package and still avoiding discontinuities in the voltage reference. A reference plane adjustment engine analyzes a package design and identifies an ideal top plane for all areas of the package, including areas under particular chip die(s) and areas that are not under a chip die. The reference plane adjustment engine then modifies the package design to reposition ground planes, source voltage planes, signal planes, and vias between layers to maintain a continuous voltage reference regardless of the top layer. The reference plane adjustment engine provides the resulting mixed voltage plane package design to a design analysis engine. A package fabrication system fabricates the package.

Abstract translation: 用于在层压封装中连续地参考多层信号的机构提供了用于从一层到另一层的信号的连续路径，同时使用用于封装的所有区域的理想电压基准并且仍避免电压基准中的不连续性。 参考平面调整引擎分析封装设计，并为封装的所有区域（包括特定芯片裸片下的区域）和不在芯片裸片下的区域识别理想的顶层平面。 参考平面调整引擎然后修改封装设计以重新定位层之间的接地层，源电压平面，信号面和通孔，以保持连续的电压基准，而不管顶层如何。 参考平面调整引擎将所得到的混合电压平面封装设计提供给设计分析引擎。 包装制造系统制造包装。

公开(公告)号：US08085548B2

公开(公告)日：2011-12-27

申请号：US11847418

申请日：2007-08-30

Applicant: Hiroki Funato ,  Takashi Suga

Inventor： Hiroki Funato ,  Takashi Suga

IPC: H05K1/18

CPC classification number: H05K9/0039 ,  H05K1/0215 ,  H05K1/0231 ,  H05K1/116 ,  H05K3/325 ,  H05K3/429 ,  H05K2201/09345 ,  H05K2201/0979 ,  H05K2201/10409

Abstract: There is provided a circuit substrate to be mounted in an electronic apparatus, and the circuit substrate has a power supply and a GND. The GND of the circuit substrate is electrically connected to GNDs of other components of the electronic apparatus through connecting parts. The circuit substrate has a part or circuit that implements a low impedance in an intended frequency range between the peripheral conductor of the connecting part opening to be used for the connection and the power supply of the circuit substrate.

Abstract translation: 提供了要安装在电子设备中的电路基板，并且电路基板具有电源和GND。 电路基板的GND通过连接部与电子设备的其他部件的GND电连接。 电路基板具有在要用于连接的连接部分开口的外围导体和电路基板的电源之间的期望频率范围内实现低阻抗的部分或电路。

公开(公告)号：US20110088928A1

公开(公告)日：2011-04-21

申请号：US12631640

申请日：2009-12-04

Applicant: Chang Hyun LIM ,  Seog Moon Choi ,  Tae Hoon Kim ,  Young Ki Lee ,  Hye Sook Shin ,  Young Ho Sohn

Inventor： Chang Hyun LIM ,  Seog Moon Choi ,  Tae Hoon Kim ,  Young Ki Lee ,  Hye Sook Shin ,  Young Ho Sohn

IPC: H05K7/20

CPC classification number: H05K7/205 ,  H05K1/0262 ,  H05K1/0263 ,  H05K1/053 ,  H05K3/44 ,  H05K3/445 ,  H05K3/4623 ,  H05K3/4641 ,  H05K2201/09345 ,  H05K2201/09509 ,  H05K2201/09554 ,  H05K2203/0315

Abstract: Disclosed is a heat dissipating substrate, which includes a metal plate, an insulating film formed on the surface of the metal plate, a circuit pattern formed on the insulating film, and a first via formed to pass through at least a part of the metal plate so that the metal plate and the circuit pattern are electrically connected to each other, and also which exhibits superior heat dissipation effects and enables the configuration of a circuit board to be simple due to no need to additionally provide a ground layer and a power layer.

Abstract translation: 公开了一种散热基板，其包括金属板，形成在金属板的表面上的绝缘膜，形成在绝缘膜上的电路图案，以及形成为穿过金属板的至少一部分的第一通孔 使得金属板和电路图形彼此电连接，并且还表现出优异的散热效果，并且由于不需要另外提供接地层和功率层，能够使电路板的构造简单。

公开(公告)号：US20100101841A1

公开(公告)日：2010-04-29

申请号：US12537264

申请日：2009-08-07

Applicant: FA-PING FAN

Inventor： FA-PING FAN

IPC: H05K1/09 ,  H05K1/00

CPC classification number: H05K1/0218 ,  H05K2201/0715 ,  H05K2201/09309 ,  H05K2201/09345 ,  H05K2201/09354 ,  H05K2201/09618

Abstract: A printed circuit board (PCB) is disclosed. The PCB includes a dielectric layer, a power layer, a ground layer, and an electromagnetic interference reducing layer. The dielectric layer includes a central portion and a periphery portion surrounding the central portion. The dielectric layer defines a number of via holes through the periphery portion. The ground layer is adhered to a surface of the dielectric layer, covering both the central portion and the periphery portion. The power layer and the EMI reducing layer are separately adhered to another surface of the dielectric layer facing away from the conductive ground layer. The conductive power layer covers the central portion. The EMI reducing layer substantially covers the periphery portion and is electrically connected to the ground layer via the via holes.

Abstract translation: 公开了印刷电路板（PCB）。 PCB包括电介质层，功率层，接地层和电磁干扰降低层。 电介质层包括中心部分和围绕中心部分的周边部分。 电介质层通过周边部分限定多个通孔。 接地层粘附到电介质层的表面，覆盖中心部分和周边部分。 功率层和EMI降低层分别粘附到电介质层的背离导电接地层的另一表面。 导电功率层覆盖中心部分。 EMI降低层基本上覆盖周边部分，并且经由通孔电连接到接地层。

公开(公告)号：US07530043B2

公开(公告)日：2009-05-05

申请号：US11563158

申请日：2006-11-25

Applicant: Shou-Kuo Hsu ,  Cheng-Hong Liu

Inventor： Shou-Kuo Hsu ,  Cheng-Hong Liu

IPC: G06F17/50 ,  H05K7/08 ,  H05K1/11

CPC classification number: H05K1/0216 ,  H05K2201/093 ,  H05K2201/09309 ,  H05K2201/09345 ,  H05K2201/09663

Abstract: A printed circuit board includes a first layer including a first power portion and a first ground portion isolated from each other, and a second layer including a second power portion and a second ground portion isolated from each other. The second layer is spaced from the first layer. The second ground portion is arranged below the first power portion. The second power portion is arranged below the first ground portion. One portion of the first power portion overlaps one portion of the second power portion, and one portion of the first ground portion overlaps one portion of the second ground portion to provide a zero-intensity electric field between the first layer and the second layer. The first power portion is coupled to the second power portion via a first via. The first ground portion is coupled to the second ground portion via a second via.

Abstract translation: 印刷电路板包括第一层，第一层包括彼此隔离的第一电力部分和第一接地部分，以及包括彼此隔离的第二电力部分和第二接地部分的第二层。 第二层与第一层间隔开。 第二接地部分布置在第一电力部分的下方。 第二动力部分布置在第一接地部分的下方。 第一功率部分的一部分与第二功率部分的一部分重叠，并且第一接地部分的一部分与第二接地部分的一部分重叠，以在第一层和第二层之间提供零强度电场。 第一功率部分经由第一通孔耦合到第二功率部分。 第一接地部分经由第二通孔耦合到第二接地部分。

公开(公告)号：US07377033B2

公开(公告)日：2008-05-27

申请号：US11641810

申请日：2006-12-20

Applicant: John M. Lauffer ,  James M. Larnerd ,  Voya R. Markovich

Inventor： John M. Lauffer ,  James M. Larnerd ,  Voya R. Markovich

IPC: H01K3/10

CPC classification number: H01L23/49811 ,  H01L2224/16225 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/15311 ,  H05K1/0216 ,  H05K1/0256 ,  H05K1/056 ,  H05K3/0047 ,  H05K3/429 ,  H05K3/44 ,  H05K3/4641 ,  H05K2201/093 ,  H05K2201/09345 ,  H05K2201/09481 ,  H05K2201/09663 ,  H05K2201/0969 ,  H05K2203/0323 ,  H05K2203/1476 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49162 ,  Y10T29/49165 ,  Y10T29/49176 ,  H01L2224/0401

Abstract: A method of making circuitized substrate which includes a plurality of contiguous open segments which define facing edge portions within an electrically conductive layer to isolate separate portions of the conductive layer such that the layer can be used for different functions, e.g., as both power and ground elements, within a product (e.g., electrical assembly) which includes the substrate as part thereof. An information handling system, e.g., a mainframe computer, which represents one of the products in which the substrate may be utilized, is also provided.

Abstract translation: 一种制造电路化衬底的方法，其包括多个邻接的开放段，其限定导电层内的相对边缘部分以隔离导电层的分离部分，使得该层可用于不同的功能，例如电力和地面 元件，在包括基板作为其一部分的产品（例如，电气组件）内。 还提供了代表其中可以使用衬底的产品之一的信息处理系统，例如主机计算机。

公开(公告)号：US20080074857A1

公开(公告)日：2008-03-27

申请号：US11847418

申请日：2007-08-30

Applicant: HIROKI FUNATO ,  Takashi Suga

Inventor： HIROKI FUNATO ,  Takashi Suga

IPC: H05K9/00

CPC classification number: H05K9/0039 ,  H05K1/0215 ,  H05K1/0231 ,  H05K1/116 ,  H05K3/325 ,  H05K3/429 ,  H05K2201/09345 ,  H05K2201/0979 ,  H05K2201/10409

Abstract: There is provided a circuit substrate to be mounted in an electronic apparatus, and the circuit substrate has a power supply and a GND. The GND of the circuit substrate is electrically connected to GNDs of other components of the electronic apparatus through connecting parts. The circuit substrate has a part or circuit that implements a low impedance in an intended frequency range between the peripheral conductor of the connecting part opening to be used for the connection and the power supply of the circuit substrate.

Abstract translation: 提供了要安装在电子设备中的电路基板，并且电路基板具有电源和GND。 电路基板的GND通过连接部与电子设备的其它部件的GND电连接。 电路基板具有在要用于连接的连接部分开口的外围导体和电路基板的电源之间的期望频率范围内实现低阻抗的部分或电路。

公开(公告)号：US20080002337A1

公开(公告)日：2008-01-03

申请号：US11563158

申请日：2006-11-25

Applicant: SHOU-KUO HSU ,  CHENG-HONG LIU

Inventor： SHOU-KUO HSU ,  CHENG-HONG LIU

IPC: H02B1/00

CPC classification number: H05K1/0216 ,  H05K2201/093 ,  H05K2201/09309 ,  H05K2201/09345 ,  H05K2201/09663

Abstract: A printed circuit board includes a first layer including a first power portion and a first ground portion isolated from each other, and a second layer including a second power portion and a second ground portion isolated from each other. The second layer is spaced from the first layer. The second ground portion is arranged below the first power portion. The second power portion is arranged below the first ground portion. One portion of the first power portion overlaps one portion of the second power portion, and one portion of the first ground portion overlaps one portion of the second ground portion to provide a zero-intensity electric field between the first layer and the second layer. The first power portion is coupled to the second power portion via a first via. The first ground portion is coupled to the second ground portion via a second via.

Abstract translation: 印刷电路板包括第一层，第一层包括彼此隔离的第一电力部分和第一接地部分，以及包括彼此隔离的第二电力部分和第二接地部分的第二层。 第二层与第一层间隔开。 第二接地部分布置在第一电力部分的下方。 第二动力部分布置在第一接地部分的下方。 第一功率部分的一部分与第二功率部分的一部分重叠，并且第一接地部分的一部分与第二接地部分的一部分重叠，以在第一层和第二层之间提供零强度电场。 第一功率部分经由第一通孔耦合到第二功率部分。 第一接地部分经由第二通孔耦合到第二接地部分。

公开(公告)号：US07239527B1

公开(公告)日：2007-07-03

申请号：US11009408

申请日：2004-12-08

Applicant: Joel R. Goergen

Inventor： Joel R. Goergen

IPC: H01R12/16

CPC classification number: H05K1/0237 ,  H05K1/0219 ,  H05K1/0225 ,  H05K3/429 ,  H05K2201/044 ,  H05K2201/093 ,  H05K2201/09345 ,  H05K2201/09609 ,  H05K2201/09663

Abstract: For electrical backplanes and the like, a power plane adaptation to improve the propagation of high-speed signals through clearances in an embedded power plane is disclosed. In exemplary embodiments, the power plane is segmented in a high-speed connector region, such that a portion of the metal layer that forms the power plane is retained in the high-speed connector region—but isolated from the power-delivery portion of the power plane. The isolated portion is connected to digital ground, and clearances are formed therein where high-speed signaling throughholes will pass through the region. In some embodiments, various attainable advantages include better manufacturability, better matching and control of high-speed signaling throughhole impedance, and improved noise isolation. Other embodiments are described and claimed.

Abstract translation: 对于电气背板等，公开了一种用于改善高速信号通过嵌入式电源平面中的间隙的传播的电力平面适配。 在示例性实施例中，电力平面在高速连接器区域中分段，使得形成电力平面的金属层的一部分保持在高速连接器区域中，但是与电力输送部分 电力飞机 隔离部分连接到数字地，并且在其中形成间隙，其中高速信令通孔将通过该区域。 在一些实施例中，各种可获得的优点包括更好的可制造性，更好地匹配和控制高速信号通孔阻抗以及改进的噪声隔离。 描述和要求保护其他实施例。