公开(公告)号：US06537850B1

公开(公告)日：2003-03-25

申请号：US10123328

申请日：2002-04-15

Applicant: David J. Corisis

Inventor： David J. Corisis

IPC: H01L2144

CPC classification number: H01L24/12 ,  H01L23/49838 ,  H01L23/5386 ,  H01L24/11 ,  H01L24/16 ,  H01L24/48 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/0518 ,  H01L2224/05599 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/11334 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/32225 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/48464 ,  H01L2224/73215 ,  H01L2224/85424 ,  H01L2224/85444 ,  H01L2224/85455 ,  H01L2224/8547 ,  H01L2224/92 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01039 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01083 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K1/111 ,  H05K2201/0979 ,  H05K2203/049 ,  Y02P70/611 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor component includes a substrate, bonding pads on the substrate, and terminal contacts bonded to the bonding pads. Exemplary components include semiconductor packages, semiconductor wafers and semiconductor dice. Exemplary terminal contacts include contact balls, contact bumps and contact columns. In each case, the terminal contacts can be arranged in a dense array, such as a ball grid array (BGA), or fine ball grid array (FBGA). The component also includes patterns of primary conductors on the substrate in electrical communication with the bonding pads and with the terminal contacts. Selected terminal contacts, particularly those most likely to experience fatigue failure due to thermal loads, are in electrical communication with the primary conductors and also with one or more secondary conductors. The secondary conductors are configured to provide alternate electrical paths for the selected terminal contacts should damage occur to the primary conductors. In addition, the secondary conductors are configured to rigidify the bonding pads and terminal contacts so that separation from the substrate is less likely to occur.

Abstract translation: 半导体部件包括基板，基板上的接合焊盘和接合到接合焊盘的端子触点。 示例性组件包括半导体封装，半导体晶片和半导体晶片。 示例性端子触点包括接触球，接触凸块和接触柱。 在每种情况下，端子触点可以布置成密集的阵列，例如球栅阵列（BGA）或细球栅阵列（FBGA）。 该部件还包括在基板上与接合焊盘和端子触点电连通的主导体图案。 所选择的端子触点，特别是由于热负载而最可能遭受疲劳故障的端子触头与主导体以及一个或多个次级导体电连通。 次级导体被配置为为主导体发生损坏时为所选择的端子触点提供可选的电路径。 此外，次级导体被配置为使接合焊盘和端子触点硬化，使得不太可能发生与衬底的分离。

公开(公告)号：US06531772B2

公开(公告)日：2003-03-11

申请号：US09832053

申请日：2001-04-10

Applicant: Salman Akram ,  James M. Wark ,  David R. Hembree

Inventor： Salman Akram ,  James M. Wark ,  David R. Hembree

IPC: H01L2334

CPC classification number: H01L23/5382 ,  H01L24/97 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/14 ,  H05K1/0292 ,  H05K1/0295 ,  H05K2201/0979 ,  H05K2201/10159 ,  H05K2201/10674 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A method and apparatus for repair of a multi-chip module, such as a memory module, is provided, where at least one redundant or auxiliary chip attach location is provided on the substrate of the multi-chip module. The auxiliary chip attach location preferably provides contacts for attachment of more than one type of replacement semiconductor chip. Accordingly, when one or more chips on the multi-chip module are found to be completely or partially defective, at least one replacement chip can be selected and attached to the auxiliary location to provide additional memory to bring the module back to its design capacity.

Abstract translation: 提供了一种用于修复诸如存储器模块的多芯片模块的方法和装置，其中在多芯片模块的基板上提供至少一个冗余或辅助芯片连接位置。 辅助芯片安装位置优选地提供用于连接多于一种类型的替换半导体芯片的触点。 因此，当发现多芯片模块上的一个或多个芯片完全或部分缺陷时，可以选择至少一个替换芯片并附加到辅助位置，以提供额外的存储器以使模块回到其设计能力。

公开(公告)号：US20030035277A1

公开(公告)日：2003-02-20

申请号：US09905474

申请日：2001-07-13

Inventor： Stephanus D. Saputro ,  Lan Zhang

IPC: H05K007/10 ,  H05K007/08 ,  H05K007/06 ,  H05K007/02 ,  H05K001/18

CPC classification number: H05K1/113 ,  G06F1/189 ,  H05K1/0231 ,  H05K1/0298 ,  H05K1/114 ,  H05K1/115 ,  H05K2201/0979 ,  H05K2201/10636 ,  Y02P70/611

Abstract: The inductance of the capacitor is reduced by connecting the capacitor directly to a via. In one embodiment inductance of a capacitor is reduced by a plurality of via, the number of via greater than the number of electrical couplings from the voltage pad to the voltage plane. In one embodiment the capacitor has a ground pad of a minimum size. In another embodiment the capacitor is electrically coupled to a trace having a length reduced to minimize inductance.

Abstract translation: 通过将电容器直接连接到通孔来减小电容器的电感。 在一个实施例中，电容器的电感被多个通孔减少，通孔的数量大于从电压焊盘到电压平面的电耦合的数量。 在一个实施例中，电容器具有最小尺寸的接地焊盘。 在另一个实施例中，电容器电耦合到具有减小的长度的迹线以最小化电感。

公开(公告)号：US06483045B1

公开(公告)日：2002-11-19

申请号：US09626409

申请日：2000-07-26

Applicant: Mu-Chun Wang ,  Shih-Chieh Kao ,  Shiang Huang-Lu ,  Yuan-Chang Liu

Inventor： Mu-Chun Wang ,  Shih-Chieh Kao ,  Shiang Huang-Lu ,  Yuan-Chang Liu

IPC: H05K111

CPC classification number: H01L23/528 ,  H01L23/5226 ,  H01L2924/0002 ,  H05K1/115 ,  H05K2201/0769 ,  H05K2201/0969 ,  H05K2201/0979 ,  H01L2924/00

Abstract: A via plug layout structure for connecting different metallic layers. The structure includes a plurality of via plugs arranged in a fan-shaped pattern and a plurality of empty bars positioned between a single via plug and the fanned-out via plugs so that incoming current to the single via plug is equally distributed to every one of the fanned-out via plug and current stress in each fanned-out via plug is identical. Hence, via plugs having particularly serious electromigration problem can be discovered. In addition, single via plug having different critical dimension can be fabricated so that maximum critical dimension sustainable by the via plug is determined after an electromigration test.

Abstract translation: 用于连接不同金属层的通孔插头布局结构。 该结构包括布置成扇形图案的多个通孔塞和位于单个通孔插头和扇形通孔之间的多个空杆，使得到单个通孔塞的进入电流被均等地分配到 通过插头的每个扇形插头中的插头和电流应力都是相同的。 因此，可以发现通过具有特别严重的电迁移问题的插头。 此外，可以制造具有不同临界尺寸的单通孔塞，使得在电迁移测试之后确定由通孔插塞可持续的最大临界尺寸。

公开(公告)号：US06414248B1

公开(公告)日：2002-07-02

申请号：US09679252

申请日：2000-10-04

Applicant: Lance L. Sundstrom

Inventor： Lance L. Sundstrom

IPC: H05K116

CPC classification number: H05K1/141 ,  H05K3/28 ,  H05K3/3436 ,  H05K3/368 ,  H05K2201/049 ,  H05K2201/09481 ,  H05K2201/09627 ,  H05K2201/0979 ,  H05K2201/10378 ,  H05K2201/10734 ,  Y02P70/613 ,  Y10T29/49149

Abstract: Parallel surfaces are interfacially mechanically bonded and optionally electrically, and/or thermally connected using an interposer fabricated from a flexible laminates, such as flex PWB. The bond/connection points for the device made on one side of the interposer are displaced in the X and Y axis from the bond/connection points on the other or obverse side for the interposer and the board. The optional electrical/thermal connection through the interposer is made through one or more traces and vias in the flex board.

Abstract translation: 使用由柔性层压板（例如柔性板）制成的插入件，平行表面被界面机械地接合并且任选地电气和/或热连接。 在插入器的一侧上形成的器件的接合/连接点在X和Y轴上从用于插入器和板的另一侧或正面的接合/连接点移位。 通过插入器的可选电/热连接通过柔性板中的一个或多个迹线和通孔进行。

公开(公告)号：US06407340B1

公开(公告)日：2002-06-18

申请号：US09653941

申请日：2000-09-01

Applicant: Bo Wikström ,  Lennart Olsson

Inventor： Bo Wikström ,  Lennart Olsson

IPC: H05K100

CPC classification number: H05K1/0242 ,  H01L23/367 ,  H01L23/5283 ,  H01L23/538 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K1/0209 ,  H05K1/0265 ,  H05K1/111 ,  H05K2201/0373 ,  H05K2201/09236 ,  H05K2201/09254 ,  H05K2201/09381 ,  H05K2201/09663 ,  H05K2201/09681 ,  H05K2201/09781 ,  H05K2201/0979 ,  H05K2201/10636 ,  Y02P70/611 ,  H01L2924/00

Abstract: An electronics device comprising a carrier, such as a printed circuit board, a substrate or a chip, and an electric conductor on a surface of the carrier. The surface of the conductor (2) facing away from the carrier has a surface structure (3, 4; 6, 7) in the form of flanges which are defined by etched grooves.

Abstract translation: 一种电子设备，包括载体，例如印刷电路板，基底或芯片，以及载体表面上的导电体。 导体（2）的背离载体的表面具有法兰形式的由蚀刻槽形成的表面结构（3,4; 6,7）。

公开(公告)号：US06312791B1

公开(公告)日：2001-11-06

申请号：US09648862

申请日：2000-08-25

Applicant: Benjamin V. Fasano ,  David H. Gabriels ,  Richard F. Indyk ,  Sundar M. Kamath ,  Scott I. Langenthal ,  Srinivasa S. N. Reddy ,  Rao V. Vallabhaneni

Inventor： Benjamin V. Fasano ,  David H. Gabriels ,  Richard F. Indyk ,  Sundar M. Kamath ,  Scott I. Langenthal ,  Srinivasa S. N. Reddy ,  Rao V. Vallabhaneni

IPC: B32B300

CPC classification number: H05K3/4092 ,  H05K1/0306 ,  H05K1/113 ,  H05K3/4053 ,  H05K3/4611 ,  H05K3/4629 ,  H05K2201/09781 ,  H05K2201/0979 ,  Y10T428/24917 ,  Y10T428/24926

Abstract: Disclosed is a multilayer ceramic substrate having an outer pad, for example an I/O pad, which is anchored to a middle pad of the multilayer ceramic substrate by a plurality of vias which in turn is anchored to an inner pad of the multilayer ceramic substrate by a second plurality of vias. The middle and outer pads and vias are made of high metal material, preferably 100% metal, so they won't adhere very well to the ceramic substrate. The inner pad is a composite metal/ceramic material which will bond very well to the ceramic substrate.

Abstract translation: 公开了一种多层陶瓷基板，其具有外焊盘，例如I / O焊盘，其通过多个通孔锚定到多层陶瓷基板的中间焊盘，所述多个通孔又固定到多层陶瓷基板的内焊盘 通过第二多个通孔。 中间和外部焊盘和通孔由高金属材料制成，优选为100％金属，因此它们不会很好地粘附到陶瓷基板上。 内垫是复合金属/陶瓷材料，其将很好地结合到陶瓷基底上。

公开(公告)号：US06303875B1

公开(公告)日：2001-10-16

申请号：US09236441

申请日：1999-01-25

Applicant: Shoichi Hata

Inventor： Shoichi Hata

IPC: H05K116

CPC classification number: H05K1/111 ,  H01L23/49838 ,  H01L2924/0002 ,  H05K1/0295 ,  H05K1/116 ,  H05K2201/0979 ,  H05K2201/09954 ,  H05K2201/10689 ,  Y02P70/611 ,  H01L2924/00

Abstract: There are provided IC packages which eliminate the need for preparing a plurality of wiring boards even when different types of IC packages are used and a circuit device using the same. A 128-pin package is arranged, so as to output the same signal from two pins positioned on both ends of each edge thereof and wires of a wiring board corresponding to those pins are short-circuited.

Abstract translation: 提供IC封装，即使在使用不同类型的IC封装时也不需要制备多个布线板，以及使用该封装的电路装置。 布置了128引脚封装，以便从位于其每个边缘的两端的两个引脚输出相同的信号，并且与这些引脚相对应的布线板的引线短路。

公开(公告)号：US06266016B1

公开(公告)日：2001-07-24

申请号：US09686637

申请日：2000-10-11

Applicant: Leif Bergstedt ,  Spartak Georgian

Inventor： Leif Bergstedt ,  Spartak Georgian

IPC: H01Q138

CPC classification number: H01P3/084 ,  H01Q9/0407 ,  H01Q9/045 ,  H01Q13/206 ,  H01Q21/0081 ,  H05K1/024 ,  H05K1/0245 ,  H05K2201/09618 ,  H05K2201/09672 ,  H05K2201/0979 ,  H05K2201/098 ,  H05K2201/09972

Abstract: The invention relates to a microstrip arrangement comprising a first and a second microstrip conductor. The two microstrip conductors have essentially the same dimensions in their longitudinal direction and transverse direction, and are galvanically interconnected by means of at least one connection. The two microstrip conductors also extend essentially parallel to one another on either side of a dielectric material. As a result of this design of the microstrip arrangement, the field losses and also other influences caused by the dielectric material will be very considerably reduced, and in practice a resultant microstrip arrangement is obtained, which, with regard to its electrical performance, appears to be suspended in the air. Preferred embodiments comprise a microstrip antenna, a circuit board and a conductor application.

Abstract translation: 本发明涉及一种包括第一和第二微带导体的微带布置。 两个微带导体在其纵向和横向上具有基本上相同的尺寸，并且通过至少一个连接电流互连。 两个微带导体也在电介质材料的任一侧基本上彼此平行地延伸。 作为这种微带布置设计的结果，由介电材料引起的场损耗和其它影响将会非常显着地降低，并且在实践中获得了微结构的微结构，对于其电性能来说， 悬挂在空中。 优选实施例包括微带天线，电路板和导体应用。

公开(公告)号：US20010004942A1

公开(公告)日：2001-06-28

申请号：US09741455

申请日：2000-12-19

Inventor： Simone Rehm ,  Roland Frech ,  Erich Klink ,  Helmut Virag ,  Thomas-Michael Winkel ,  Wiren Becker ,  Bruce Chamberlin ,  Wai Ma

IPC: H05K001/11

CPC classification number: H05K1/113 ,  H05K1/0231 ,  H05K1/115 ,  H05K3/429 ,  H05K2201/09472 ,  H05K2201/0979 ,  H05K2201/10522 ,  H05K2201/10636 ,  Y02P70/611 ,  Y10T29/4913

Abstract: Described is a method for minimizing switching noise in the high- and mid-frequency range on printed circuit cards or boards by means of a plurality of surface mounted decoupling capacitors. A novel configuration and implementation of capacitor pads including the connecting vias is also presented. As a result the parasitic inductance of the pads and vias can be significantly reduced. Thus the effectiveness of the decoupling capacitors in the mid and high frequency range can be increased, the voltage drop can be reduced and the system performance can be increased. Several design rules for the new pad via configuration lead to the significant reduction of the parasitic inductance. The proposal is especially important for high integrated system designs on boards and cards combined with increased cycle times.

Abstract translation: 描述了一种通过多个表面安装的去耦电容器来最小化印刷电路板或板上的高频和中频范围内的开关噪声的方法。 还介绍了包括连接通孔的电容器焊盘的新颖配置和实现。 结果，焊盘和通孔的寄生电感可以显着降低。 因此，可以提高中高频区域中的去耦电容器的有效性，可以降低电压降并且可以提高系统性能。 新焊盘通过配置的几个设计规则导致寄生电感的显着减少。 该建议对于板卡和卡上的高集成系统设计以及增加的周期时间尤其重要。