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公开(公告)号：US20240152296A1
公开(公告)日：2024-05-09
申请号：US18077190
申请日：2022-12-07
Applicant: PHISON ELECTRONICS CORP.
Inventor： Yu-Heng Liu , Yu-Siang Yang , An-Cheng Liu , Wei Lin
IPC: G06F3/06
CPC classification number: G06F3/0619 , G06F3/0653 , G06F3/0659 , G06F3/0679
Abstract: A data reading method, a memory storage device, and a memory control circuit unit are disclosed. The method includes: receiving a read command from a host system, and the read command instructs reading data from at least one logical unit, and the logical unit is mapped to a first physical unit; obtaining state information of at least two neighboring memory cells in the first physical unit; determining an electrical parameter offset value corresponding to the neighboring memory cells according to the state information; and sending a read command sequence according to the electrical parameter offset value, and the read command sequence instructs reading the first physical unit based on at least one electrical parameter, and the electrical parameter is controlled by the electrical parameter offset value.
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112.发明授权公开(公告)号：US11972139B2
公开(公告)日：2024-04-30
申请号：US17679109
申请日：2022-02-24
Applicant: PHISON ELECTRONICS CORP.
Inventor： Shih-Jia Zeng , Chun-Wei Tsao , Hsiao-Yi Lin , Wei Lin
CPC classification number: G06F3/0655 , G06F3/0604 , G06F3/0679 , G11C16/26 , G11C29/021 , G11C29/028
Abstract: A read voltage level correction method, a memory storage device, and a memory control circuit unit are provided. The method includes: using a first read voltage level as an initial read voltage level to perform a first data read operation on a first physical unit among multiple physical units to obtain a second read voltage level used to successfully read the first physical unit; recording association information between the first read voltage level and the second read voltage level in a transient look-up table; and performing a second data read operation according to a read level tracking table and the association information recorded in the transient look-up table.
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公开(公告)号：US11962328B1
公开(公告)日：2024-04-16
申请号：US17994399
申请日：2022-11-28
Applicant: PHISON ELECTRONICS CORP.
Inventor： Shih-Jia Zeng , Yi-Fang Chang , Chun-Wei Tsao , Chen-An Hsu , Wei Lin
CPC classification number: H03M13/1555 , H03M13/015 , H03M13/1575
Abstract: A decoding method, a memory storage device and a memory control circuit unit are disclosed. The method includes: activating a decoding circuit which supports a plurality of decoding modes each corresponding to a threshold value, wherein a distribution of the threshold value corresponds to error correction abilities of the decoding modes; reading first data from a rewritable non-volatile memory module; performing, by the decoding circuit, a first decoding operation on the first data; obtaining a decoding parameter according to an execution result of the first decoding operation; and performing, by the decoding circuit, a second decoding operation on the first data based on a first decoding mode among the decoding modes according to a relative numerical relationship between the decoding parameter and the threshold value.
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公开(公告)号：US11829644B2
公开(公告)日：2023-11-28
申请号：US17581858
申请日：2022-01-22
Applicant: PHISON ELECTRONICS CORP.
Inventor： Po-Cheng Su , Chih-Wei Wang , Yu-Cheng Hsu , Wei Lin
CPC classification number: G06F3/0659 , G06F3/0619 , G06F3/0679
Abstract: A memory control method, a memory storage device, and a memory control circuit unit are provided. The memory control method includes: receiving a read command from a host system; in response to a first physical erasing unit being a first type physical unit, sending a first operation command sequence to instruct a rewritable non-volatile memory module to read a first physical programming unit based on a first electronic configuration; and in response to the first physical erasing unit being a second type physical unit, sending a second operation command sequence to instruct the rewritable non-volatile memory module to read the first physical programming unit based on a second electronic configuration. The first electronic configuration is different from the second electronic configuration.
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公开(公告)号：US20230176783A1
公开(公告)日：2023-06-08
申请号：US17581858
申请日：2022-01-22
Applicant: PHISON ELECTRONICS CORP.
Inventor： Po-Cheng Su , Chih-Wei Wang , Yu-Cheng Hsu , Wei Lin
IPC: G06F3/06
CPC classification number: G06F3/0659 , G06F3/0619 , G06F3/0679
Abstract: A memory control method, a memory storage device, and a memory control circuit unit are provided. The memory control method includes: receiving a read command from a host system; in response to a first physical erasing unit being a first type physical unit, sending a first operation command sequence to instruct a rewritable non-volatile memory module to read a first physical programming unit based on a first electronic configuration; and in response to the first physical erasing unit being a second type physical unit, sending a second operation command sequence to instruct the rewritable non-volatile memory module to read the first physical programming unit based on a second electronic configuration. The first electronic configuration is different from the second electronic configuration.
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Patent Agency Ranking
公开(公告)号：US11615848B2
公开(公告)日：2023-03-28
申请号：US17214958
申请日：2021-03-29
Applicant: PHISON ELECTRONICS CORP.
Inventor： Yu-Siang Yang , Wei Lin , An-Cheng Liu , Yu-Heng Liu , Chun-Hsi Lai , Ting-Chien Zhan
Abstract: A memory control method, a memory storage device, and a memory control circuit unit are provided. The memory control method includes: programming multiple first memory cells in a first physical erasing unit in a rewritable non-volatile memory module; and applying an electronic pulse to at least one word line in the rewritable non-volatile memory module. The at least one word line is coupled to multiple second memory cells in the first physical erasing unit. The second memory cells include the first memory cells. The electronic pulse is not configured to read, program, or erase the second memory cells.
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117.发明授权公开(公告)号：US11604586B2
公开(公告)日：2023-03-14
申请号：US16921874
申请日：2020-07-06
Applicant: PHISON ELECTRONICS CORP.
Inventor： Wei Lin , Yu-Cheng Hsu , Hsiao-Yi Lin , Yu-Siang Yang
IPC: G06F3/06
Abstract: A data protection method, a memory storage device and a memory control circuit unit are provided. The method includes: setting a plurality of disk array tags corresponding to a plurality of word lines and a plurality of memory planes, and the plurality of disk array tags corresponding to one of the word lines connected to one of the memory planes are at least partially identical to the plurality of disk array tags corresponding to another one of the word lines connected to another one of the memory planes; receiving a write command and data corresponding to the write command from a host system; and sequentially writing the data into the plurality of word lines and the plurality of memory planes corresponding to the plurality of disk array tags.
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公开(公告)号：US20220293185A1
公开(公告)日：2022-09-15
申请号：US17214958
申请日：2021-03-29
Applicant: PHISON ELECTRONICS CORP.
Inventor： Yu-Siang Yang , Wei Lin , An-Cheng Liu , Yu-Heng Liu , Chun-Hsi Lai , Ting-Chien Zhan
Abstract: A memory control method, a memory storage device, and a memory control circuit unit are provided. The memory control method includes: programming multiple first memory cells in a first physical erasing unit in a rewritable non-volatile memory module; and applying an electronic pulse to at least one word line in the rewritable non-volatile memory module. The at least one word line is coupled to multiple second memory cells in the first physical erasing unit. The second memory cells include the first memory cells. The electronic pulse is not configured to read, program, or erase the second memory cells.
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公开(公告)号：US11373713B1
公开(公告)日：2022-06-28
申请号：US17209214
申请日：2021-03-22
Applicant: PHISON ELECTRONICS CORP.
Inventor： Shih-Jia Zeng , Lih Yuarn Ou , Hsiao-Yi Lin , Wei Lin
Abstract: A memory control method, a memory storage device, and a memory control circuit unit are provided. The memory control method includes: reading multiple first memory cells using multiple read voltage levels to obtain a first threshold voltage distribution of the first memory cells; obtaining shift information of the first threshold voltage distribution with respect to an original threshold voltage distribution of the first memory cells; obtaining first reliability information corresponding to the first threshold voltage distribution; recovering original reliability information corresponding to the original threshold voltage distribution according to a statistical characteristic of the first reliability information; adjusting the original reliability information according to the shift information to obtain second reliability information corresponding to the first threshold voltage distribution; and updating reliability information related to the first memory cells according to the second reliability information.
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公开(公告)号：US11101820B1
公开(公告)日：2021-08-24
申请号：US16889808
申请日：2020-06-02
Applicant: PHISON ELECTRONICS CORP.
Inventor： Wei Lin , Shih-Jia Zeng , Yu-Cheng Hsu , Yu-Siang Yang
Abstract: A memory control method for a rewritable non-volatile memory module is provided according to an exemplary embodiment of the disclosure. The method includes: sending a first read command sequence which indicates a reading of a first physical unit by using a first read voltage level to obtain first data; decoding the first data; sending a second read command sequence which indicates a reading of the first physical unit by using a second read voltage level to obtain second data; decoding the second data with assistance information to improve a decoding success rate of the second data if the second read voltage level meets a first condition or the second data meets a second condition; and decoding the second data without the assistance information if the second read voltage level does not meet the first condition and the second data does not meet the second condition.
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