公开(公告)号：US4292106A

公开(公告)日：1981-09-29

申请号：US51837

申请日：1979-06-25

Applicant: C. George Herschdorfer ,  Dennis J. Vaughan

Inventor： C. George Herschdorfer ,  Dennis J. Vaughan

IPC: B29C47/00 ,  B29C70/50 ,  B32B27/12 ,  C08J5/08 ,  H05K1/03 ,  H05K3/02 ,  B29D7/14 ,  B29D7/16 ,  B29D9/04 ,  B29D23/04

CPC classification number: C08J5/08 ,  B29C47/0004 ,  B29C70/506 ,  B32B27/12 ,  H05K1/0313 ,  H05K1/0366 ,  H05K1/0373 ,  H05K3/022 ,  B29C47/0021 ,  B29C47/0066 ,  B29C47/02 ,  B29K2101/10 ,  B29K2301/10 ,  C08J2323/02 ,  H05K1/032 ,  H05K2201/012 ,  H05K2201/0158 ,  H05K2201/0239 ,  H05K2201/0355 ,  H05K2203/122 ,  H05K2203/1545

Abstract: A process for producing reinforced laminates from crosslinkable thermoplastic olefin polymer material. In the process, a normally solid, high molecular weight crosslinkable thermoplastic olefin polymer containing a catalyst which reacts with and effects crosslinking of the polymer and which has a decomposition temperature above the melting temperature of the polymer, is heated to a molten state at a temperature above the polymer melting temperature but below the catalyst decomposition temperature. A continuous nonreinforced sheet is then formed from the molten polymer at a temperature below the decomposition temperature and is applied to at least one surface of a substrate to form a laminate. The laminate is then heated under pressure to a temperature above the decomposition temperature of the catalyst to effect substantially complete crosslinking of the polymer and is cooled to a temperature below the polymer melting temperature to a self-supporting state to fix the shape of the laminate.

Abstract translation: 一种由可交联热塑性烯烃聚合物材料生产增强层压材料的方法。 在该方法中，含有与聚合物反应并实现聚合物交联并且具有高于聚合物熔融温度的分解温度的催化剂的通常为固体，高分子量的可交联热塑性烯烃聚合物在温度下被加热至熔融状态 高于聚合物熔融温度但低于催化剂分解温度。 然后在低于分解温度的温度下由熔融聚合物形成连续的非增强片，并施加到基底的至少一个表面以形成层压体。 然后将层压体在压力下加热到高于催化剂分解温度的温度，以实现聚合物的基本上完全的交联，并将其冷却至低于聚合物熔融温度的温度，使之达到自支撑状态以固定层压体的形状。

公开(公告)号：US3770571A

公开(公告)日：1973-11-06

申请号：US3770571D

申请日：1969-04-02

Applicant: RICHARDSON CO

Inventor： ALSBERG H ,  FREDERIKSEN R

IPC: A47J31/06 ,  H05K1/03 ,  H05K3/18 ,  H05K3/38 ,  H05K3/42 ,  B32B15/08

CPC classification number: H05K3/387 ,  H05K1/032 ,  H05K3/181 ,  H05K3/38 ,  H05K3/426 ,  H05K2201/0133 ,  H05K2201/0158 ,  H05K2203/1105 ,  Y10S205/92 ,  Y10S264/59 ,  Y10T428/24917 ,  Y10T428/31696

Abstract: The invention is directed to a printed circuit board with a substrate characterized by a polymeric hydrocarbon surface based on a conjugated diene polymer such as butadiene polymer, and a metal coating directly bonded as by electroless deposition to at least a portion of the hydrocarbon surface. In particular, the printed circuit board is characterized by a reinforced hydrocarbon substrate based on the conjugated diene polymer and an unusually superior bond between the metal and hydrocarbon surface. One method of producing the board is carried out with an uncured polymer as the hydrocarbon surface wherein after the metallizing step, the board is subjected to curing conditions to form a thermoset substrate.

Abstract translation: 本发明涉及具有基底的印刷电路板，其特征在于基于共轭二烯聚合物如丁二烯聚合物的聚合烃表面，以及通过无电沉积直接键合到至少一部分烃表面的金属涂层。 特别地，印刷电路板的特征在于基于共轭二烯聚合物的增强烃基材和金属和烃表面之间非常优异的粘合。 制造板的一种方法是用未固化的聚合物作为烃表面进行，其中在金属化步骤之后，对板进行固化条件以形成热固性基材。

公开(公告)号：US11818835B2

公开(公告)日：2023-11-14

申请号：US17172769

申请日：2021-02-10

Applicant: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD. ,  TOMOEGAWA CO., LTD.

Inventor： Hiroaki Takahashi ,  Kiyotaka Komori ,  Masaya Koyama ,  Jun Tochihira ,  Ryu Harada

IPC: H05K1/02 ,  B32B27/20 ,  B32B27/32 ,  B32B15/08 ,  H05K1/03 ,  H05K3/02 ,  B32B15/085 ,  B32B15/20 ,  H05K3/46

CPC classification number: H05K1/024 ,  B32B15/08 ,  B32B15/085 ,  B32B15/20 ,  B32B27/20 ,  B32B27/32 ,  H05K1/036 ,  H05K1/0373 ,  H05K1/0393 ,  H05K3/022 ,  H05K3/4673 ,  B32B2270/00 ,  B32B2307/202 ,  B32B2307/206 ,  B32B2457/08 ,  H05K2201/0133 ,  H05K2201/0141 ,  H05K2201/0158 ,  H05K2201/0195

Abstract: A multilayer printed wiring board including one or more insulating layers 2 and at least one conductive layer 1 which are stacked alternately is disclosed. The one or more insulating layers 2 include at least one liquid crystal polymer resin layer 4 so that each of the one or more insulating layers 2 includes at least one layer selected from a group consisting of at least one polyolefin resin layer 3 and the at least one liquid crystal polymer resin layer 4. A percentage by volume of the at least one liquid crystal polymer resin layer 4 relative to the one or more insulating layers 2 is within a range of 5 to 90%.

公开(公告)号：US20180332721A1

公开(公告)日：2018-11-15

申请号：US15773373

申请日：2016-11-18

Applicant: Mitsui Mining & Smelting Co., Ltd.

Inventor： Toshiyuki SHIMIZU ,  Toshifumi MATSUSHIMA ,  Yoshihiro YONEDA

IPC: H05K3/46 ,  H05K1/02

CPC classification number: H05K3/4652 ,  B32B15/08 ,  B32B37/26 ,  B32B2037/268 ,  B32B2307/204 ,  B32B2457/08 ,  H05K1/0298 ,  H05K1/162 ,  H05K3/4623 ,  H05K3/4682 ,  H05K2201/0154 ,  H05K2201/0158 ,  H05K2201/0187 ,  H05K2201/0209 ,  H05K2201/0355 ,  H05K2203/0156

Abstract: A production method includes: preparing a metal clad laminate including a dielectric layer ≤30 μm thick, a first metal foil on a first surface of the dielectric layer, a second metal foil on a second surface of the dielectric layer, first and second carriers on the metal foil via a releasable layer; arranging the pair of metal clad laminates on a resin substrate so the first carrier of each metal clad laminate faces the resin substrate on each surface of the resin substrate; releasing the second carrier from a laminated member to expose the second metal foil; forming a pattern on the second metal foil; arranging an insulating layer on the pattern and arranging a metal layer on the insulating layer; and separating the first carrier and the first metal foil from each other. The dielectric layer has a strain energy at break of 1.8 MJ or less.

公开(公告)号：US20180223048A1

公开(公告)日：2018-08-09

申请号：US15686232

申请日：2017-08-25

Applicant: Zhen Ding Technology Co., Ltd.

Inventor： MAO-FENG HSU ,  SHOU-JUI HSIANG ,  SZU-HSIANG SU ,  YU-WEN KAO ,  CHIA-YIN TENG ,  MING-JAAN HO ,  YAO-YI CHENG ,  HSIN-MIN HSIAO

IPC: C08G81/02 ,  C09D179/08 ,  C03C17/32 ,  H05K1/03 ,  H05K3/22 ,  H05K1/02

CPC classification number: C08G81/024 ,  C03C17/32 ,  C03C2218/32 ,  C08G73/1014 ,  C08G73/1039 ,  C08G73/105 ,  C08G73/1071 ,  C09D179/08 ,  H05K1/024 ,  H05K1/0326 ,  H05K1/034 ,  H05K1/0393 ,  H05K3/22 ,  H05K2201/0158 ,  H05K2203/0759

Abstract: A resin composition having lower dielectric constant Dk, lower dielectric loss Df, lower water absorption, higher surface impedance, and higher glass transition temperature includes resins. The resins have a chemical structure selected from a group consisting of or any combination thereof.

公开(公告)号：US09966333B2

公开(公告)日：2018-05-08

申请号：US15725144

申请日：2017-10-04

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Li-Chuan Tsai ,  Chih-Cheng Lee

IPC: H05K1/11 ,  H05K1/16 ,  H05K1/09 ,  H05K1/03 ,  H05K7/00 ,  H05K1/18 ,  H01L23/498 ,  H05K1/02 ,  H01L21/48 ,  H05K3/00 ,  H05K3/22 ,  H05K3/36 ,  H05K3/40 ,  H01L23/00

CPC classification number: H01L23/49838 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/17 ,  H01L2224/16227 ,  H01L2924/15153 ,  H01L2924/15313 ,  H01L2924/19105 ,  H05K1/0266 ,  H05K1/0298 ,  H05K1/111 ,  H05K1/115 ,  H05K1/181 ,  H05K1/183 ,  H05K3/0017 ,  H05K3/0026 ,  H05K3/0047 ,  H05K3/22 ,  H05K3/36 ,  H05K3/40 ,  H05K3/4682 ,  H05K3/4697 ,  H05K2201/0158 ,  H05K2201/09472 ,  H05K2201/09527 ,  H05K2201/10204 ,  H05K2203/166 ,  Y02P70/611

Abstract: A semiconductor substrate includes: (1) a first dielectric structure having a first surface and a second surface opposite the first surface; (2) a second dielectric structure having a third surface and a fourth surface opposite the third surface, wherein the fourth surface faces the first surface, the second dielectric structure defining a through hole extending from the third surface to the fourth surface, wherein a cavity is defined by the through hole and the first dielectric structure; (3) a first patterned conductive layer, disposed on the first surface of the first dielectric structure; and (4) a second patterned conductive layer, disposed on and contacting the second surface of the first dielectric structure and including at least one conductive trace, wherein the first dielectric structure defines at least one opening, and a periphery of the opening corresponds to a periphery of the through hole of the second dielectric structure.

公开(公告)号：US20180009141A1

公开(公告)日：2018-01-11

申请号：US15679146

申请日：2017-08-16

Applicant: NINGBO SUNNY OPOTECH CO., LTD.

Inventor： Mingzhu WANG ,  Bojie Zhao ,  Takehiko Tanaka ,  Nan Guo ,  Zhenyu Chen ,  Heng Jiang ,  Zhongyu Luan ,  Fengsheng Xi ,  Feifan Chen ,  Liang Ding

IPC: B29C45/14 ,  H04M1/02 ,  G02B7/02 ,  G02B7/00 ,  G02B5/20 ,  H04N5/225 ,  H01L27/146 ,  B29L31/34

CPC classification number: G02B7/021 ,  B29C45/14639 ,  B29L2031/3481 ,  G02B3/0075 ,  G02B5/201 ,  G02B7/006 ,  G02B13/001 ,  G02B13/004 ,  H01L21/565 ,  H01L25/0655 ,  H01L27/14618 ,  H01L27/14625 ,  H01L27/14627 ,  H01L27/14634 ,  H01L27/14636 ,  H01L27/14685 ,  H01L27/14687 ,  H01L27/1469 ,  H04M1/0264 ,  H04N5/2252 ,  H04N5/2253 ,  H04N5/2254 ,  H04N5/2257 ,  H04N5/2258 ,  H05K1/0203 ,  H05K1/0274 ,  H05K1/183 ,  H05K1/185 ,  H05K1/189 ,  H05K2201/0141 ,  H05K2201/0158 ,  H05K2201/0175 ,  H05K2201/09036 ,  H05K2201/10121

Abstract: An array imaging module includes a molded photosensitive assembly which includes a supporting member, at least a circuit board, at least two photosensitive units, at least two lead wires, and a mold sealer. The photosensitive units are coupled at the chip coupling area of the circuit board. The lead wires are electrically connected the photosensitive units at the chip coupling area of the circuit board. The mold sealer includes a main mold body and has two optical windows. When the main mold body is formed, the lead wires, the circuit board and the photosensitive units are sealed and molded by the main mold body of the mold sealer, such that after the main mold body is formed, the main mold body and at least a portion of the circuit board are integrally formed together at a position that the photosensitive units are aligned with the optical windows respectively.

公开(公告)号：US20170367192A1

公开(公告)日：2017-12-21

申请号：US15612357

申请日：2017-06-02

Applicant: Nanoshield Technology Co. Ltd.

Inventor： James Cheng LEE

IPC: H05K3/28 ,  H05K1/18 ,  H05K3/30

CPC classification number: H05K3/284 ,  H05K1/185 ,  H05K3/285 ,  H05K3/303 ,  H05K2201/0104 ,  H05K2201/015 ,  H05K2201/0158 ,  H05K2201/0179 ,  H05K2201/0257 ,  H05K2203/1333

Abstract: A method for waterproofing a device and the resulting device are provided. The device includes a printed circuit board assembly (PCBA), which includes a printed circuit board, and at least one electronic component disposed on the printed circuit board. A waterproof coating such as a polymer coating is disposed on or in contact with at least one portion of the at least one electronic component. A nanofilm is disposed on the PCBA. The nanofilm includes an inner coating and an outer coating. The inner coating is disposed on the printed circuit board or in contact with the waterproof coating. The inner coating comprises metal oxide nanoparticles having a particle diameter in a range of about 5 nm to about 100 nm. The outer coating in contact with the inner coating, and comprises silicon dioxide nanoparticles having a particle diameter in a range of 0.1 nm to 10 nm.

公开(公告)号：US20170347448A1

公开(公告)日：2017-11-30

申请号：US15676519

申请日：2017-08-14

Applicant: Intel Corporation

Inventor： Christopher Jezewski ,  Ravi Pillarisetty ,  Brian Doyle

IPC: H05K1/03 ,  D03D11/02 ,  D03D15/00 ,  H05K3/00 ,  H05K3/10 ,  H05K3/32 ,  D03D1/00 ,  H05K3/28 ,  H05K1/02 ,  H05K1/18

CPC classification number: H05K1/038 ,  D03D1/0088 ,  D03D11/02 ,  D03D15/00 ,  H05K1/028 ,  H05K1/0393 ,  H05K1/189 ,  H05K3/0058 ,  H05K3/10 ,  H05K3/28 ,  H05K3/284 ,  H05K3/32 ,  H05K2201/0145 ,  H05K2201/015 ,  H05K2201/0154 ,  H05K2201/0158 ,  H05K2201/029

Abstract: A system comprises an article comprising one or more fabric layers, a. plurality of electronic devices, each being incorporated into or onto one of the one or more fabric layers, and one or more communication links between two or more of the plurality of electronic devices. Each of the plurality of electronic devices can comprise a flexible substrate coupled to the fabric layer, one or more metallization layers deposited on the flexible substrate, and one or more electronic components electrically coupled to the one or more metallization layers.

公开(公告)号：US20170223827A1

公开(公告)日：2017-08-03

申请号：US15489945

申请日：2017-04-18

Applicant: YAZAKI Corporation

Inventor： Maki YAMADA ,  Hiroki KONDO ,  Makoto KAMBE

IPC: H05K1/03 ,  H05K1/09 ,  H05K1/18 ,  H05K3/12 ,  H05K3/32

CPC classification number: H05K1/0353 ,  H05K1/09 ,  H05K1/095 ,  H05K1/181 ,  H05K1/189 ,  H05K3/0014 ,  H05K3/12 ,  H05K3/1208 ,  H05K3/284 ,  H05K3/32 ,  H05K2201/0145 ,  H05K2201/0158 ,  H05K2201/10272 ,  H05K2203/095

Abstract: A film-like printed circuit board includes: a low-melting-point resin film substrate composed of a low-melting-point resin in which a melting point is 370° C. or less; a circuit formed in a manner that a circuit-forming conductive paste applied onto the low-melting-point resin film substrate is subjected to plasma baking; an electronic component bonding layer formed in a manner that a mounting conductive paste applied onto the circuit is subjected to the plasma baking; and an electronic component mounted on the circuit via the electronic component bonding layer.