-
公开(公告)号：US08449949B2
公开(公告)日：2013-05-28
申请号：US13214624
申请日：2011-08-22
Applicant: Yueh-Ling Lee , Shane Fang
Inventor： Yueh-Ling Lee , Shane Fang
IPC: H05K3/02
CPC classification number: B32B27/08 , B32B5/147 , B32B27/18 , B32B27/20 , B32B27/281 , B32B27/302 , B32B27/308 , B32B27/322 , B32B27/34 , B32B27/36 , B32B27/38 , B32B2260/021 , B32B2260/046 , B32B2262/101 , B32B2264/102 , B32B2270/00 , B32B2307/206 , B32B2307/714 , B32B2457/00 , H05K1/0373 , H05K3/0032 , H05K3/184 , H05K3/185 , H05K2201/0112 , H05K2201/0236 , H05K2203/107 , Y10T29/49156 , Y10T428/26 , Y10T428/31504 , Y10T428/31511 , Y10T428/3154 , Y10T428/31721 , Y10T428/31725 , Y10T428/31786 , Y10T428/31855 , Y10T428/31942
Abstract: The present invention is directed to non-lithographic patterning by laser (or similar-type energy beam) ablation, where the ablation system ultimately results in circuitry features that are relative free from debris induced over-plating defects (debris relating to the ablation process) and fully additive plating induced over-plating defects. Compositions of the invention include a circuit board precursor having an insulating substrate and a cover layer. The insulating substrate is made from a dielectric material and also a metal oxide activatable filler. The cover layer can be sacrificial or non-sacrificial and is used to remediate unwanted debris arising from the ablation process.
-
公开(公告)号：US08436254B2
公开(公告)日：2013-05-07
申请号：US13301812
申请日：2011-11-22
Applicant: Cheng-Po Yu , Han-Pei Huang
Inventor： Cheng-Po Yu , Han-Pei Huang
IPC: H05K1/00
CPC classification number: H05K1/11 , H05K1/0284 , H05K1/142 , H05K3/185 , H05K3/4007 , H05K3/4661 , H05K2201/0236 , H05K2201/09045 , H05K2201/09118 , H05K2201/09163 , H05K2201/09436 , H05K2201/09509 , H05K2201/09845 , H05K2203/1327 , Y10T29/49126 , Y10T29/49128 , Y10T29/49155 , Y10T29/49158 , Y10T428/24802 , Y10T428/24917
Abstract: A method of fabrication a circuit board structure comprising providing a circuit board main body, forming a molded, irregular plastic body having a non-plate type, stereo structure and at least one scraggy surface by encapsulating at least a portion of said circuit board main body with injection molded material, and forming a first three-dimensional circuit pattern on said molded, irregular plastic body thereby defining a three-dimensional circuit device.
Abstract translation: 一种制造电路板结构的方法，包括提供电路板主体，通过封装所述电路板主体的至少一部分来形成具有非板型，立体结构和至少一个刮痕表面的模制的不规则塑料体 并且在所述模制的不规则塑料体上形成第一三维电路图案，从而限定三维电路装置。
-
公开(公告)号：US20130040071A1
公开(公告)日：2013-02-14
申请号：US13653423
申请日：2012-10-17
Applicant: UNIMICRON TECHNOLOGY CORP.
Inventor： Cheng-Po Yu , Chi-Min Chang , Wei-Ming Cheng
CPC classification number: H05K3/185 , H05K3/0032 , H05K3/107 , H05K3/465 , H05K3/4661 , H05K2201/0236
Abstract: A method for fabricating a circuit board is provided. A non-conductive material layer is provided on a core substrate, wherein the non-conductive material layer comprises a dielectric material and catalytic particles. A recessed circuit structure is then formed in the non-conductive material layer with a laser beam. Simultaneously, the catalytic particles in the recessed circuit structure are activated with aid of the laser. A buried conductive structure is then formed in the recessed circuit structure by chemical copper deposition methods.
Abstract translation: 提供一种制造电路板的方法。 非导电材料层设置在芯基板上，其中非导电材料层包括电介质材料和催化颗粒。 然后在非导电材料层中用激光束形成凹陷的电路结构。 同时，凹陷电路结构中的催化颗粒借助于激光器被激活。 然后通过化学铜沉积方法在凹陷电路结构中形成掩埋导电结构。
-
公开(公告)号：US08187478B2
公开(公告)日：2012-05-29
申请号：US12211637
申请日：2008-09-16
Applicant: Yi-Chun Liu
Inventor： Yi-Chun Liu
IPC: H01B13/00
CPC classification number: H05K3/107 , H05K3/045 , H05K3/184 , H05K3/465 , H05K3/4661 , H05K2201/0236 , H05K2203/1173 , H05K2203/1338 , Y10T29/49155
Abstract: A fabricating process of a structure with an embedded circuit is described as follows. Firstly, a substrate having an upper surface and a lower surface opposite to the upper surface is provided. Afterward, a dielectric layer is formed on the upper surface of the substrate. Next, a plating-resistant layer is formed on the dielectric layer. Then, the plating-resistant layer and the dielectric layer are patterned for forming an recess pattern on the dielectric layer. Subsequently, a conductive base layer is formed in the recess pattern by using a chemical method, and the plating-resistant layer is exposed by the conductive base layer. After that, the plating-resistant layer is removed.
Abstract translation: 具有嵌入电路的结构的制造工艺描述如下。 首先，提供具有与上表面相对的上表面和下表面的基板。 之后，在基板的上表面形成电介质层。 接下来，在电介质层上形成耐电镀层。 然后，对电镀层和电介质层进行图案化以在电介质层上形成凹陷图案。 随后，通过使用化学方法在凹陷图案中形成导电性基底层，并且通过导电性基底层露出耐电镀层。 之后，除去耐电镀层。
-
公开(公告)号：US20110253435A1
公开(公告)日：2011-10-20
申请号：US13166133
申请日：2011-06-22
Applicant: Han-Pei Huang , Cheng-Hung Yu
Inventor： Han-Pei Huang , Cheng-Hung Yu
CPC classification number: H05K3/4644 , B33Y10/00 , B33Y80/00 , H05K1/0284 , H05K3/046 , H05K3/06 , H05K3/185 , H05K3/205 , H05K3/386 , H05K2201/0236 , H05K2201/09118 , H05K2203/0108 , H05K2203/013 , H05K2203/107 , Y10T29/49126 , Y10T29/49128 , Y10T29/49155 , Y10T29/49165
Abstract: A multilayer three-dimensional circuit structure and a manufacturing method thereof are provided in the present invention. The manufacturing method includes following steps. First, a three-dimensional insulating structure is provided. A first three-dimensional circuit structure is then formed on a surface of the three-dimensional insulating structure. Next, an insulating layer covering the first three-dimensional circuit structure is formed. Thereafter, a second three-dimensional circuit structure is formed on the insulating layer. Subsequently, at least a conductive via penetrating the insulating layer is formed for electrically connecting the second three-dimensional circuit structure and the first three-dimensional circuit structure.
Abstract translation: 本发明提供了一种多层三维电路结构及其制造方法。 制造方法包括以下步骤。 首先，提供三维绝缘结构。 然后在三维绝缘结构的表面上形成第一三维电路结构。 接下来，形成覆盖第一三维电路结构的绝缘层。 此后，在绝缘层上形成第二三维电路结构。 随后，至少形成了穿过绝缘层的导电通孔，用于电连接第二三维电路结构和第一三维电路结构。
-
Patent Agency Ranking
116.发明授权公开(公告)号：US07987589B2
公开(公告)日：2011-08-02
申请号：US12333014
申请日：2008-12-11
Applicant: Han-Pei Huang , Cheng-Hung Yu
Inventor： Han-Pei Huang , Cheng-Hung Yu
IPC: H05K3/02
CPC classification number: H05K3/4644 , B33Y10/00 , B33Y80/00 , H05K1/0284 , H05K3/046 , H05K3/06 , H05K3/185 , H05K3/205 , H05K3/386 , H05K2201/0236 , H05K2201/09118 , H05K2203/0108 , H05K2203/013 , H05K2203/107 , Y10T29/49126 , Y10T29/49128 , Y10T29/49155 , Y10T29/49165
Abstract: A multilayer three-dimensional circuit structure and a manufacturing method thereof are provided in the present invention. The manufacturing method includes following steps. First, a three-dimensional insulating structure is provided. A first three-dimensional circuit structure is then formed on a surface of the three-dimensional insulating structure. Next, an insulating layer covering the first three-dimensional circuit structure is formed. Thereafter, a second three-dimensional circuit structure is formed on the insulating layer. Subsequently, at least a conductive via penetrating the insulating layer is formed for electrically connecting the second three-dimensional circuit structure and the first three-dimensional circuit structure.
Abstract translation: 本发明提供了一种多层三维电路结构及其制造方法。 制造方法包括以下步骤。 首先，提供三维绝缘结构。 然后在三维绝缘结构的表面上形成第一三维电路结构。 接下来，形成覆盖第一三维电路结构的绝缘层。 此后，在绝缘层上形成第二三维电路结构。 随后，至少形成了穿过绝缘层的导电通孔，用于电连接第二三维电路结构和第一三维电路结构。
-
公开(公告)号：US20110143922A1
公开(公告)日：2011-06-16
申请号：US12854366
申请日：2010-08-11
Applicant: Cheng-Hsien Lee , Yi-Chun Liu
Inventor： Cheng-Hsien Lee , Yi-Chun Liu
CPC classification number: H05K3/4661 , C23C18/2066 , H05K3/107 , H05K3/181 , H05K3/465 , H05K2201/0236
Abstract: A composition with catalyst particles for making a circuit pattern is provided. The composition includes an insulation material and a plurality of catalyst particles. The catalyst particles are distributed in the insulation material and not made of metal. When the composition is bathed in a chemical plating solution, a redox reaction takes place between some of the catalyst particles and the chemical plating solution so as to deposit a conductive pattern on the composition.
Abstract translation: 提供具有用于制造电路图案的催化剂颗粒的组合物。 该组合物包括绝缘材料和多个催化剂颗粒。 催化剂颗粒分布在绝缘材料中，不由金属制成。 当组合物浸在化学镀溶液中时，在一些催化剂颗粒和化学镀溶液之间发生氧化还原反应，以便在组合物上沉积导电图案。
-
公开(公告)号：US20110094778A1
公开(公告)日：2011-04-28
申请号：US12606192
申请日：2009-10-27
Applicant: Cheng-Po Yu , Chi-Min Chang , Wei-Ming Cheng
Inventor： Cheng-Po Yu , Chi-Min Chang , Wei-Ming Cheng
CPC classification number: H05K3/185 , H05K3/0032 , H05K3/107 , H05K3/465 , H05K3/4661 , H05K2201/0236
Abstract: A method for fabricating a circuit board is provided. A non-conductive material layer is provided on a core substrate, wherein the non-conductive material layer comprises a dielectric material and catalytic particles. A recessed circuit structure is then formed in the non-conductive material layer with a laser beam. Simultaneously, the catalytic particles in the recessed circuit structure are activated with aid of the laser. A buried conductive structure is then formed in the recessed circuit structure by chemical copper deposition methods.
Abstract translation: 提供一种制造电路板的方法。 非导电材料层设置在芯基板上，其中非导电材料层包括电介质材料和催化颗粒。 然后在非导电材料层中用激光束形成凹陷的电路结构。 同时，凹陷电路结构中的催化颗粒借助于激光器被激活。 然后通过化学铜沉积方法在凹陷电路结构中形成掩埋导电结构。
-
119.发明申请公开(公告)号：US20110091697A1
公开(公告)日：2011-04-21
申请号：US12580256
申请日：2009-10-16
Applicant: Tzyy-Jang Tseng , Shu-Sheng Chiang
Inventor： Tzyy-Jang Tseng , Shu-Sheng Chiang
CPC classification number: H05K3/422 , B32B7/06 , B32B27/06 , B32B27/36 , B32B2255/00 , B32B2255/10 , B32B2255/205 , B32B2255/28 , B32B2264/105 , B32B2307/204 , B32B2307/40 , B32B2307/748 , B32B2457/08 , H05K3/0035 , H05K3/185 , H05K3/285 , H05K3/4007 , H05K3/421 , H05K2201/0236 , H05K2201/0367 , H05K2203/0191 , H05K2203/0565 , H05K2203/1415 , Y10T29/49124 , Y10T29/49144 , Y10T29/49149 , Y10T29/49165 , Y10T428/24917
Abstract: A method for fabricating a solder pad structure. A circuit board having thereon at least one copper pad is provided. A solder resist is formed on the circuit board and covers the copper pad. A solder resist opening, which exposes a portion of the copper pad, is formed in the solder resist by laser. The laser also creates a laser activated layer on sidewalls of the solder resist opening. A chemical copper layer is then grown from the exposed copper pad and concurrently from the laser activated layer.
Abstract translation: 一种制造焊盘结构的方法。 其上设置有至少一个铜焊盘的电路板。 在电路板上形成阻焊剂并覆盖铜焊盘。 通过激光在阻焊剂中形成露出铜焊盘的一部分的阻焊剂开口。 激光器还在阻焊剂开口的侧壁上产生激光激活层。 然后从暴露的铜垫生长化学铜层，同时从激光活化层生长化学铜层。
-
120.发明授权公开(公告)号：US07772118B2
公开(公告)日：2010-08-10
申请号：US12061768
申请日：2008-04-03
Applicant: Takaharu Yamano
Inventor： Takaharu Yamano
IPC: H01L21/44 , H01L23/52 , H01L23/48 , H01L29/40 , H01L21/768
CPC classification number: H01L21/76898 , H01L23/481 , H01L2224/16 , H01L2224/16225 , H01L2924/00011 , H01L2924/00014 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/1461 , H05K1/0306 , H05K3/007 , H05K3/205 , H05K3/423 , H05K3/4605 , H05K3/4661 , H05K2201/0236 , H05K2201/09563 , H05K2201/09581 , H05K2201/096 , H05K2201/10378 , H05K2203/0723 , H05K2203/0733 , H05K2203/1105 , H05K2203/1383 , Y10T29/49165 , H01L2924/00 , H01L2224/0401
Abstract: A disclosed substrate is composed of a base member having a through-hole, a penetrating via provided in the through-hole, and a wiring connected to the penetrating via. The penetrating via includes a penetrating part having two ends on both sides of the base member, which is provided in the through-hole, a first protrusion protruding from the base member, which is formed on a first end of the penetrating part so as to be connected to the wiring, and a second protrusion protruding from the base member, which is formed on a second end of the penetrating part. The first protrusion and second protrusion are wider than a diameter of the through-hole.
Abstract translation: 所公开的基板由具有通孔的基部构件，设置在通孔中的贯通孔以及与贯通孔连接的配线构成。 贯通孔包括贯通部，该贯通部在基部构件的两侧设置有设置在贯通孔中的两端，从基体突出的第一突起，该第一突起形成在贯通部的第一端上，从而 连接到布线，以及形成在穿透部的第二端上的从基部构件突出的第二突起。 第一突起和第二突起比通孔的直径宽。
-
-
-
-
-
-
-
-
-
Search Results
192
records
(took 0.019 seconds)
