公开(公告)号：US20100139969A1

公开(公告)日：2010-06-10

申请号：US12379480

申请日：2009-02-23

Applicant: Jin Yong An ,  Ki Hwan Kim

Inventor： Jin Yong An ,  Ki Hwan Kim

IPC: H05K1/11 ,  B05D5/12 ,  H05K3/00

CPC classification number: H05K3/4007 ,  H01L2224/16225 ,  H01L2224/81192 ,  H05K3/061 ,  H05K3/243 ,  H05K3/4644 ,  H05K3/4682 ,  H05K2201/0355 ,  H05K2201/0367 ,  H05K2201/09481 ,  H05K2201/096 ,  H05K2203/054 ,  H05K2203/1536

Abstract: Disclosed herein is a printed circuit board, including: metal bumps having constant diameters and protruding over an insulation layer; a circuit layer formed beneath the insulation layer; and vias passing through the insulation layer to connect the metal bumps with the circuit layer.

Abstract translation: 这里公开了一种印刷电路板，包括：具有恒定直径并在绝缘层上突出的金属凸块; 形成在绝缘层之下的电路层; 以及通过绝缘层的通孔以将金属凸块与电路层连接。

公开(公告)号：US20100139964A1

公开(公告)日：2010-06-10

申请号：US12382360

申请日：2009-03-13

Applicant: Jin Yong An ,  Jae Joon Lee

Inventor： Jin Yong An ,  Jae Joon Lee

IPC: H05K1/11 ,  B44C1/22

CPC classification number: H05K3/4007 ,  H01L21/4857 ,  H01L23/49811 ,  H01L23/49822 ,  H01L2221/68345 ,  H01L2924/0002 ,  H05K3/108 ,  H05K3/205 ,  H05K3/4682 ,  H05K2201/0367 ,  H05K2203/0228 ,  H05K2203/0376 ,  H05K2203/054 ,  Y10T29/49126 ,  Y10T29/49165 ,  H01L2924/00

Abstract: Disclosed herein is a printed circuit board, including: an upper circuit layer including connection pads made of a conductive metal and buried in an insulation layer; and metal bumps, each having a constant diameter, which are integrated with the connection pads and protrude over the insulation layer.

Abstract translation: 这里公开了一种印刷电路板，包括：上电路层，包括由导电金属制成的并埋在绝缘层中的连接焊盘; 和金属凸块，每个具有恒定的直径，其与连接焊盘成一体并突出在绝缘层上。

公开(公告)号：US20100132997A1

公开(公告)日：2010-06-03

申请号：US12629438

申请日：2009-12-02

Applicant: Takuya HANDO

Inventor： Takuya HANDO

IPC: H01R12/00 ,  H05K3/10

CPC classification number: H05K3/4682 ,  H01L23/49816 ,  H01L23/49822 ,  H01L2221/68345 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/1461 ,  H01L2924/15174 ,  H01L2924/15311 ,  H05K3/0097 ,  H05K3/205 ,  H05K3/244 ,  H05K3/4007 ,  H05K2201/0355 ,  H05K2201/0367 ,  H05K2203/0369 ,  H05K2203/1536 ,  Y10T29/49155 ,  Y10T29/49162 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A multilayer wiring substrate is manufactured through a recess forming step, a gold-diffusion-prevention-layer forming step, a terminal forming step, resin-insulating-layer forming step, a conductor forming step, and a metal-layer removing step. In the recess forming step, a copper foil layer is half-etched so as to form recesses. In the gold-diffusion-prevention-layer forming step, a gold diffusion prevention layer is formed in each recess. In the terminal forming step, a gold layer, a nickel layer, and a copper layer are stacked in sequence on the gold diffusion prevention layer to thereby form a surface connection terminal. In the resin-insulating-layer forming step, a resin insulating layer is formed, and, in the conductor forming step, via conductors and conductor layers are formed. In the metal-layer removing step, the copper foil layer and the gold diffusion prevention layer are removed so that the gold layer projects from the main face of the laminated structure.

Abstract translation: 通过凹陷形成步骤，金扩散防止层形成步骤，端子形成步骤，树脂绝缘层形成步骤，导体形成步骤和金属层去除步骤制造多层布线基板。 在凹部形成工序中，铜箔层被半蚀刻形成凹部。 在金扩散防止层形成工序中，在各凹部中形成金扩散防止层。 在端子形成工序中，将金层，镍层和铜层依次层叠在金扩散防止层上，形成表面连接端子。 在树脂绝缘层形成工序中，形成树脂绝缘层，在导体形成工序中形成通孔导体和导体层。 在金属层除去工序中，除去铜箔层和金扩散防止层，使金层从层叠结构体的主面突出。

公开(公告)号：US20100103635A1

公开(公告)日：2010-04-29

申请号：US12603324

申请日：2009-10-21

Applicant: Risto TUOMINEN ,  Petteri PALM

Inventor： Risto TUOMINEN ,  Petteri PALM

IPC: H05K1/18

CPC classification number: H05K1/188 ,  H01L21/4846 ,  H01L21/568 ,  H01L23/5385 ,  H01L23/5389 ,  H01L23/544 ,  H01L23/552 ,  H01L24/24 ,  H01L24/82 ,  H01L25/105 ,  H01L25/50 ,  H01L2223/54426 ,  H01L2224/04105 ,  H01L2224/19 ,  H01L2224/24137 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01055 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/1461 ,  H01L2924/3025 ,  H01L2924/3511 ,  H05K1/0269 ,  H05K3/4611 ,  H05K2201/0355 ,  H05K2201/0367 ,  H05K2201/09918 ,  H05K2201/10674 ,  H05K2203/063 ,  H05K2203/166 ,  H01L2924/00

Abstract: A single-layer component package comprising: a single conductive-pattern layer having a first surface; an insulating-material layer on the first surface of the single conductive-pattern layer; in an installation cavity inside the insulating-material layer, a semiconductor component having flat contact zones; and solid contact pillars containing copper and solderlessly, metallurgically and electrically connecting the flat contact zones to the single conductive-pattern layer.

Abstract translation: 一种单层部件封装，包括：具有第一表面的单个导电图案层; 在单个导电图案层的第一表面上的绝缘材料层; 在绝缘材料层内的安装空腔中，具有平坦的接触区域的半导体部件; 以及包含铜和无焊料的固体接触柱，将扁平接触区冶金和电连接到单个导电图案层。

公开(公告)号：US07703889B2

公开(公告)日：2010-04-27

申请号：US11113459

申请日：2005-04-25

Applicant: Hirosumi Ito

Inventor： Hirosumi Ito

IPC: B41J2/14 ,  B41J2/16 ,  B41J2/05

CPC classification number: H05K3/4007 ,  B41J2/14209 ,  B41J2002/14217 ,  B41J2002/14225 ,  B41J2002/14306 ,  B41J2002/14459 ,  B41J2002/14491 ,  H05K3/0058 ,  H05K3/321 ,  H05K3/361 ,  H05K3/365 ,  H05K2201/0133 ,  H05K2201/0367 ,  H05K2201/091 ,  H05K2201/10977 ,  H05K2203/0195

Abstract: There is disclosed a printed wiring board comprising: an electrically insulating flexible layer which has on one of its opposite sides a protrusion which forms a corresponding recess on the other side of the flexible layer; an electrically conducting layer formed on the protrusion; and a wire formed on the flexible layer, connected to the conducting layer, and extending in a direction. The conducting layer has a shape long in the direction of extension of the wire.

Abstract translation: 公开了一种印刷电路板，包括：电绝缘柔性层，其在其相对侧的一侧上具有在柔性层的另一侧上形成相应凹部的突起; 形成在所述突起上的导电层; 以及形成在柔性层上的导线，连接到导电层并沿一个方向延伸。 导电层具有沿导线延伸方向长的形状。

公开(公告)号：US07679196B2

公开(公告)日：2010-03-16

申请号：US11639045

申请日：2006-12-14

Applicant: Takanori Sekido ,  You Kondoh

Inventor： Takanori Sekido ,  You Kondoh

IPC: H01L29/41 ,  H05K7/02

CPC classification number: H01L21/50 ,  B81B2207/012 ,  B81B2207/017 ,  B81C1/00301 ,  B81C1/00333 ,  H01L2224/16 ,  H05K1/144 ,  H05K2201/0367 ,  H05K2201/0379 ,  H05K2201/042 ,  H05K2201/2018

Abstract: A stacked mounting structure includes at least two substrates namely a first substrate on which a first protruding electrode is formed and a second substrate on which a second protruding electrode is formed, and an intermediate substrate which is disposed between the first substrate and the second substrate, and which connects the first substrate and the second substrate by leaving a predetermined gap between the first substrate and the second substrate. Mounted components are disposed in the gap between the first substrate and the second substrate. The first protruding electrode and the second protruding electrode are connected in an opening which is provided in the intermediate substrate.

Abstract translation: 堆叠安装结构包括至少两个基板，即其上形成有第一突出电极的第一基板和形成有第二突出电极的第二基板，以及设置在第一基板和第二基板之间的中间基板， 并且通过在第一基板和第二基板之间留下预定的间隙来连接第一基板和第二基板。 安装的部件设置在第一基板和第二基板之间的间隙中。 第一突出电极和第二突出电极在设置在中间基板中的开口部连接。

公开(公告)号：US20100059866A1

公开(公告)日：2010-03-11

申请号：US12207986

申请日：2008-09-10

Applicant: KiYoun Jang ,  SungSoo Kim ,  YongHee Kang

Inventor： KiYoun Jang ,  SungSoo Kim ,  YongHee Kang

IPC: H01L21/768 ,  H01L23/538

CPC classification number: H01L23/49811 ,  H01L21/4846 ,  H01L21/6835 ,  H01L23/498 ,  H01L23/49827 ,  H01L24/06 ,  H01L2221/68359 ,  H01L2221/68363 ,  H01L2224/0401 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30105 ,  H05K3/108 ,  H05K3/205 ,  H05K3/4007 ,  H05K2201/0367 ,  H05K2201/0376 ,  H05K2201/097 ,  H05K2201/09736 ,  H05K2203/049 ,  H05K2203/1476 ,  H01L2924/00

Abstract: A semiconductor device has a vertically offset bond on trace (BOT) interconnect structure. The vertical offset is achieved by forming a first conductive layer extending above a surface of a carrier. The first conductive layer is pressed into a surface of a substrate so that the first conductive layer is recessed below the surface of the substrate. The carrier is removed. A second conductive layer is formed above the surface of the substrate to create the vertical offset between the first and second conductive layers. The vertical offset is about 20 micrometers. A conductive via is formed through the substrate. Bond wire bumps are formed on the first and second conductive layers. The bond wire bumps are about 10 micrometers in height. A seed layer is formed over the carrier prior to forming the first conductive layer and removed after forming the second conducive layer.

Abstract translation: 半导体器件具有在迹线（BOT）互连结构上的垂直偏移接合。 通过形成在载体的表面上方延伸的第一导电层来实现垂直偏移。 将第一导电层压入基板的表面，使得第一导电层在基板的表面下方凹入。 载体被移除。 在衬底的表面上方形成第二导电层，以在第一和第二导电层之间产生垂直偏移。 垂直偏移约为20微米。 通过衬底形成导电通孔。 在第一导电层和第二导电层上形成接合线凸块。 接合线凸块的高度约为10微米。 在形成第一导电层之前在载体上形成种子层，并且在形成第二导电层之后去除。

公开(公告)号：US07667144B2

公开(公告)日：2010-02-23

申请号：US11854343

申请日：2007-09-12

Applicant: Shao-Chien Lee ,  Chih-Ming Chang

Inventor： Shao-Chien Lee ,  Chih-Ming Chang

IPC: H01R12/04 ,  H05K1/11

CPC classification number: H05K3/4007 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/48 ,  H01L25/105 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/051 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16237 ,  H01L2224/4824 ,  H01L2924/00014 ,  H05K3/06 ,  H05K3/205 ,  H05K3/243 ,  H05K2201/0367 ,  H05K2203/0376 ,  Y10T29/49124 ,  Y10T29/49128 ,  Y10T29/49147 ,  Y10T29/49153 ,  Y10T29/49204 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A circuit board including a dielectric layer, a circuit layer, at least one conductive joint column, and a solder mask layer is provided. The circuit layer having at least one pad is in contact with the dielectric layer. The conductive joint column is disposed on the pad. The solder mask layer is disposed on the dielectric layer and covers the circuit layer. The solder mask layer is in contact with the conductive joint column, and the conductive joint column penetrates the solder mask layer. A height of the conductive joint column is larger than a thickness of the solder mask layer. The enhanced reliability of bonding between another component and the conductive joint column will be provided. Further, a method of fabricating a circuit board is also provided.

Abstract translation: 提供了包括电介质层，电路层，至少一个导电接合柱和焊料掩模层的电路板。 具有至少一个焊盘的电路层与电介质层接触。 导电接头柱设置在垫上。 焊料掩模层设置在电介质层上并覆盖电路层。 焊接掩模层与导电接头柱接触，并且导电接头柱穿透焊接掩模层。 导电接头柱的高度大于焊料掩模层的厚度。 将提供另一部件与导电接头柱之间的接合的可靠性增强。 此外，还提供了一种制造电路板的方法。

公开(公告)号：US07665999B2

公开(公告)日：2010-02-23

申请号：US12270956

申请日：2008-11-14

Applicant: Gareth G. Hougham ,  Brian S. Beaman ,  Evan G. Colgan ,  Paul W. Coteus ,  Stefano S. Oggioni ,  Enrique Vargas

Inventor： Gareth G. Hougham ,  Brian S. Beaman ,  Evan G. Colgan ,  Paul W. Coteus ,  Stefano S. Oggioni ,  Enrique Vargas

IPC: H01R12/00

CPC classification number: H01R12/714 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01R12/52 ,  H05K3/326 ,  H05K3/4007 ,  H05K7/1061 ,  H05K2201/0133 ,  H05K2201/0367 ,  H05K2201/09481 ,  H05K2201/09745 ,  H05K2201/10378 ,  H05K2201/10734 ,  Y10T29/49002 ,  Y10T29/49121 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49147 ,  Y10T29/49149 ,  Y10T29/49151 ,  Y10T29/49155 ,  Y10T29/49158 ,  Y10T29/49165 ,  Y10T29/49204 ,  Y10T29/49208 ,  Y10T29/49213 ,  Y10T29/49218 ,  Y10T29/49222 ,  H01L2924/00

Abstract: A module arrangement which includes a land grid array (LGA) interposer structure, including an electrically insulating carrier plane, and at least one interposer mounted on a first surface of said carrier plane. The interposer possesses a hemi-toroidal configuration in transverse cross-section and is constituted of a moldable dielectric elastomeric material. A plurality of electrically-conductive elements are arranged about the surface of the at least one hemi-toroidal interposer and extend radically inwardly and downwardly from an uppermost end thereof into electrical contact with at least one component located on an opposite side of the electrically insulating carrier plane.

Abstract translation: 一种模块装置，其包括包括电绝缘载体平面的平面栅格阵列（LGA）插入器结构以及安装在所述载体平面的第一表面上的至少一个插入器。 插入件在横截面中具有半环形结构，并且由可模制的介电弹性体材料构成。 多个导电元件围绕至少一个半环形插入件的表面布置，并且从其最上端向内和向下自由地延伸至与位于电绝缘载体的相对侧上的至少一个部件的电接触 飞机

公开(公告)号：US20100032833A1

公开(公告)日：2010-02-11

申请号：US12535775

申请日：2009-08-05

Applicant: Kiichiro Higaki ,  Koichi Sugihara ,  Katsuya Murakami ,  Shigenori Sawachi ,  Mitsuru Oida

Inventor： Kiichiro Higaki ,  Koichi Sugihara ,  Katsuya Murakami ,  Shigenori Sawachi ,  Mitsuru Oida

IPC: H01L23/498 ,  H01L21/60

CPC classification number: H05K3/4015 ,  H01L21/563 ,  H01L23/3171 ,  H01L23/49816 ,  H01L24/05 ,  H01L24/12 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/05552 ,  H01L2224/05553 ,  H01L2224/05555 ,  H01L2224/0558 ,  H01L2224/05624 ,  H01L2224/1134 ,  H01L2224/13099 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16 ,  H01L2224/73203 ,  H01L2224/81101 ,  H01L2224/81801 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/12044 ,  H01L2924/351 ,  H05K3/325 ,  H05K3/328 ,  H05K3/3457 ,  H05K2201/0367 ,  H05K2201/10734 ,  H05K2203/049 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A semiconductor device includes a semiconductor chip of a multilayer wiring structure having an insulating film formed on a surface thereof, multiple electrode pads formed at a central part and an outer peripheral part of the insulating film, and multiple protective metal layers formed respectively on the electrode pads. The semiconductor device also includes a substrate having the semiconductor chip mounted thereon and including multiple substrate terminals formed on a surface thereof respectively in positions corresponding to the electrode pads. The semiconductor chip is mounted on the substrate by connecting a stud bump to a solder bump. The stud bump is formed on any one of each of the protective metal layers and each of the substrate terminals and the solder bump is formed on the other one of each of the protective metal layers and each of the substrate terminals.

Abstract translation: 一种半导体器件包括：在其表面上形成有绝缘膜的多层布线结构的半导体芯片，形成在绝缘膜的中心部分和外周部分的多个电极焊盘，以及分别形成在电极上的多个保护金属层 垫 半导体器件还包括其上安装有半导体芯片并且分别在其表面上形成的多个基板端子的对应于电极焊盘的位置的基板。 通过将柱形凸块连接到焊料凸块来将半导体芯片安装在基板上。 在每个保护金属层中的任一个上形成螺柱凸块，并且在每个保护金属层和每个基板端子中的另一个上形成每个基板端子和焊料凸块。