公开(公告)号：US20060050488A1

公开(公告)日：2006-03-09

申请号：US11068688

申请日：2005-03-01

Applicant: Paul Goodwin

Inventor： Paul Goodwin

IPC: H05K7/06

CPC classification number: G11C5/04 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2924/00011 ,  H01L2924/00014 ,  H05K1/0203 ,  H05K1/118 ,  H05K1/181 ,  H05K1/189 ,  H05K3/0061 ,  H05K2201/056 ,  H05K2201/1056 ,  H05K2201/10734 ,  H05K2201/2018 ,  H05K2203/1572 ,  H01L2224/0401

Abstract: Multiple DIMM circuits or instantiations are presented in a single module. In some embodiments, memory integrated circuits (preferably CSPs) and accompanying AMBs, or accompanying memory registers, are arranged in two ranks in two fields on each side of a flexible circuit. The flexible circuit has expansion contacts disposed along one side. The flexible circuit is disposed about a supporting substrate or board to place one complete DIMM circuit or instantiation on each side of the constructed module. In alternative but also preferred embodiments, the ICs on the side of the flexible circuit closest to the substrate are disposed, at least partially, in what are, in a preferred embodiment, windows, pockets, or cutaway areas in the substrate. Other embodiments may only populate one side of the flexible circuit or may only remove enough substrate material to reduce but not eliminate the entire substrate contribution to overall profile. The flexible circuit may exhibit one or two or more conductive layers, and may have changes in the layered structure or have split layers. Other embodiments may stagger or offset the ICs or include greater numbers of ICs.

公开(公告)号：US20060042820A1

公开(公告)日：2006-03-02

申请号：US11206063

申请日：2005-08-18

Applicant: Gwun-Jin Lin ,  Chih-Heng Chuo ,  Kuo-Fu Su

Inventor： Gwun-Jin Lin ,  Chih-Heng Chuo ,  Kuo-Fu Su

IPC: H01B7/08

CPC classification number: H05K1/028 ,  H05K1/118 ,  H05K2201/056 ,  H05K2201/09063 ,  H05K2201/1034

Abstract: A signal transmission cable adapted to pass through a hinge assembly includes a flexible circuit substrate; a first connection section formed at a first end of the flexible circuit substrate and having a plurality of signal transmission lines provided thereon; a second connection section formed at a second end of the flexible circuit substrate and having a plurality of signal transmission lines provided thereon; and a cluster section formed on the flexible circuit substrate between the first and the second connection section, and having a plurality of signal transmission lines provided thereon to connect at two ends to the signal transmission lines on the first and the second connection section, respectively. The cluster section includes a plurality of clustered flat cables, which are formed by cutting the flexible circuit substrate along a plurality of paralleled cutting lines extended in the lengthwise direction of the flexible circuit substrate.

Abstract translation: 适于穿过铰链组件的信号传输电缆包括柔性电路基板; 第一连接部分，形成在柔性电路基板的第一端并且具有设置在其上的多个信号传输线; 第二连接部，形成在所述柔性电路基板的第二端，并且具有设置在其上的多个信号传输线; 以及在所述柔性电路基板上形成在所述第一连接部和所述第二连接部之间的集束部，并且具有设置在其上的多个信号传输线，以分别在所述第一连接部和所述第二连接部的两端连接到所述信号传输线。 集群部分包括多个聚束扁平电缆，其通过沿着柔性电路基板的长度方向上延伸的多个平行的切割线切割柔性电路基板而形成。

公开(公告)号：US20050141141A1

公开(公告)日：2005-06-30

申请号：US11012989

申请日：2004-12-14

Applicant: Tatsuo Sekimoto ,  Tomoki Hiramatsu ,  Motoji Takemoto ,  Tetsuo Yuki

Inventor： Tatsuo Sekimoto ,  Tomoki Hiramatsu ,  Motoji Takemoto ,  Tetsuo Yuki

IPC: G11B33/12 ,  G11B5/55 ,  G11B25/04 ,  G11B33/14 ,  H05K1/18

CPC classification number: G11B33/122 ,  H05K1/189 ,  H05K3/0061 ,  H05K3/0064 ,  H05K2201/056

Abstract: A flexible printed circuit board using a lead-free solder is to be fixed within a disk enclosure while ensuring a high rigidity. In one embodiment, a rotating disk storage device comprises a flexible printed circuit board (FPC), wherein there is formed a wiring pattern including a signal line for the transmission of a signal of data read by a head in an actuator head suspension assembly (AHSA) and wherein one side end portion is fixed to a base and an opposite side end portion is fixed to the AHSA. A first metallic plate and a second metallic plate are both fixed to one side end portion of the FPC. A connector is disposed in an area where the first metallic plate in the FPC is provided, and connected to the wiring pattern. A shock sensor is disposed in an area where the second metallic plate in the FPC is provided, and connected to the wiring pattern. A reinforcing plate of a synthetic resin is, in an opposed state of the first and second metallic plates fixed to one side end portion of the FPC, held between the opposed faces of both metallic plates and is fixed to the base together with both metallic plates.

Abstract translation: 使用无铅焊料的柔性印刷电路板将固定在磁盘外壳内，同时确保高刚性。 在一个实施例中，旋转盘存储装置包括柔性印刷电路板（FPC），其中形成布线图案，其包括用于传输由头部在致动器头部悬挂组件（AHSA）中读取的数据的信号的信号线 ），并且其中一个侧端部固定到基座并且相对侧端部固定到AHSA。 第一金属板和第二金属板都固定到FPC的一个侧端部。 连接器设置在设置有FPC的第一金属板的区域中，并连接到布线图案。 冲击传感器设置在设置有FPC的第二金属板的区域中，并连接到布线图案。 合成树脂的增强板在固定在FPC的一个侧端部的第一和第二金属板的相对状态下，保持在两个金属板的相对面之间并与两个金属板一起固定到基座 。

公开(公告)号：US20050018412A1

公开(公告)日：2005-01-27

申请号：US10914483

申请日：2004-08-09

Applicant: David Roper ,  James Cady ,  James Wilder ,  James Wehrly ,  Jeff Buchle ,  Julian Dowden

Inventor： David Roper ,  James Cady ,  James Wilder ,  James Wehrly ,  Jeff Buchle ,  Julian Dowden

IPC: H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L25/10 ,  H05K1/14 ,  H05K1/18 ,  H05K3/36

CPC classification number: H01L23/49816 ,  H01L23/3114 ,  H01L23/49827 ,  H01L23/4985 ,  H01L23/5387 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/16237 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06579 ,  H01L2225/06586 ,  H01L2225/107 ,  H01L2924/19041 ,  H01L2924/3011 ,  H05K1/141 ,  H05K1/147 ,  H05K1/189 ,  H05K3/363 ,  H05K2201/056 ,  H05K2201/10689 ,  H05K2201/10734

Abstract: The present invention stacks integrated circuits into modules that conserve board surface area. In a two-high stack or module devised in accordance with a preferred embodiment of the present invention, a pair of integrated circuits is stacked, with one integrated circuit above the other. The two integrated circuits are connected with a pair of flexible circuit structures. Each of the pair of flexible circuit structures is partially wrapped about a respective opposite lateral edge of the lower integrated circuit of the module. The flex circuit pair connects the upper and lower integrated circuits and provides a thermal and electrical path connection path between the module and its application environment. The module has a ballout pattern with a different pitch and/or supplemental module contacts devised to allow combined signaling to the integrated circuits through contacts having a desired ballout footprint. The present invention may be employed to advantage in numerous configurations and combinations of integrated circuits in modules provided for high-density memories or high capacity computing.

Abstract translation: 本发明将集成电路堆叠成节省电路板表面积的模块。 在根据本发明的优选实施例设计的两高堆叠或模块中，堆叠一对集成电路，一个集成电路在另一个之上。 两个集成电路与一对柔性电路结构连接。 一对柔性电路结构中的每一个部分地缠绕在模块的下部集成电路的相应的相对侧边缘上。 柔性电路对连接上下集成电路，并在模块与其应用环境之间提供热和电路连接路径。 模块具有不同间距和/或补充模块触点的布置图案，其设计为允许通过具有期望的展开占位面积的触点对集成电路的组合信令。 本发明可以有利于提供用于高密度存储器或高容量计算的模块中的集成电路的多种配置和组合。

公开(公告)号：US20040245615A1

公开(公告)日：2004-12-09

申请号：US10624097

申请日：2003-07-21

Applicant: Staktek Group, L.P.

Inventor： James W. Cady ,  Russell Rapport ,  Julian Partridge ,  James Douglas Wehrly JR. ,  James Wilder ,  David L. Roper ,  Jeff Buchle

IPC: H01L023/538

CPC classification number: H01L23/3114 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/4985 ,  H01L23/5387 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/16237 ,  H01L2224/73253 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06579 ,  H01L2225/06586 ,  H01L2225/107 ,  H01L2924/01322 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/3011 ,  H05K1/141 ,  H05K1/147 ,  H05K1/189 ,  H05K3/363 ,  H05K2201/056 ,  H05K2201/10689 ,  H05K2201/10734

Abstract: With the use of stacked modules, a system and method for point to point addressing of multiple integrated memory circuits is provided. A single memory expansion board is populated with stacked modules of integrated circuits. The single memory expansion board is located at the terminus of a transmission line, thus, effectively placing at a relative single point in the addressing system, added memory capacity that would otherwise have required multiple memory expansion boards and, consequently, a longer bus. Therefore, signal degradation issues are mitigated and the system has improved tolerance for higher signal speeds with added memory capacity. In a preferred embodiment, a four DIMM socket memory access bus that does not employ stacking is replaced with a single DIMM socket bus that supports stacking up to four high on a single DIMM. Although the present invention is preferably employed to advantage using stacked modules comprised from multiple CSPs, it may be employed with modules comprised from any number and type of integrated circuits including any type of packaging, whether CSP or leaded.

Abstract translation: 通过使用堆叠模块，提供了用于多个集成存储器电路的点对点寻址的系统和方法。 单个存储器扩展板上装有集成电路的堆叠模块。 单个存储器扩展板位于传输线的终点处，因此，有效地放置在寻址系统中的相对单个点处，增加了否则将需要多个存储器扩展板的存储器容量，并且因此需要更长的总线。 因此，信号降级问题得到缓解，并且具有增加的存储容量的系统已经改善了对更高信号速度的容限。 在优选实施例中，不使用堆叠的四个DIMM插槽存储器存取总线被单个DIMM插槽总线替代，该DIMM插槽总线在单个DIMM上支持堆叠高达四个高。 虽然本发明优选地使用由多个CSP组成的堆叠模块，但是可以使用包括任何数量和类型的集成电路的模块，包括任何类型的封装，无论是CSP还是带引线。

公开(公告)号：US06756663B2

公开(公告)日：2004-06-29

申请号：US10337879

申请日：2003-01-08

Applicant: Tsukasa Shiraishi ,  Tsutomu Mitani ,  Kazuyoshi Amami ,  Yoshihiro Bessho

Inventor： Tsukasa Shiraishi ,  Tsutomu Mitani ,  Kazuyoshi Amami ,  Yoshihiro Bessho

IPC: H05K346

CPC classification number: H01L21/563 ,  H01L23/5385 ,  H01L24/45 ,  H01L24/48 ,  H01L25/0652 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15192 ,  H01L2924/19041 ,  H01L2924/19106 ,  H01L2924/19107 ,  H05K1/0284 ,  H05K1/141 ,  H05K1/147 ,  H05K1/189 ,  H05K3/328 ,  H05K3/3421 ,  H05K3/3442 ,  H05K3/363 ,  H05K3/368 ,  H05K2201/056 ,  H05K2201/10386 ,  H05K2201/10674 ,  H05K2203/049 ,  H05K2203/1572 ,  H01L2924/00 ,  H01L2224/05599

Abstract: A semiconductor device is made by mounting semiconductor elements on both sides of a wiring board having three-dimensional wiring including inner-via holes. A high operating speed and smaller size are made possible by employing a laminated structure of semiconductor elements without using the chip-on-chip configuration. Semiconductor elements are mounted on both sides of a wiring board having three-dimensional wiring including inner via holes so that the semiconductor elements oppose each other via the wiring board. The electrodes of the semiconductor elements are connected with each other by the three-dimensional wiring of the wiring board.

Abstract translation: 半导体器件通过将半导体元件安装在具有包括内通孔的三维布线的布线板的两侧上而制成。 通过采用半导体元件的叠层结构而不使用片上芯片配置，可以实现高工作速度和较小尺寸。 半导体元件安装在具有包括内部通孔的三维布线的布线板的两侧，使得半导体元件经由布线板彼此相对。 半导体元件的电极通过布线板的三维布线彼此连接。

公开(公告)号：US20030143766A1

公开(公告)日：2003-07-31

申请号：US10408111

申请日：2003-04-08

Applicant: NEC CORPORATION

Inventor： Takashi Ishikawa ,  Yuji Kondo ,  Akihiro Yano

IPC: H01L021/00

CPC classification number: H05B33/04 ,  G09F9/30 ,  H01L27/3241 ,  H05K1/189 ,  H05K2201/053 ,  H05K2201/056 ,  H05K2201/10106 ,  H05K2201/10128 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49169

Abstract: A flat panel display module includes a transparent substrate, a light emitting section, a sealing cap, a flexible printed circuit board and a semiconductor device. The transparent substrate with a wiring line terminal section is formed on one of surfaces of the transparent substrate in at least one of opposing ends of the transparent substrate. The light emitting section is provided in a display region in a center section on the surface on which the wiring line terminal section of the transparent substrate is formed. The sealing cap is provided for a sealing region to cover the light emitting section such that ends of the sealing cap does not reach the ends of the transparent substrate or the wiring line terminal section of the transparent substrate. The flexible printed circuit board is connected to the wiring line terminal section and extending along the sealing cap of the transparent substrate. The semiconductor device is mounted on the flexible printed circuit board for the light emitting section.

公开(公告)号：US06525414B2

公开(公告)日：2003-02-25

申请号：US09725283

申请日：2000-11-29

Applicant: Tsukasa Shiraishi ,  Tsutomu Mitani ,  Kazuyoshi Amami ,  Yoshihiro Bessho

Inventor： Tsukasa Shiraishi ,  Tsutomu Mitani ,  Kazuyoshi Amami ,  Yoshihiro Bessho

IPC: H05K346

CPC classification number: H01L21/563 ,  H01L23/5385 ,  H01L24/45 ,  H01L24/48 ,  H01L25/0652 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15192 ,  H01L2924/19041 ,  H01L2924/19106 ,  H01L2924/19107 ,  H05K1/0284 ,  H05K1/141 ,  H05K1/147 ,  H05K1/189 ,  H05K3/328 ,  H05K3/3421 ,  H05K3/3442 ,  H05K3/363 ,  H05K3/368 ,  H05K2201/056 ,  H05K2201/10386 ,  H05K2201/10674 ,  H05K2203/049 ,  H05K2203/1572 ,  H01L2924/00 ,  H01L2224/05599

Abstract: A semiconductor device is made by mounting semiconductor elements on both sides of a wiring board having three-dimensional wiring including inner-via holes. A high operating speed and smaller size are made possible by employing a laminated structure of semiconductor elements without using the chip-on-chip configuration. Semiconductor elements are mounted on both sides of a wiring board having three-dimensional wiring including inner via holes so that the semiconductor elements oppose each other via the wiring board. The electrodes of the semiconductor elements are connected with each other by the three-dimensional wiring of the wiring board.

Abstract translation: 半导体器件通过将半导体元件安装在具有包括内通孔的三维布线的布线板的两侧上而制成。 通过采用半导体元件的叠层结构而不使用片上芯片配置，可以实现高工作速度和较小尺寸。 半导体元件安装在具有包括内部通孔的三维布线的布线板的两侧，使得半导体元件经由布线板彼此相对。 半导体元件的电极通过布线板的三维布线彼此连接。

公开(公告)号：US06452811B1

公开(公告)日：2002-09-17

申请号：US09654073

申请日：2000-09-01

Applicant: James L. Tracy ,  James A. Zollo

Inventor： James L. Tracy ,  James A. Zollo

IPC: H05K900

CPC classification number: H05K1/141 ,  H05K1/147 ,  H05K1/189 ,  H05K3/363 ,  H05K2201/056 ,  H05K2201/10371

Abstract: Methods and apparatus for adding additional circuitry (19) to a circuit board (11) having a radiation shield (14) associated therewith include the additional circuitry (19) mounted onto a flex circuit (21) which in turn is mounted on the radiation shield (14). A conductor (32) containing portion (24) of the flex circuit (21) extends therefrom and is routed around and through a cutout (18) in the bottom surface of the radiation shield (14). The conductor (32) is connected to the printed circuit board (11) at the location of the cutout (18) in the radiation shield (14).

Abstract translation: 将附加电路（19）添加到具有与其相关联的辐射屏蔽（14）的电路板（11）的方法和装置包括安装在柔性电路（21）上的附加电路（19），柔性电路（21）又安装在辐射屏蔽 （14）。 柔性电路（21）的容纳部分（24）的导体（32）从其延伸并绕过并穿过辐射屏蔽（14）的底表面中的切口（18）。 导体（32）在辐射屏蔽（14）中的切口（18）的位置处连接到印刷电路板（11）。

公开(公告)号：US20020051349A1

公开(公告)日：2002-05-02

申请号：US09984189

申请日：2001-10-29

Applicant: YAZAKI CORPORATION

Inventor： Yasuyoshi Serizawa ,  Takahiko Suzuki ,  Minoru Kubota ,  Kenji Iwasaki

IPC: H05K005/00 ,  H05K005/04 ,  H05K005/06

CPC classification number: H05K1/028 ,  H01R13/582 ,  H05K5/0247 ,  H05K2201/056 ,  H05K2201/10598 ,  H05K2201/2027

Abstract: A first casing (11, 12)includes a first end (30, 31). A second casing (11, 12) is mated with the first casing (11, 12). The second casing (11, 12) includes a second end (30, 31) facing the first end (30, 31). A flexible circuit member (23) is housed between the first and second casings (11, 12). The circuit member (23) is drawn out from the first and second ends (30, 31). The circuit member (23) is retained between the first and second ends (30, 31) under pressure.

Abstract translation: 第一壳体（11,12）包括第一端（30,31）。 第二壳体（11,12）与第一壳体（11,12）配合。 第二壳体（11,12）包括面向第一端部（30,31）的第二端部（30,31）。 柔性电路构件（23）容纳在第一和第二壳体（11,12）之间。 电路构件（23）从第一端和第二端（30,31）拉出。 电路构件（23）在压力下保持在第一端和第二端（30,31）之间。