公开(公告)号：US20100000777A1

公开(公告)日：2010-01-07

申请号：US12198343

申请日：2008-08-26

Applicant: HUI-CHEN ZHAO ,  QING-LIN ZHOU

Inventor： HUI-CHEN ZHAO ,  QING-LIN ZHOU

IPC: H05K1/11

CPC classification number: H05K1/0245 ,  H05K1/0219 ,  H05K1/0222 ,  H05K1/115 ,  H05K2201/09227 ,  H05K2201/09236 ,  H05K2201/09636

Abstract: A printed circuit board includes a first signal via, a second signal via, and a first ground via. A distance between the first ground via and the first signal via is substantially equal to a distance between the first ground via and the second signal via.

Abstract translation: 印刷电路板包括第一信号通孔，第二信号通孔和第一接地通孔。 第一接地通孔和第一信号通孔之间的距离基本上等于第一接地通孔和第二信号通孔之间的距离。

公开(公告)号：US20090316300A1

公开(公告)日：2009-12-24

申请号：US12485091

申请日：2009-06-16

Applicant: Katsutoshi KAMEI ,  Voonyee HO

Inventor： Katsutoshi KAMEI ,  Voonyee HO

IPC: G11B5/127 ,  H05K1/00 ,  H05K3/10

CPC classification number: H05K1/0237 ,  G11B5/484 ,  H05K1/0263 ,  H05K1/0265 ,  H05K1/056 ,  H05K2201/0191 ,  H05K2201/09236 ,  H05K2201/09736 ,  H05K2201/09845 ,  H05K2201/09972 ,  Y10T29/49155

Abstract: A first insulating layer is formed on a suspension body. Wiring traces are formed in parallel at an interval on the first insulating layer. A second insulating layer is formed in a region on the first insulating layer on both sides of the wiring traces. A wiring trace is formed in a region on the second insulating layer on the side of the wiring trace. A wiring trace is formed in a region on the second insulating layer on the side of the wiring trace. A third insulating layer is formed on the first and second insulating layers to cover the wiring traces.

Abstract translation: 在悬架体上形成第一绝缘层。 在第一绝缘层上以一定间隔平行地形成接线迹线。 第二绝缘层形成在布线迹线两侧的第一绝缘层上的区域中。 在布线迹线侧的第二绝缘层的区域中形成布线。 在布线迹线侧的第二绝缘层的区域中形成布线。 在第一和第二绝缘层上形成第三绝缘层以覆盖布线迹线。

公开(公告)号：US07626825B2

公开(公告)日：2009-12-01

申请号：US12003225

申请日：2007-12-20

Applicant: Hisashi Takamatsu ,  Takeshi Yamashita ,  Hideyuki Kuwano ,  Osamu Kagaya ,  Hiroyuki Arima

Inventor： Hisashi Takamatsu ,  Takeshi Yamashita ,  Hideyuki Kuwano ,  Osamu Kagaya ,  Hiroyuki Arima

IPC: H05K1/00

CPC classification number: G02B6/4201 ,  G02B6/4271 ,  G02B6/4277 ,  G02B6/4279 ,  G02B6/4281 ,  G02B6/4283 ,  H05K1/0219 ,  H05K1/0224 ,  H05K1/0253 ,  H05K1/0393 ,  H05K2201/0715 ,  H05K2201/09236 ,  H05K2201/09663 ,  H05K2201/10121 ,  H05K2201/10446

Abstract: An optical transmitter module is described. The optical transmitter module includes a lead pin for electrically connecting the inside and outside of a housing, and a flexible printed circuit board connected to the lead pin. The flexible printed circuit board has a signal pattern and two ground conductor patterns to be connected to an optical modulation element, a laser terminal pattern to be connected to a semiconductor laser, a Peltier terminal pattern to be connected to a Peltier element, and two covering conductive layers in addition to a layer on which such patterns are formed. The covering conductive layers cover all the patterns except for the signal pattern.

Abstract translation: 描述了光发射机模块。 光发射机模块包括用于电连接壳体的内部和外部的引脚和连接到引脚的柔性印刷电路板。 柔性印刷电路板具有要连接到光调制元件的信号图案和两个接地导体图案，要连接到半导体激光器的激光端子图案，要连接到珀耳帖元件的珀耳帖端子图案，以及两个覆盖 除了形成这种图案的层之外的导电层。 覆盖导电层覆盖除了信号图案之外的所有图案。

公开(公告)号：US20090277665A1

公开(公告)日：2009-11-12

申请号：US12429223

申请日：2009-04-24

Applicant: Tadashi Kumamoto ,  Hideo Miyazawa ,  Takeshi Okuyama

Inventor： Tadashi Kumamoto ,  Hideo Miyazawa ,  Takeshi Okuyama

IPC: H01B11/02 ,  H01R25/00

CPC classification number: H01R9/035 ,  H01R13/6471 ,  H01R13/6473 ,  H01R13/6589 ,  H05K1/0219 ,  H05K1/0245 ,  H05K1/117 ,  H05K2201/09236 ,  H05K2201/10189

Abstract: A connector for balanced transmission includes a block member having input and output contact pairs formed on front and back surfaces thereof, and a relay wiring substrate having front and back surfaces with a ground layer in between, on which surfaces input contact connecting pads, output contact connecting pads, input wiring patterns, and output wiring patterns are formed. Each input contact pair includes a pair of contact parts formed on the front or back surface of the block member and a pair of lead parts connected to the input contact connecting pads formed on the front or back surface of the relay wiring substrate. Each output contact pair includes a pair of contact parts formed on the front or back surface of the block member and a pair of lead parts connected to the output contact connecting pads formed on the front or back surface of the relay wiring substrate.

Abstract translation: 用于平衡传输的连接器包括：块构件，其具有形成在其前表面和后表面上的输入和输出触点对;以及中继布线基板，具有前后表面，其间具有接地层，输入触点连接焊盘，输出触点 形成连接焊盘，输入布线图案和输出布线图案。 每个输入触点对包括一对形成在块体前表面或后表面上的接触部分，以及一对连接到形成在中继布线基板的前表面或后表面上的输入接触连接焊盘的引线部分。 每个输出触点对都包括一对形成在块体前表面或后表面上的接触部分，以及一对连接到形成在中继布线基板的前表面或后表面上的输出接触连接焊盘的引线部分。

公开(公告)号：US07615709B2

公开(公告)日：2009-11-10

申请号：US11978810

申请日：2007-10-30

Applicant: Joel R. Goergen

Inventor： Joel R. Goergen

IPC: H01R12/04 ,  H05K1/11

CPC classification number: H05K3/4688 ,  H05K1/0218 ,  H05K1/024 ,  H05K1/0243 ,  H05K1/0271 ,  H05K1/116 ,  H05K3/382 ,  H05K3/429 ,  H05K3/4626 ,  H05K3/4641 ,  H05K2201/0209 ,  H05K2201/044 ,  H05K2201/0723 ,  H05K2201/09236 ,  H05K2201/093 ,  H05K2201/09309 ,  H05K2201/09318 ,  H05K2201/09327 ,  H05K2201/09354 ,  H05K2201/09381 ,  H05K2201/09454 ,  H05K2201/09636 ,  H05K2201/09663 ,  H05K2201/09718 ,  H05K2201/09781 ,  H05K2203/061 ,  Y10T29/49117 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49162 ,  Y10T29/49163 ,  Y10T29/49165

Abstract: A circuit board comprises signaling through-holes that pass through a plurality of layers, including signal trace and digital ground plane layers, and power reference plane layers. Clearances are set to achieve a desired impedance characteristic for the through-holes. At a power reference plane layer, the clearance is defined around multiple neighboring through-holes.

Abstract translation: 电路板包括通过多个层的信令通孔，包括信号迹线和数字接地层以及功率参考平面层。 设定间隙以实现通孔所需的阻抗特性。 在功率参考平面层上，间隙围绕多个相邻的通孔限定。

公开(公告)号：US20090269978A1

公开(公告)日：2009-10-29

申请号：US12109544

申请日：2008-04-25

Applicant: Paul John Pepe ,  Shawn Phillip Tobey ,  Sheldon Easton Muir ,  Steven Richard Bopp

Inventor： Paul John Pepe ,  Shawn Phillip Tobey ,  Sheldon Easton Muir ,  Steven Richard Bopp

IPC: H01R13/66 ,  H01R24/00

CPC classification number: H01R13/6466 ,  H01R13/6469 ,  H01R13/6658 ,  H01R13/719 ,  H05K1/0228 ,  H05K1/0237 ,  H05K1/0239 ,  H05K1/162 ,  H05K2201/09236 ,  H05K2201/09672 ,  H05K2201/10189 ,  Y10S439/941

Abstract: An electrical connector includes a housing and a plurality of contacts within the housing that are configured to engage with mating contacts of a mating connector. The contacts form at least a first differential pair and a second differential pair. The electrical connector also includes a circuit board housed within the housing. The circuit board has a substrate body formed from a dielectric material and includes a first trace electrically coupled to a contact of the first differential pair and a second trace electrically coupled to a contact of the second differential pair. At least one of the first and second traces is an open-ended trace. The circuit board also has a non-ohmic plate that is positioned adjacent to the traces. The plate is positioned to electromagnetically couple the first and second traces to each other and the non-ohmic plate and traces are configured for a desired electrical performance.

Abstract translation: 电连接器包括壳体和壳体内的多个触点，其构造成与配合连接器的配合触点接合。 触点形成至少第一差分对和第二差分对。 电连接器还包括容纳在壳体内的电路板。 电路板具有由电介质材料形成的衬底主体，并且包括电耦合到第一差分对的触点的第一迹线和电耦合到第二差分对的触点的第二迹线。 第一和第二迹线中的至少一个是开放式迹线。 电路板还具有邻近迹线定位的非欧姆板。 板被定位成将第一和第二迹线电磁耦合到彼此，并且非欧姆板和迹线被配置为期望的电性能。

公开(公告)号：US07609526B2

公开(公告)日：2009-10-27

申请号：US11230336

申请日：2005-09-20

Applicant: Shunsuke Eiki

Inventor： Shunsuke Eiki

IPC: H05K7/00

CPC classification number: H01G4/012 ,  H05K1/162 ,  H05K2201/09236 ,  H05K2201/09881

Abstract: A circuit board including a capacitor structure formed on a surface of an insulating substrate, wherein the capacitor structure includes paired linear conductive layers arranged on the surface of the insulating substrate, parallel to each other with a predetermined distance between them, and a dielectric material filled in a groove defined by those surfaces of the paired linear conductive layers which face each other and the surface of the insulating substrate.

Abstract translation: 一种电路板，包括形成在绝缘基板的表面上的电容器结构，其中所述电容器结构包括布置在所述绝缘基板的表面上的成对的线性导电层，彼此之间以预定距离彼此平行，并且填充介电材料 在由彼此面对的成对线性导电层的那些表面和绝缘基板的表面限定的凹槽中。

公开(公告)号：US07609501B2

公开(公告)日：2009-10-27

申请号：US12017020

申请日：2008-01-19

Applicant: Anthony A. Anthony ,  William M. Anthony

Inventor： Anthony A. Anthony ,  William M. Anthony

IPC: H02H9/00

CPC classification number: H01L23/49822 ,  H01L23/49838 ,  H01L23/50 ,  H01L23/552 ,  H01L23/66 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16265 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01087 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/023 ,  H05K1/0237 ,  H05K2201/09236 ,  H05K2201/10378 ,  Y10T29/49124 ,  Y10T29/4913 ,  Y10T29/49204 ,  H01L2924/00 ,  H01L2224/05599

Abstract: The present invention relates to an interposer substrate for interconnecting between active electronic componentry such as but not limited to a single or multiple integrated circuit chips in either a single or a combination and elements that could comprise of a mounting substrate, substrate module, a printed circuit board, integrated circuit chips or other substrates containing conductive energy pathways that service an energy utilizing load and leading to and from an energy source. The interposer will also possess a multi-layer, universal multi-functional, common conductive shield structure with conductive pathways for energy and EMI conditioning and protection that also comprise a commonly shared and centrally positioned conductive pathway or electrode of the structure that can simultaneously shield and allow smooth energy interaction between grouped and energized conductive pathway electrodes containing a circuit architecture for energy conditioning as it relates to integrated circuit device packaging. The invention can be employed between an active electronic component and a multilayer circuit card. A method for making the interposer is not presented and can be varied to the individual or proprietary construction methodologies that exist or will be developed.

Abstract translation: 本发明涉及用于将有源电子元件（例如但不限于单个或多个）单个或多个集成电路芯片互连的插入器基板，以及可以包括安装基板，基板模块，印刷电路 板，集成电路芯片或其他包含导电能量路径的基板，其能够利用负载并通向能量源的能量。 插入器还将具有多层通用多功能通用导电屏蔽结构，其具有用于能量和EMI调节和保护的导电路径，其还包括可共同屏蔽的结构的共同共享和中心定位的导电路径或电极， 允许包含用于能量调节的电路架构的组合和通电的导电路径电极之间的平滑的能量相互作用，因为它涉及集成电路器件封装。 本发明可以用于有源电子部件和多层电路卡之间。 不提供制作插入器的方法，并且可以根据现有或将要开发的个人或专有的施工方法来改变。

公开(公告)号：US07609125B2

公开(公告)日：2009-10-27

申请号：US11580444

申请日：2006-10-13

Applicant: Minh van Quach ,  Nurwati S. Devnani ,  Robert B. Manley

Inventor： Minh van Quach ,  Nurwati S. Devnani ,  Robert B. Manley

IPC: H01P3/08

CPC classification number: H05K1/0219 ,  H01L23/66 ,  H01L2223/6627 ,  H01L2223/6638 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/19032 ,  H01L2924/19051 ,  H01L2924/3011 ,  H05K1/0237 ,  H05K2201/0715 ,  H05K2201/09236 ,  H01L2924/00

Abstract: Systems, devices and methods are disclosed herein for reducing crosstalk between pairs of differential signal conductors. One or more ground traces connected to one or more over- or under-lying ground planes by vias are located between pairs of differential signal conductors. The electrical shielding provided by the combination of the one or more ground traces and the one or more ground planes results in reduced cross-talk between different pairs of differential signal conductors, and facilitates high-speed data rates between integrated circuits and printed circuit boards. In a preferred embodiment, such ground traces and ground planes are employed in HiTCE packaging containing multiple pairs of differential signal conductors.

Abstract translation: 本文公开了用于减少差分信号导体对之间的串扰的系统，装置和方法。 通过通孔连接到一个或多个过或不足的接地层的一个或多个接地迹线位于差分信号导体对之间。 由一个或多个接地迹线和一个或多个接地平面的组合提供的电屏蔽导致不同差分信号导体对之间的串扰减少，并且有助于集成电路和印刷电路板之间的高速数据速率。 在优选实施例中，在包含多对差分信号导体的HiTCE封装中使用这种接地迹线和接地层。

公开(公告)号：US20090258541A1

公开(公告)日：2009-10-15

申请号：US12369532

申请日：2009-02-11

Applicant: Bernard Harold Hammond, JR. ,  David Patrick Murray

Inventor： Bernard Harold Hammond, JR. ,  David Patrick Murray

IPC: H01R13/66

CPC classification number: H01R13/6466 ,  H01R24/64 ,  H05K1/0228 ,  H05K1/162 ,  H05K2201/09236 ,  H05K2201/09672 ,  H05K2201/10189 ,  Y10S439/941

Abstract: Methods and systems for compensating for alien crosstalk generated by one or more of a plurality of wire pairs in a telecommunications jack are disclosed. One method includes positioning a crosstalk compensation arrangement relating to crosstalk across at least a first wire pair and a second wire pair on a circuit board within a telecommunications jack. The method also includes altering the crosstalk compensation arrangement to accommodate at least one zone of crosstalk compensation having an asymmetric capacitive coupling between a first wire pair and a second wire pair to reduce alien crosstalk generated from one of the first and second wire pairs. Specific jacks and compensation arrangements are disclosed as well.

Abstract translation: 公开了用于补偿由电信插座中的多个线对中的一个或多个产生的外来串扰的方法和系统。 一种方法包括将跨串扰的串扰补偿装置定位在电信插孔内的电路板上的至少第一线对和第二线对上。 该方法还包括改变串扰补偿装置以适应至少一个串扰补偿区域，其具有第一线对和第二线对之间的非对称电容耦合，以减少从第一和第二线对之一产生的外来串扰。 具体的插孔和补偿安排也被公开。