公开(公告)号：US20170261799A1

公开(公告)日：2017-09-14

申请号：US15604877

申请日：2017-05-25

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： CHONG-GUK LEE ,  JOO-YEON WON ,  SE-HUI JANG ,  SU-Ml MOON ,  DONG-WOOK LEE

IPC: G02F1/1345 ,  H01L23/498 ,  H01L27/12 ,  H05K1/02 ,  H01L23/00 ,  H05K1/18

CPC classification number: G02F1/13452 ,  H01L23/4985 ,  H01L24/16 ,  H01L24/48 ,  H01L27/124 ,  H01L2224/16227 ,  H01L2224/48227 ,  H01L2224/81191 ,  H01L2924/00014 ,  H01L2924/15159 ,  H05K1/028 ,  H05K1/189 ,  H05K2201/09227 ,  H05K2201/09272 ,  H05K2201/09281 ,  H05K2201/10674 ,  H01L2224/45099

Abstract: A chip on film package includes a base substrate, an input line, an integrated circuit (IC) chip and an output line. The input line is disposed on the base substrate. The IC chip is electrically connected to the input line. The output line includes a main output and a sub output line. The main output line is electrically connected to the IC chip and extends in a first direction from the IC chip. The sub output line is electrically connected to the IC chip. The sub output line includes at least six bending parts, and is extended in the first direction.

公开(公告)号：US09664964B2

公开(公告)日：2017-05-30

申请号：US14678406

申请日：2015-04-03

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Chong-Guk Lee ,  Joo-Yeon Won ,  Se-Hui Jang ,  Su-Mi Moon ,  Dong-Wook Lee

IPC: H01L23/48 ,  G02F1/1345 ,  H01L27/12 ,  H01L23/498 ,  H05K1/02 ,  H01L23/00 ,  H05K1/18

CPC classification number: G02F1/13452 ,  H01L23/4985 ,  H01L24/16 ,  H01L24/48 ,  H01L27/124 ,  H01L2224/16227 ,  H01L2224/48227 ,  H01L2224/81191 ,  H01L2924/00014 ,  H01L2924/15159 ,  H05K1/028 ,  H05K1/189 ,  H05K2201/09227 ,  H05K2201/09272 ,  H05K2201/09281 ,  H05K2201/10674 ,  H01L2224/45099

Abstract: A chip on film package includes a base substrate, an input line, an integrated circuit (IC) chip and an output line. The input line is disposed on the base substrate. The IC Chip is electrically connected to the input line. The output line includes a main output and a sub output line. The main output line is electrically connected to the IC chip and extends in a first direction from the IC chip. The sub output line is electrically connected to the IC chip. The sub output line includes at least six bending parts, and is extended in the first direction.

公开(公告)号：US09575607B2

公开(公告)日：2017-02-21

申请号：US14622357

申请日：2015-02-13

Applicant: MStar Semiconductor, Inc.

Inventor： Guo-Kiang Hung ,  Chien-Chuan Chen ,  Chao-Yang Kuo

IPC: G06F3/044 ,  H05K1/11 ,  H05K1/16

CPC classification number: G06F3/044 ,  H05K1/11 ,  H05K1/167 ,  H05K2201/09263 ,  H05K2201/09272 ,  H05K2201/09281 ,  H05K2201/09381 ,  H05K2201/09418 ,  H05K2201/097 ,  H05K2201/10053

Abstract: An electrode of a self-capacitive touch panel is provided. The electrode, coupled to a control circuit of the self-capacitive touch panel via a conducting wire, includes: a serpentine portion, having a first side; a main portion, having a second side; and a connecting portion, connected to the first side and the second side to connect the serpentine portion and the main portion. A length of the connecting portion is smaller than a length of the first side and a length of the second side.

Abstract translation: 提供了一种自电容式触摸面板的电极。 经由导线与电容式触摸屏的控制电路相连的电极包括：具有第一侧的蛇形部分; 主要部分，具有第二面; 以及连接部分，连接到第一侧和第二侧以连接蛇形部分和主要部分。 连接部分的长度小于第一侧的长度和第二侧的长度。

公开(公告)号：US09480151B2

公开(公告)日：2016-10-25

申请号：US13574789

申请日：2011-01-31

Applicant: Margaretha Maria De Kok ,  Jeroen Van Den Brand ,  Gerardus Titus Van Heck

Inventor： Margaretha Maria De Kok ,  Jeroen Van Den Brand ,  Gerardus Titus Van Heck

IPC: H05K1/00 ,  H05K1/02 ,  H01L27/32 ,  H01L51/52 ,  H01R4/70 ,  H05K3/36 ,  H05B33/08 ,  H05B33/10 ,  H05K13/04 ,  H01L31/0392 ,  H01L31/042 ,  G09F9/00 ,  G09F19/22 ,  H01R4/04 ,  H01R12/70 ,  H05K1/03 ,  H05K1/14 ,  H05K1/18 ,  H05K3/32

CPC classification number: H05K1/0277 ,  G09F9/00 ,  G09F19/22 ,  H01L27/3293 ,  H01L31/0392 ,  H01L31/042 ,  H01L51/5203 ,  H01L2251/5338 ,  H01L2251/5361 ,  H01R4/04 ,  H01R4/70 ,  H01R12/7076 ,  H05B33/0896 ,  H05B33/10 ,  H05K1/0283 ,  H05K1/038 ,  H05K1/147 ,  H05K1/189 ,  H05K3/321 ,  H05K3/325 ,  H05K3/365 ,  H05K13/04 ,  H05K2201/029 ,  H05K2201/0311 ,  H05K2201/046 ,  H05K2201/083 ,  H05K2201/09081 ,  H05K2201/09281 ,  H05K2201/10106 ,  H05K2201/10287 ,  H05K2201/10484 ,  Y02E10/50 ,  Y10T29/4913

Abstract: An assembly of a plurality of tiles (1) with a carrier (40), wherein the tiles (1) comprise a foil (20) with an electro-physical transducer (10) and electrical connectors (24, 28) to said transducer. The tiles are mechanically and electrically coupled to the carrier, and the tiles overlay according to a fish scale pattern.

Abstract translation: 具有载体（40）的多个瓦片（1）的组件，其中瓦片（1）包括具有电 - 物理换能器（10）的箔（20）和到所述换能器的电连接器（24,28）。 瓦片机械地和电耦合到载体上，并且瓦片根据鱼鳞图案覆盖。

公开(公告)号：US20160294346A1

公开(公告)日：2016-10-06

申请号：US15088147

申请日：2016-04-01

Applicant: FOXCONN INTERCONNECT TECHNOLOGY LIMITED

Inventor： YONG-CHUN XU ,  JIAN-SHE HU ,  CHAO-TUNG HUANG ,  CHIH-CHING HSU

IPC: H03H7/01 ,  H05K1/11 ,  H01F27/28 ,  H05K1/18 ,  H03H7/09 ,  H01F27/24

CPC classification number: H03H7/09 ,  H01F27/24 ,  H01F27/28 ,  H01F27/29 ,  H01F27/292 ,  H01F30/02 ,  H05K1/0231 ,  H05K1/0233 ,  H05K1/0245 ,  H05K1/111 ,  H05K2201/09272 ,  H05K2201/09281 ,  H05K2201/10015 ,  H05K2201/1003

Abstract: A printed circuit board assembly includes a printed circuit board, a number of electronic components mounted thereon, and a number of conductive traces electrically connecting the components to form a number of transmission channels. Each of the channels has first and second transmission routes for transmitting differential signals. Each channel includes a common mode choke, a pair of capacitors, and an autotransformer. The common mode choke includes a first coil series connection with the first transmission route and a second coil series connection with the second transmission route. The capacitors include a first capacitor series connection with the first transmitting route and a second capacitor series connection with the second transmitting route.

Abstract translation: 印刷电路板组件包括印刷电路板，安装在其上的许多电子部件以及电连接部件以形成多个传输通道的多个导电迹线。 每个信道具有用于发送差分信号的第一和第二传输路由。 每个通道包括一个共模扼流圈，一对电容器和一个自耦变压器。 共模扼流圈包括与第一传输路径的第一线圈串联连接和与第二传输路由的第二线圈串联连接。 电容器包括与第一发送路径的第一电容器串联连接和与第二发送路径的第二电容器串联连接。

公开(公告)号：US20160062172A1

公开(公告)日：2016-03-03

申请号：US14678406

申请日：2015-04-03

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Chong-Guk Lee ,  Joo-Yeon Won ,  Se-Hui Jang ,  Su-Mi Moon ,  Dong-Wook Lee

IPC: G02F1/1345 ,  H01L23/00 ,  H01L27/12

CPC classification number: G02F1/13452 ,  H01L23/4985 ,  H01L24/16 ,  H01L24/48 ,  H01L27/124 ,  H01L2224/16227 ,  H01L2224/48227 ,  H01L2224/81191 ,  H01L2924/00014 ,  H01L2924/15159 ,  H05K1/028 ,  H05K1/189 ,  H05K2201/09227 ,  H05K2201/09272 ,  H05K2201/09281 ,  H05K2201/10674 ,  H01L2224/45099

Abstract: A chip on film package includes a base substrate, an input line, an integrated circuit (IC) chip and an output line. The input line is disposed on the base substrate, The IC Chip is electrically connected to the input line. The output line includes a main output and a sub output line, The main output line is electrically connected to the IC chip and extends in a first direction from the IC chip. The sub output line is electrically connected to the IC chip. The sub output line includes at least six bending parts, and is extended in the first direction.

Abstract translation: 薄膜封装芯片包括基底基板，输入线，集成电路（IC）芯片和输出线。 输入线设置在基底基板上.IC芯片电连接到输入线。 输出线包括主输出和副输出线。主输出线与IC芯片电连接，并从IC芯片沿第一方向延伸。 副输出线电连接到IC芯片。 子输出线包括至少六个弯曲部分，并且沿第一方向延伸。

公开(公告)号：US09277642B2

公开(公告)日：2016-03-01

申请号：US14012216

申请日：2013-08-28

Applicant: Eastman Kodak Company

Inventor： Ronald Steven Cok

IPC: H05K1/02 ,  H05K3/46 ,  H05K3/12 ,  H05K3/00 ,  H05K1/09

CPC classification number: H05K1/0274 ,  H05K1/0298 ,  H05K1/097 ,  H05K3/0041 ,  H05K3/12 ,  H05K3/1258 ,  H05K3/1275 ,  H05K3/1283 ,  H05K3/1291 ,  H05K3/465 ,  H05K3/4685 ,  H05K2201/09209 ,  H05K2201/09281 ,  H05K2201/0979 ,  H05K2201/09845 ,  H05K2203/0108

Abstract: A method of making an imprinted micro-wire structure includes providing a substrate having an edge area and a central area separate from the edge area and providing first, second, and third different stamps. A curable bottom, connecting layer, and top layer are formed on the substrate. A bottom-layer micro-channel is imprinted in the bottom layer in the central area and the edge area, a connecting-layer micro-channel is imprinted in the connecting layer in the edge area over the bottom-layer micro-channel, an edge micro-channel is imprinted in the top layer in the edge area over the connecting-layer micro-channel, and top-layer micro-channels are imprinted in the top layer over the central area. Micro-wires are formed in each micro-channel. The bottom-layer micro-wire in the central area is electrically connected to the edge micro-wire in the edge area and is electrically isolated from the top-layer micro-wire.

Abstract translation: 制造压印微线结构的方法包括提供具有与边缘区域分离的边缘区域和中心区域的基板，并提供第一，第二和第三不同的邮票。 在基板上形成可固化的底部，连接层和顶层。 底层微通道印在中心区域和边缘区域的底层中，连接层微通道被压印在底层微通道上的边缘区域中的连接层中，边缘 微通道印在连接层微通道上的边缘区域的顶层中，顶层微通道印在中心区域的顶层中。 微线形成在每个微通道中。 中心区域的底层微线电连接到边缘区域中的边缘微线，并与顶层微线电隔离。

公开(公告)号：US09215798B2

公开(公告)日：2015-12-15

申请号：US14012173

申请日：2013-08-28

Applicant: Ronald Steven Cok

Inventor： Ronald Steven Cok

IPC: H01B13/00 ,  H05K1/02 ,  H05K3/46 ,  H05K3/12 ,  H05K3/00 ,  H05K1/09

CPC classification number: H05K1/0274 ,  H05K1/0298 ,  H05K1/097 ,  H05K3/0041 ,  H05K3/12 ,  H05K3/1258 ,  H05K3/1275 ,  H05K3/1283 ,  H05K3/1291 ,  H05K3/465 ,  H05K3/4685 ,  H05K2201/09209 ,  H05K2201/09281 ,  H05K2201/0979 ,  H05K2201/09845 ,  H05K2203/0108

Abstract: A method of making an imprinted micro-wire structure includes providing a substrate, a first stamp, and a different multi-level second stamp. A curable bottom layer is provided over the substrate. One or more bottom-layer micro-channel(s) are imprinted in the curable bottom layer with the first stamp and a bottom-layer micro-wire formed in each bottom-layer micro-channel. A curable multi-layer is formed adjacent to and in contact with the cured bottom layer. First and second multi-layer micro-channels and a top-layer micro-channel are imprinted in the curable multi-layer with the multi-level second stamp. Either two bottom-layer micro-wires are electrically connected through the first and second multi-layer micro-wires and a top-layer micro-wire or two top-layer micro-wires are electrically connected through the first and second multi-layer micro-wires and a bottom-layer micro-wire.

Abstract translation: 制造压印微线结构的方法包括提供衬底，第一印模和不同的多级第二印模。 在基板上设置可固化的底层。 一个或多个底层微通道被印刷在可固化底层中，第一印模和底层微线形成在每个底层微通道中。 在固化的底层附近形成可固化的多层，并且与固化的底层接触。 第一和第二多层微通道和顶层微通道用多级第二印记印在可固化多层中。 两个底层微电线通过第一和第二多层微线电连接，并且顶层微线或两个顶层微线通过第一和第二多层微电子电连接 电线和底层微线。

公开(公告)号：US20150333387A1

公开(公告)日：2015-11-19

申请号：US14278330

申请日：2014-05-15

Applicant: KAI XIAO ,  RAUL ENRIQUEZ SHIBAYAMA ,  GONG OUYANG

Inventor： KAI XIAO ,  RAUL ENRIQUEZ SHIBAYAMA ,  GONG OUYANG

IPC: H01P3/08 ,  H01P11/00

CPC classification number: H05K1/0245 ,  B33Y10/00 ,  B33Y80/00 ,  H01P3/02 ,  H01P3/08 ,  H01P11/003 ,  H05K2201/09281 ,  Y10T29/49156

Abstract: A broadside coupled differential design is described herein. The design may include a differential pair. Each trace of the differential pair includes a wide portion and a narrow portion. The wide portion of the first trace of the differential pair is to be aligned with a narrow portion of the second trace of the differential pair. Additionally, the wide portion of the second trace of the differential pair is to be aligned with a narrow portion of the first trace of the differential pair, such that the wide and narrow portions of the traces of the differential pair are staggered.

Abstract translation: 这里描述了宽边耦合差分设计。 该设计可以包括差分对。 差分对的每个迹线包括宽部分和窄部分。 差分对的第一迹线的宽部分将与差分对的第二迹线的窄部分对准。 此外，差分对的第二迹线的宽部分将与差分对的第一迹线的窄部分对齐，使得差分对的迹线的宽和窄部分交错。

公开(公告)号：US09101056B2

公开(公告)日：2015-08-04

申请号：US14012240

申请日：2013-08-28

Applicant: Eastman Kodak Company

Inventor： Ronald Steven Cok

IPC: H01B13/00 ,  H05K1/02 ,  H05K3/46 ,  H05K3/12 ,  H05K3/00 ,  H05K1/09

CPC classification number: H05K1/0274 ,  H05K1/0298 ,  H05K1/097 ,  H05K3/0041 ,  H05K3/12 ,  H05K3/1258 ,  H05K3/1275 ,  H05K3/1283 ,  H05K3/1291 ,  H05K3/465 ,  H05K3/4685 ,  H05K2201/09209 ,  H05K2201/09281 ,  H05K2201/0979 ,  H05K2201/09845 ,  H05K2203/0108

Abstract: A method of making an imprinted micro-wire structure includes providing a substrate having an edge area and a central area separate from the edge area and providing a first stamp and a multi-level second stamp. A curable bottom layer and multi-layer are provided on the substrate. A bottom-layer micro-channel is imprinted in the bottom layer. A multi-layer micro-channel and a top-layer micro-channel are imprinted in the multi-layer. Micro-wires are formed in each micro-channel. The bottom-layer micro-wire extends from the central area into the edge area. The multi-layer micro-wire contacts the bottom-layer micro-wire in the edge area. The top-layer micro-wire is over the central area and is separate from the multi-layer micro-wire and the bottom-layer micro-channel. The bottom-layer micro-wire is electrically connected to the multi-layer micro-wire and is electrically isolated from the top-layer micro-wire.

Abstract translation: 制造压印微线结构的方法包括提供具有与边缘区域分离的边缘区域和中心区域的基板，并提供第一印模和多级第二印模。 在基板上设置有可固化的底层和多层。 底层微通道印在底层中。 多层微通道和顶层微通道印在多层中。 微线形成在每个微通道中。 底层微线从中心区域延伸到边缘区域。 多层微线接触边缘区域的底层微线。 顶层微线在中心区域之上，与多层微线和底层微通道分离。 底层微线电连接到多层微线，并与顶层微线电隔离。