公开(公告)号：US20160205765A1

公开(公告)日：2016-07-14

申请号：US14914987

申请日：2014-09-30

Applicant: FUJIKURA LTD.

Inventor： Ryotaro TAKAGI ,  Kosuke SHIMOZURU ,  Yuji INATANI

IPC: H05K1/02 ,  H05K1/11

CPC classification number: H05K1/028 ,  H05K1/0215 ,  H05K1/0281 ,  H05K1/0298 ,  H05K1/0393 ,  H05K1/115 ,  H05K1/118 ,  H05K3/0061 ,  H05K2201/0305 ,  H05K2201/09063 ,  H05K2201/09554 ,  H05K2201/09627 ,  H05K2203/043 ,  H05K2203/1178 ,  H05K2203/167

Abstract: A wiring board assembly (1) includes: a flexible printed wiring board (2) which includes at least an insulating substrate (5) including a through-hole (53), and wiring patterns (61) and (62) provided on the insulating substrate (5) and extending to peripheral edge portions (531n) and (532n) of the through-hole (53); a metal reinforcing plate (3) attached to the flexible printed wiring board (2) and facing the through-hole (53); and a solder connection portion (4) covering an inner wall surface (534) of the through-hole (53) and electrically connecting the wiring patterns (61) and (62) to the metal reinforcing plate (3).

Abstract translation: 布线板组件（1）包括：柔性印刷布线板（2），其至少包括具有通孔（53）的绝缘基板（5）和设置在绝缘层上的布线图案（61）和（62） 基板（5）并延伸到通孔（53）的周边边缘部分（531n）和（532n）; 安装在柔性印刷电路板（2）上并与通孔（53）相对的金属加强板（3）; 以及覆盖通孔（53）的内壁面（534）并将布线图案（61）和（62）电连接到金属加强板（3）的焊料连接部分（4）。

公开(公告)号：US09173283B2

公开(公告)日：2015-10-27

申请号：US14132118

申请日：2013-12-18

Applicant: ShenZhen Goldsun Network Intelligence Technology Co., Ltd.

Inventor： Shao-You Tang ,  Po-Chuan Hsieh

IPC: H05K1/02 ,  H05K1/16

CPC classification number: H05K1/0225 ,  H05K1/0222 ,  H05K1/0245 ,  H05K1/0253 ,  H05K1/16 ,  H05K2201/09254 ,  H05K2201/09618 ,  H05K2201/09627

Abstract: A printed circuit board (PCB) includes a ground layer, a first layer, a second layer, a connector footprint, and a pair of differential signal lines. The connector footprint comprises first and second bonding pads. The PCB defines a first signal via in a central portion of a space bounded by the first bonding pad, and a second signal via in a central portion of a space bounded by the second bonding pad. A number of first ground vias on the first bonding pad and a number of second ground vias on the second bonding pad are electrically connected to the ground layer. First annular slots surrounding corresponding first ground via are defined in the ground layer. Second annular slots surrounding corresponding second ground vias are defined in the ground layer. Connection slots are defined in the ground layer and communicate between the first annular slots and the second annular slots.

Abstract translation: 印刷电路板（PCB）包括接地层，第一层，第二层，连接器覆盖区和一对差分信号线。 连接器封装包括第一和第二焊盘。 PCB在由第一接合焊盘限定的空间的中心部分中限定第一信号通道，以及在由第二接合焊盘界定的空间的中心部分中的第二信号通孔。 第一接合焊盘上的多个第一接地通孔和第二接合焊盘上的多个第二接地通孔电连接到接地层。 围绕对应的第一接地通孔的第一环形槽限定在接地层中。 围绕相应的第二接地通孔的第二环形槽限定在接地层中。 连接槽限定在接地层中，并在第一环形槽和第二环形槽之间连通。

公开(公告)号：US09036305B1

公开(公告)日：2015-05-19

申请号：US14082340

申请日：2013-11-18

Applicant: HGST Netherlands B.V.

Inventor： John Thomas Contreras ,  Nobumasa Nishiyama ,  Eiji Soga ,  Kazuhiro Nagaoka ,  Rehan Zakai

IPC: G11B5/55 ,  G11B5/02

CPC classification number: G11B5/484 ,  G11B5/4846 ,  G11B5/4853 ,  G11B5/486 ,  H05K1/0228 ,  H05K1/0245 ,  H05K1/025 ,  H05K1/0265 ,  H05K1/056 ,  H05K2201/09236 ,  H05K2201/09509 ,  H05K2201/09554 ,  H05K2201/09627 ,  H05K2203/0323

Abstract: A multiple-segment transmission line in a hard disk drive enables a wider optimization range of the slope, duration and amplitude of the transmission line overshoot (TLO) wave shape. There is a first segment with two traces for connection to the write driver circuitry, an end segment with two traces for connection to the write head and at least two intermediate segments. The number of traces in a segment is different from the number of traces in the segments to which the segment is immediately connected. There is an even number of traces in each segment and the traces in each segment are interleaved. The number of segments and the number of traces in each segment can be selected to achieve the desired impedance levels for the different segments to achieve the desired wave shape for the TLO. All of the traces on the transmission line are preferably coplanar.

Abstract translation: 硬盘驱动器中的多段传输线能够实现传输线过冲（TLO）波形的斜率，持续时间和振幅的较宽优化范围。 存在具有用于连接到写入驱动器电路的两个迹线的第一段，具有用于连接到写入头和至少两个中间段的两条迹线的端段。 段中的轨迹数不同于段立即连接到的段中的轨迹数。 在每个段中存在偶数个迹线，并且每个段中的迹线被交织。 可以选择段的数量和每个段中的迹线数以实现不同段的期望阻抗水平以实现TLO的期望波形。 传输线上的所有迹线最好是共面的。

公开(公告)号：US20150027762A1

公开(公告)日：2015-01-29

申请号：US14444144

申请日：2014-07-28

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Yong Sang SHIN ,  Joo Sung PARK

IPC: H05K1/02 ,  H05K1/11 ,  H05K1/09

CPC classification number: H05K1/0271 ,  H05K1/112 ,  H05K1/113 ,  H05K3/4644 ,  H05K2201/09527 ,  H05K2201/09627 ,  H05K2201/09781 ,  H05K2201/0979

Abstract: Disclosed herein is a printed circuit board capable of increasing reliability by decreasing stress between an insulating layer and solder balls. The printed circuit board includes: an insulating layer part including circuit patterns and connecting lands having solder balls seated thereon and including a plurality of insulating layers; a plurality of connecting pads and non-connecting pads formed at the insulating layer part; and a plurality of reinforcing vias formed in the non-connecting pads and reinforcing a close adhesion state between the insulating layer part and the non-connecting pads.

Abstract translation: 这里公开了能够通过降低绝缘层和焊球之间的应力来提高可靠性的印刷电路板。 印刷电路板包括：包括电路图案的绝缘层部分和其上安装有焊球并且包括多个绝缘层的连接焊盘; 多个连接焊盘和形成在绝缘层部分的非连接焊盘; 以及形成在所述非连接焊盘中的多个加强通孔，并且在所述绝缘层部分和所述非连接焊盘之间增强紧密粘合状态。

公开(公告)号：US20140301058A1

公开(公告)日：2014-10-09

申请号：US14227453

申请日：2014-03-27

Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.

Inventor： Satoshi SUNOHARA ,  Keiji YOSHIZAWA

IPC: H01L23/522 ,  H05K1/11 ,  H05K1/18

CPC classification number: H05K1/115 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49894 ,  H01L2224/16225 ,  H01L2924/15174 ,  H05K3/4602 ,  H05K3/4673 ,  H05K2201/0195 ,  H05K2201/0209 ,  H05K2201/09627 ,  H05K2203/1476

Abstract: A wiring substrate includes a first insulation layer, a first wiring layer formed on the first insulation layer, and a second insulation layer stacked on the first insulation layer. The second insulation layer covers the first insulation layer and includes a filler. A third insulation layer is stacked on the second insulation layer. The third insulation layer is filler-free. A through electrode extends through the second and third insulation layers in a thicknesswise direction. A second wiring layer is stacked on the third insulation layer and the through electrode. The through electrode electrically connects the second wiring layer to the first wiring layer.

Abstract translation: 布线基板包括第一绝缘层，形成在第一绝缘层上的第一布线层和堆叠在第一绝缘层上的第二绝缘层。 第二绝缘层覆盖第一绝缘层并且包括填充物。 第三绝缘层堆叠在第二绝缘层上。 第三绝缘层是无填料的。 通孔在厚度方向上延伸穿过第二和第三绝缘层。 第二布线层堆叠在第三绝缘层和贯通电极上。 通孔电连接第二布线层与第一布线层。

公开(公告)号：US08479386B2

公开(公告)日：2013-07-09

申请号：US12944904

申请日：2010-11-12

Applicant: Takeshi Shioga ,  Kazuaki Kurihara ,  Kanae Nakagawa ,  Taiji Sakai ,  Masataka Mizukoshi

Inventor： Takeshi Shioga ,  Kazuaki Kurihara ,  Kanae Nakagawa ,  Taiji Sakai ,  Masataka Mizukoshi

IPC: H05K3/02

CPC classification number: H05K1/162 ,  H01L21/486 ,  H01L23/15 ,  H01L23/498 ,  H01L23/49827 ,  H01L23/50 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/3011 ,  H05K1/0306 ,  H05K1/112 ,  H05K3/4605 ,  H05K2201/0179 ,  H05K2201/09509 ,  H05K2201/096 ,  H05K2201/09627 ,  H05K2201/10378 ,  Y10T29/49002 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49155 ,  Y10T29/49156 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A method for manufacturing an interposer including forming a capacitor over a semiconductor substrate; forming a first resin layer with a first partial electrode buried in over the semiconductor substrate and the capacitor; cutting an upper part of the first partial electrode and the first resin layer with a cutting tool; forming a second resin layer with a second partial electrode buried in over a glass substrate with a through-electrode buried in; cutting an upper part of the second partial electrode and the second resin layer with the cutting tool; making thermal processing with the first resin layer and the second resin layer adhered to each other while connecting the first partial electrode and the second partial electrode to each other; removing the semiconductor substrate; forming a third resin layer over the glass substrate, covering the capacitor; and burying a third partial electrode in the third resin layer.

Abstract translation: 一种用于制造包括在半导体衬底上形成电容器的插入器的方法; 形成第一树脂层，其中第一部分电极埋在半导体衬底和电容器之上; 用切割工具切割第一部分电极和第一树脂层的上部; 形成具有埋在玻璃基板上的第二部分电极的第二树脂层，其中埋入有通孔; 用切割工具切割第二部分电极和第二树脂层的上部; 在使第一部分电极和第二部分电极彼此连接的同时，使第一树脂层和第二树脂层彼此粘合; 去除半导体衬底; 在玻璃基板上形成第三树脂层，覆盖电容器; 并在第三树脂层中埋设第三部分电极。

公开(公告)号：US08368488B2

公开(公告)日：2013-02-05

申请号：US12155941

申请日：2008-06-11

Applicant: Han Kim ,  Hyung-Sik Choi ,  Sang-Hoon Kim ,  Joon-Sung Kim

Inventor： Han Kim ,  Hyung-Sik Choi ,  Sang-Hoon Kim ,  Joon-Sung Kim

IPC: H01P1/203

CPC classification number: H05K1/116 ,  H01L2224/16225 ,  H01L2924/00011 ,  H01L2924/00014 ,  H05K1/0236 ,  H05K2201/09309 ,  H05K2201/09627 ,  H01L2224/0401

Abstract: An electromagnetic bandgap structure and a printed circuit board that can solve a mixed signal problem between an analog circuit and a digital circuit are disclosed. In accordance with an embodiment of the present invention, an electromagnetic bandgap structure is stacked with a first metal layer, a first dielectric layer, a metal plate, a second dielectric layer and a second metal layer, and an odd number of vias can be serially connected through a metal line between the first metal layer and the metal plate. This electromagnetic bandgap structure can have a small size and a low bandgap frequency.

Abstract translation: 公开了可解决模拟电路和数字电路之间的混合信号问题的电磁带隙结构和印刷电路板。 根据本发明的实施例，电磁带隙结构层叠有第一金属层，第一介电层，金属板，第二介电层和第二金属层，并且可以串联奇数个通孔 通过第一金属层和金属板之间的金属线连接。 该电磁带隙结构可以具有小尺寸和低带隙频率。

公开(公告)号：US08344266B2

公开(公告)日：2013-01-01

申请号：US11837322

申请日：2007-08-10

Applicant: Steven C. Bird ,  Linda M. Mazaheri ,  Bob Needham ,  Phuong Rosalynn Duong

Inventor： Steven C. Bird ,  Linda M. Mazaheri ,  Bob Needham ,  Phuong Rosalynn Duong

IPC: H05K1/11

CPC classification number: H05K1/113 ,  H05K1/0231 ,  H05K2201/09227 ,  H05K2201/09536 ,  H05K2201/09627 ,  H05K2201/10734

Abstract: Techniques for optimizing application specific integrated circuit (ASIC) and other IC pin assignment corresponding to a high density interconnect (HDI) printed circuit board (PCB) layout are provided. Applying the techniques described herein, pin assignments may be systematically and strategically planned, for example, in an effort to reduce the PCB layer count and associated cost, increase signal integrity and speed, reduce the surface area used by an ASIC and its support circuitry, reduce plane perforations, and reduce via crosstalk when compared to conventional designs with an ASIC mounted on a multilayered PCB.

Abstract translation: 提供了用于优化专用集成电路（ASIC）和对应于高密度互连（HDI）印刷电路板（PCB）布局）的其他IC引脚分配的技术。 应用本文描述的技术，可以系统地和策略性地规划引脚分配，例如，为了减少PCB层数量和相关成本，增加信号完整性和速度，减少由ASIC及其支持电路使用的表面积， 与安装在多层PCB上的ASIC的传统设计相比，减少了平面穿孔，并减少了串扰。

公开(公告)号：US08315678B2

公开(公告)日：2012-11-20

申请号：US12247475

申请日：2008-10-08

Applicant: Sergey V. Uchaykin

Inventor： Sergey V. Uchaykin

IPC: H01L39/24 ,  H05K1/00 ,  H05K3/00

CPC classification number: H05K3/429 ,  H01L39/14 ,  H05K1/0298 ,  H05K1/09 ,  H05K1/115 ,  H05K3/24 ,  H05K2201/0391 ,  H05K2201/09627 ,  Y10T29/49124 ,  Y10T428/24917

Abstract: Superconducting connections are provided to internal layers of a multi-layer circuit board structure, for example by superconducting vias.

Abstract translation: 超导连接提供给多层电路板结构的内层，例如通过超导通孔。

公开(公告)号：US20120267756A1

公开(公告)日：2012-10-25

申请号：US13542444

申请日：2012-07-05

Applicant: Hao Shi ,  Jung-Hoon Chun ,  Xingchao Yuan

Inventor： Hao Shi ,  Jung-Hoon Chun ,  Xingchao Yuan

IPC: H01L23/488 ,  G06F17/50

CPC classification number: H01L23/49838 ,  H01L23/49822 ,  H01L23/50 ,  H01L23/645 ,  H01L24/05 ,  H01L2224/0401 ,  H01L2224/05552 ,  H01L2224/05553 ,  H01L2224/05555 ,  H01L2224/16 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/3011 ,  H05K1/112 ,  H05K1/165 ,  H05K3/4602 ,  H05K2201/09627 ,  H05K2201/10674 ,  H01L2924/00

Abstract: In some embodiments, the semiconductor package includes a substrate having multiple layers, from a first layer to a final layer, a die coupled to the first layer, an electrical connector such as a solder ball coupled to the final layer, and a spiral trace disposed and electrically coupled between the die and the electrical connector. Inductance of the spiral trace is selected such that the package has a predetermined impedance. Material, cross-sectional area, number and density of windings, and total overall length of the spiral trace are selected accordingly. In other embodiments, the semiconductor package includes a substrate with multiple layers; a die coupled to the first of the layers; an electrical connector coupled to the final layer; and a spiral trace, in or on the substrate. The spiral trace is near the die, and electrically coupled between the die and the electrical connector.

Abstract translation: 在一些实施例中，半导体封装包括具有多个层的衬底，从第一层到最终层，耦合到第一层的管芯，耦合到最终层的焊球等电连接器以及布置在其上的螺旋迹线 并且电连接在管芯和电连接器之间。 选择螺旋迹线的电感，使得封装具有预定的阻抗。 相应地选择材料，横截面积，绕组的数量和密度以及螺旋迹线的总长度。 在其他实施例中，半导体封装包括具有多层的衬底; 耦合到第一层的管芯; 耦合到最终层的电连接器; 以及衬底中或衬底上的螺旋迹线。 螺旋迹线靠近模具，并且电连接在管芯和电连接器之间。