公开(公告)号：US08680960B2

公开(公告)日：2014-03-25

申请号：US13797387

申请日：2013-03-12

Applicant: NuCurrent, Inc.

Inventor： Vinit Singh ,  Jacob Babcock ,  Christine A. Frysz

IPC: H01F5/00

CPC classification number: H01Q1/38 ,  A61N1/0553 ,  A61N1/3605 ,  A61N1/37229 ,  A61N1/3756 ,  A61N1/3787 ,  B33Y80/00 ,  H01F5/00 ,  H01F5/003 ,  H01F7/06 ,  H01F17/00 ,  H01F17/0006 ,  H01F17/0013 ,  H01F17/02 ,  H01F21/005 ,  H01F27/28 ,  H01F27/2804 ,  H01F27/30 ,  H01F27/42 ,  H01F29/02 ,  H01F38/14 ,  H01F41/00 ,  H01F41/04 ,  H01F41/041 ,  H01F41/32 ,  H01F2027/2809 ,  H01Q7/00 ,  H01R43/00 ,  H01R43/20 ,  H02J7/025 ,  H02J17/00 ,  H02J50/12 ,  H02P13/00 ,  H03H7/01 ,  H04B5/0031 ,  H04B5/0037 ,  H04B5/0062 ,  H04B5/0068 ,  H04B5/0075 ,  H05B6/06 ,  H05B6/1245 ,  H05B6/36 ,  H05B6/362 ,  H05K1/165 ,  H05K2201/0352 ,  Y02B40/126 ,  Y10T29/49005 ,  Y10T29/4902 ,  Y10T29/4908 ,  Y10T29/49117 ,  Y10T29/49155 ,  Y10T29/49169 ,  Y10T29/49195

Abstract: A multi-layer, multi-turn structure for an inductor having a plurality of conductor layers separated by layers of insulator is described. The inductor further comprises a connector electrically connected between the conductor layers. The structure of the inductor may comprise a cavity therewithin. The structure of the inductor constructed such that electrical resistance is reduced therewithin, thus increasing the efficiency of the inductor. The inductor is particularly useful at operating within the radio frequency range and greater.

Abstract translation: 描述了具有由绝缘体层隔开的多个导体层的电感器的多层多匝结构。 该电感器还包括电连接在导体层之间的连接器。 电感器的结构可以包括其中的空腔。 电感器的结构使得电阻在其中减小，从而提高电感器的效率。 电感器在无线电频率范围内工作时特别有用。

公开(公告)号：US20140063761A1

公开(公告)日：2014-03-06

申请号：US13601704

申请日：2012-08-31

Applicant: Chuan Hu

Inventor： Chuan Hu

IPC: H05K1/11 ,  H05K3/10 ,  H05K7/06

CPC classification number: H05K1/11 ,  H01L23/66 ,  H01L2924/0002 ,  H05K1/0216 ,  H05K1/024 ,  H05K1/025 ,  H05K3/002 ,  H05K3/0029 ,  H05K3/10 ,  H05K3/107 ,  H05K3/465 ,  H05K2201/0352 ,  H05K2201/09036 ,  H05K2203/058 ,  Y10T29/49162 ,  H01L2924/00

Abstract: Off-plane conductive line interconnects may be formed in microelectronic devices. In one example, such as device includes a first set of metal conductive lines in a dielectric substrate at a first horizontal layer of the substrate, a second set of metal conductive lines in the substrate at the first horizontal layer of the substrate and vertically offset from the first set of metal lines, and a dielectric material insulating the metal lines from each other and the first horizontal layer from other horizontal layers. Vias in the dielectric material to connect both the first and second set of metal lines to metal lines at a second horizontal layer of the substrate.

Abstract translation: 离平面导线互连可以形成在微电子器件中。 在一个示例中，例如器件包括在衬底的第一水平层处的电介质衬底中的第一组金属导电线，在衬底的第一水平层处的第二组金属导电线，并且垂直偏离 第一组金属线，以及电介质材料，使金属线彼此绝缘，并且第一水平层与其他水平层绝缘。 电介质材料中的通孔将第一和第二组金属线连接到衬底的第二水平层处的金属线。

公开(公告)号：US20130299218A1

公开(公告)日：2013-11-14

申请号：US13936420

申请日：2013-07-08

Applicant: IBIDEN CO., LTD.

Inventor： Yasushi INAGAKI ,  Katsuyuki Sano

IPC: H05K1/09

CPC classification number: H05K1/09 ,  H01L23/49816 ,  H01L23/49822 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01025 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/19106 ,  H01L2924/3011 ,  H01L2924/3511 ,  H05K1/0237 ,  H05K1/056 ,  H05K1/183 ,  H05K1/185 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/4608 ,  H05K3/4641 ,  H05K2201/0347 ,  H05K2201/0352 ,  H05K2201/09309 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2201/09809 ,  H01L2224/05599

Abstract: A package substrate free of malfunction or error even with an IC chip in a high frequency range, particularly an IC chip with a frequency exceeding 3 GHz, is provided. A conductor layer 34P on a core substrate 30 is formed to have a thickness of 30 μm and a conductor circuit 58 on an interlayer resin insulating layer 50 is formed to have a thickness of 15 μm. By making the conductor layer 34P thick, it is possible to increase a volume of the conductor itself and decrease resistance. Further, by employing the conductor layer 34 as a power supply layer, it is possible to improve a capability of supplying power to the IC chip.

Abstract translation: 即使IC芯片处于高频范围，特别是具有频率超过3GHz的IC芯片，也不会出现故障或误差的封装基板。 芯基板30上的导体层34P形成为具有30μm的厚度，层间树脂绝缘层50上的导体电路58形成为15μm的厚度。 通过使导体层34P变厚，可以增加导体本身的体积并降低电阻。 此外，通过使用导体层34作为电源层，可以提高向IC芯片供电的能力。

公开(公告)号：US08569880B2

公开(公告)日：2013-10-29

申请号：US12869841

申请日：2010-08-27

Applicant: Yasushi Inagaki ,  Katsuyuki Sano

Inventor： Yasushi Inagaki ,  Katsuyuki Sano

IPC: H01L23/522

CPC classification number: H01L23/66 ,  H01L21/4857 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/50 ,  H01L23/5383 ,  H01L23/5386 ,  H01L24/81 ,  H01L2223/6616 ,  H01L2223/6622 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/13111 ,  H01L2224/16225 ,  H01L2224/81192 ,  H01L2224/81801 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01025 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01058 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01084 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/15787 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/19106 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/351 ,  H05K1/056 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/4608 ,  H05K3/4641 ,  H05K2201/0352 ,  H05K2201/09536 ,  H05K2201/09736 ,  H05K2201/098 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A multilayer printed wiring board in which interlayer insulation layer and conductive layer are formed on a multilayer core substrate composed of three or more layers, having through holes for connecting the front surface with the rear surface and conductive layers on the front and rear surfaces and conductive layer in the inner layer to achieve electric connection through via holes, the through holes being composed of power source through holes, grounding through holes and signal through holes connected electrically to a power source circuit or a grounding circuit or a signal circuit of an IC chip, when the power source through holes pass through the grounding conductive layer of the inner layer in the core substrate, of the power source through holes, at least a power source through hole just below the IC having no conductive circuit extending from the power source through hole in the grounding conductive layer.

Abstract translation: 一种多层印刷电路板，其中层间绝缘层和导电层形成在由三层或更多层组成的多层芯基板上，具有用于将前表面与后表面连接的通孔和前表面和后表面上的导电层，并具有导电性 层，通过通孔进行电连接，通孔由电源通孔，接地通孔和与电源电路或接地电路或IC芯片的信号电路电连接的信号通孔组成， 当电源通孔穿过核心基板中的内层的接地导电层时，通过电源通孔，至少在IC下面至少有一个电源通孔，IC上没有从电源延伸的导电电路， 接地导电层中的孔。

公开(公告)号：US20130200969A1

公开(公告)日：2013-08-08

申请号：US13797437

申请日：2013-03-12

Applicant: NuCurrent, Inc.

Inventor： Vinit SINGH ,  Jacob BABCOCK ,  Christine A. FRYSZ

IPC: H01F21/00 ,  H01F5/00

CPC classification number: H01Q1/38 ,  A61N1/0553 ,  A61N1/3605 ,  A61N1/37229 ,  A61N1/3756 ,  A61N1/3787 ,  B33Y80/00 ,  H01F5/00 ,  H01F5/003 ,  H01F7/06 ,  H01F17/00 ,  H01F17/0006 ,  H01F17/0013 ,  H01F17/02 ,  H01F21/005 ,  H01F27/28 ,  H01F27/2804 ,  H01F27/30 ,  H01F27/42 ,  H01F29/02 ,  H01F38/14 ,  H01F41/00 ,  H01F41/04 ,  H01F41/041 ,  H01F41/32 ,  H01F2027/2809 ,  H01Q7/00 ,  H01R43/00 ,  H01R43/20 ,  H02J7/025 ,  H02J17/00 ,  H02J50/12 ,  H02P13/00 ,  H03H7/01 ,  H04B5/0031 ,  H04B5/0037 ,  H04B5/0062 ,  H04B5/0068 ,  H04B5/0075 ,  H05B6/06 ,  H05B6/1245 ,  H05B6/36 ,  H05B6/362 ,  H05K1/165 ,  H05K2201/0352 ,  Y02B40/126 ,  Y10T29/49005 ,  Y10T29/4902 ,  Y10T29/4908 ,  Y10T29/49117 ,  Y10T29/49155 ,  Y10T29/49169 ,  Y10T29/49195

Abstract: A multi-layer, multi-turn structure for an inductor having a plurality of conductor layers separated by layers of insulator is described. The inductor further comprises a connector electrically connected between the conductor layers. The structure of the inductor may comprise a cavity therewithin. The structure of the inductor constructed such that electrical resistance is reduced therewithin, thus increasing the efficiency of the inductor. The inductor is particularly useful at operating within the radio frequency range and greater.

Abstract translation: 描述了具有由绝缘体层隔开的多个导体层的电感器的多层多匝结构。 电感器还包括电连接在导体层之间的连接器。 电感器的结构可以包括其中的空腔。 电感器的结构使得电阻在其中减小，从而提高电感器的效率。 电感器在无线电频率范围内工作时特别有用。

公开(公告)号：US20130200070A1

公开(公告)日：2013-08-08

申请号：US13797593

申请日：2013-03-12

Applicant: NuCurrent, Inc.

Inventor： Vinit SINGH ,  Jacob BABCOCK ,  Christine A. FRYSZ

IPC: H05B6/36

CPC classification number: H01Q1/38 ,  A61N1/0553 ,  A61N1/3605 ,  A61N1/37229 ,  A61N1/3756 ,  A61N1/3787 ,  B33Y80/00 ,  H01F5/00 ,  H01F5/003 ,  H01F7/06 ,  H01F17/00 ,  H01F17/0006 ,  H01F17/0013 ,  H01F17/02 ,  H01F21/005 ,  H01F27/28 ,  H01F27/2804 ,  H01F27/30 ,  H01F27/42 ,  H01F29/02 ,  H01F38/14 ,  H01F41/00 ,  H01F41/04 ,  H01F41/041 ,  H01F41/32 ,  H01F2027/2809 ,  H01Q7/00 ,  H01R43/00 ,  H01R43/20 ,  H02J7/025 ,  H02J17/00 ,  H02J50/12 ,  H02P13/00 ,  H03H7/01 ,  H04B5/0031 ,  H04B5/0037 ,  H04B5/0062 ,  H04B5/0068 ,  H04B5/0075 ,  H05B6/06 ,  H05B6/1245 ,  H05B6/36 ,  H05B6/362 ,  H05K1/165 ,  H05K2201/0352 ,  Y02B40/126 ,  Y10T29/49005 ,  Y10T29/4902 ,  Y10T29/4908 ,  Y10T29/49117 ,  Y10T29/49155 ,  Y10T29/49169 ,  Y10T29/49195

Abstract: A multi-layer, multi-turn structure for an inductor having a plurality of conductor layers separated by layers of insulator is described. The inductor further comprises a connector electrically connected between the conductor layers. The structure of the inductor may comprise a cavity therewithin. The structure of the inductor constructed such that electrical resistance is reduced therewithin, thus increasing the efficiency of the inductor. The inductor is particularly useful at operating within the radio frequency range and greater.

Abstract translation: 描述了具有由绝缘体层隔开的多个导体层的电感器的多层多匝结构。 电感器还包括电连接在导体层之间的连接器。 电感器的结构可以包括其中的空腔。 电感器的结构使得电阻在其中减小，从而提高电感器的效率。 电感器在无线电频率范围内工作时特别有用。

公开(公告)号：US08481424B2

公开(公告)日：2013-07-09

申请号：US13243112

申请日：2011-09-23

Applicant: Michimasa Takahashi ,  Yukinobu Mikado ,  Takenobu Nakamura ,  Masakazu Aoyama

Inventor： Michimasa Takahashi ,  Yukinobu Mikado ,  Takenobu Nakamura ,  Masakazu Aoyama

IPC: H05K3/00

CPC classification number: H01L23/48 ,  H01L2924/0002 ,  H05K1/115 ,  H05K3/00 ,  H05K3/4602 ,  H05K3/4652 ,  H05K2201/0352 ,  H05K2201/0394 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2201/09709 ,  H05K2201/09827 ,  Y10T29/49124 ,  H01L2924/00

Abstract: A method for manufacturing a multilayer printed wiring board including forming a multilayer printed wiring board structure comprising first and second buildup portions, the first buildup portion including insulating layers, conductor layers and first viaholes electrically connecting the conductor layers through the insulation layers such that the first viaholes are formed in the insulating layers, respectively, the second buildup portion including insulating layers, conductor layers and second viaholes electrically connecting the conductor layers through the insulation layers such that the first viaholes are tapered toward the second viaholes, and the second via holes are tapered toward the first viaholes. The viaholes are formed by plating openings formed after lamination of respective ones of the insulating layers of the buildup portions, and each insulating layer in the buildup portions is about 100 μm or less in thickness.

Abstract translation: 一种制造多层印刷线路板的方法，包括形成包括第一和第二积累部分的多层印刷线路板结构，所述第一累积部分包括绝缘层，导体层和通过绝缘层将导体层电连接的第一通孔，使得第一 分别在绝缘层中形成通孔，第二累积部分包括绝缘层，导体层和第二通孔，其通过绝缘层电连接导体层，使得第一通孔朝向第二通孔逐渐变细，第二通孔为 朝向第一通孔逐渐变细。 通孔由叠层后的积层部分的绝缘层各自形成的电镀开口形成，而积层部的绝缘层的厚度为100μm左右。

公开(公告)号：US20130105214A1

公开(公告)日：2013-05-02

申请号：US13665063

申请日：2012-10-31

Applicant: SAMSUNG TECHWIN CO., LTD.

Inventor： Soon Chul KWON ,  Sang Min LEE

IPC: H05K3/06 ,  H05K1/11 ,  H05K1/02

CPC classification number: H05K3/06 ,  H05K1/0296 ,  H05K1/115 ,  H05K3/4007 ,  H05K2201/0352 ,  H05K2203/1476 ,  Y10T29/49155

Abstract: Provided is a method for manufacturing a circuit board provided with metal posts formed on at least one surface of the circuit board, the method including preparing a substrate made of a conductive material, performing a first selective etching a first surface of the substrate in regions corresponding to insulating portions of a first circuit pattern, laminating a first insulating layer over the first surface of the substrate, and performing a second etching on a second surface opposite of the first surface of the substrate, thereby forming the metal posts and the first circuit.

Abstract translation: 提供一种制造电路板的方法，该电路板设置有形成在电路板的至少一个表面上的金属柱，该方法包括制备由导电材料制成的衬底，在对应的区域中进行第一选择性蚀刻衬底的第一表面 绝缘部分的第一电路图案，在基板的第一表面上层叠第一绝缘层，并且在与基板的第一表面相对的第二表面上执行第二蚀刻，由此形成金属柱和第一电路。

公开(公告)号：US20130068517A1

公开(公告)日：2013-03-21

申请号：US13673868

申请日：2012-11-09

Applicant: ADVANCED SEMICONDUCTOR ENGINEERING,

Inventor： Chih-Cheng LEE

IPC: H05K1/11

CPC classification number: H05K1/115 ,  H05K1/0298 ,  H05K3/0023 ,  H05K3/04 ,  H05K3/045 ,  H05K3/06 ,  H05K3/10 ,  H05K3/108 ,  H05K3/4038 ,  H05K3/4644 ,  H05K3/465 ,  H05K2201/0352 ,  H05K2203/025 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165

Abstract: A method for manufacturing a substrate structure is provided. The method includes the following steps. A substrate is provided. The substrate has a patterned first metal layer, a pattern second metal layer and a through hole. After that, a first dielectric layer and a second dielectric layer are formed at a first surface and a second surface of the substrate, respectively. The second surface is opposite to the first surface. Then, the first dielectric layer and the second dielectric layer are patterned. After that, a first trace layer is formed at a surface of the patterned first dielectric layer. The first trace layer is embedded into the patterned first dielectric layer and is coplanar with the first dielectric layer. Then, a second trace layer is formed on a surface of the second dielectric layer.

Abstract translation: 提供了一种用于制造衬底结构的方法。 该方法包括以下步骤。 提供基板。 衬底具有图案化的第一金属层，图案第二金属层和通孔。 之后，分别在基板的第一表面和第二表面上形成第一电介质层和第二电介质层。 第二表面与第一表面相对。 然后，对第一电介质层和第二电介质层进行图案化。 之后，在图案化的第一介电层的表面形成第一迹线层。 第一迹线层被嵌入到图案化的第一介电层中并且与第一介电层共面。 然后，在第二电介质层的表面上形成第二迹线层。

公开(公告)号：US08354688B2

公开(公告)日：2013-01-15

申请号：US13337054

申请日：2011-12-24

Applicant: Charles W. C. Lin ,  Chia-Chung Wang

Inventor： Charles W. C. Lin ,  Chia-Chung Wang

IPC: H01L33/00

CPC classification number: H05K1/021 ,  H01L21/486 ,  H01L23/3677 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L33/483 ,  H01L33/642 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/8592 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01028 ,  H01L2924/01087 ,  H01L2924/12041 ,  H01L2924/15153 ,  H01L2924/181 ,  H01L2924/3025 ,  H05K3/4084 ,  H05K2201/0352 ,  H05K2201/0355 ,  H05K2201/10106 ,  H05K2203/049 ,  H05K2203/063 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A semiconductor chip assembly includes a semiconductor device, a heat spreader, a conductive trace and dual adhesives. The heat spreader includes a bump, a base and a ledge. The conductive trace includes a pad and a terminal. The semiconductor device is mounted on the bump in a cavity in the bump, is electrically connected to the conductive trace and is thermally connected to the heat spreader. The bump extends into an opening in the first adhesive and is aligned with and spaced from an opening in the second adhesive. The base and the ledge extend laterally from the bump. The first adhesive is sandwiched between the base and the ledge, the second adhesive is sandwiched between the conductive trace and the ledge and the ledge is sandwiched between the adhesives. The conductive trace is located outside the cavity and provides signal routing between the pad and the terminal.

Abstract translation: 半导体芯片组件包括半导体器件，散热器，导电迹线和双重粘合剂。 散热器包括凸块，底座和凸缘。 导电迹线包括焊盘和端子。 半导体器件安装在凸块中的凸起中的凸起中，电连接到导电迹线并且热连接到散热器。 凸块延伸到第一粘合剂中的开口中并且与第二粘合剂中的开口对准并与之隔开。 底座和凸缘从凸块横向延伸。 第一粘合剂被夹在基部和凸缘之间，第二粘合剂夹在导电迹线和凸缘之间，并且凸缘夹在粘合剂之间。 导电迹线位于腔体外部，并在焊盘和端子之间提供信号路由。