公开(公告)号：US20100007012A1

公开(公告)日：2010-01-14

申请号：US12550327

申请日：2009-08-28

Applicant: Peter C. Salmon

Inventor： Peter C. Salmon

IPC: H01L23/50 ,  H01L23/367

CPC classification number: H05K3/363 ,  H01L21/6835 ,  H01L23/49811 ,  H01L23/5386 ,  H01L23/5387 ,  H01L24/16 ,  H01L24/81 ,  H01L2221/68345 ,  H01L2224/05573 ,  H01L2224/11332 ,  H01L2224/1134 ,  H01L2224/13099 ,  H01L2224/13109 ,  H01L2224/13144 ,  H01L2224/16237 ,  H01L2224/45144 ,  H01L2224/81052 ,  H01L2224/81191 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15788 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/351 ,  H01L2924/3651 ,  H05K1/0289 ,  H05K1/115 ,  H05K3/007 ,  H05K3/3436 ,  H05K3/3484 ,  H05K3/4015 ,  H05K3/4682 ,  H05K2201/0367 ,  H05K2201/0379 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/10674 ,  H05K2203/016 ,  H05K2203/0568 ,  Y02P70/613 ,  Y10T29/49155 ,  H01L2924/00 ,  H01L2224/05599

Abstract: This specification describes techniques for manufacturing an electronic system module. The module includes flexible multi-layer interconnection circuits with trace widths as narrow as 5 microns or less. A glass panel manufacturing facility, similar to those employed for making liquid crystal display, LCD, panels is preferably used to fabricate the interconnection circuits. A multi-layer interconnection circuit is fabricated on the glass panel using a release layer. A special assembly layer is formed over the interconnection circuit comprising a thick dielectric layer with openings formed at input/output (I/O) pad locations. Solder paste is deposited in the openings using a squeegee to form wells filled with solder. IC chips are provided with gold stud bumps at I/O pad locations, and these bumps are inserted in the wells to form flip chip connections. The IC chips are tested and reworked. The same bump/well connections can be used to attach fine-pitch cables. Module packaging layers are provided for hermetic sealing and for electromagnetic shielding. A blade server or supercomputer embodiment is also described.

Abstract translation: 本说明书描述了用于制造电子系统模块的技术。 该模块包括具有窄至5微米或更小的迹线宽度的柔性多层互连电路。 与用于制造液晶显示器，LCD，面板的玻璃面板制造设备相似，优选地用于制造互连电路。 使用剥离层在玻璃面板上制造多层互连电路。 在互连电路上形成特殊的组装层，该电路包括在输入/输出（I / O）焊盘位置处形成有开口的厚电介质层。 使用刮刀将焊膏沉积在开口中以形成填充有焊料的孔。 IC芯片在I / O焊盘位置处设有金柱凸起，并且这些凸块插入孔中以形成倒装芯片连接。 IC芯片经过测试和返工。 相同的凹凸/连接可用于连接细间距电缆。 提供模块封装层用于密封和电磁屏蔽。 还描述了刀片服务器或超级计算机实施例。

公开(公告)号：US07639338B2

公开(公告)日：2009-12-29

申请号：US11124803

申请日：2005-05-09

Applicant: Shinichi Tomari ,  Futoshi Nakanishi

Inventor： Shinichi Tomari ,  Futoshi Nakanishi

IPC: G02F1/1345

CPC classification number: G02F1/13452 ,  H05K3/323 ,  H05K3/361 ,  H05K3/4007 ,  H05K2201/0326 ,  H05K2201/0367 ,  H05K2201/09481 ,  H05K2201/09909

Abstract: A LCD device includes external terminals for metallic interconnects in a peripheral area on which TCPs are mounted. The external terminal includes a first ITO film connected to the metallic interconnect, a second ITO film formed on the first ITO film and a plurality of insulator islands sandwiched between the first ITO film and the second ITO film. The surface of the second ITO film has convex and concave portions whereby electric connection between the terminal of the TCP and the second ITO film is improved.

Abstract translation: LCD装置包括在安装有TCP的外围区域中的用于金属互连的外部端子。 外部端子包括连接到金属互连的第一ITO膜，形成在第一ITO膜上的第二ITO膜和夹在第一ITO膜和第二ITO膜之间的多个绝缘体岛。 第二ITO膜的表面具有凸部和凹部，从而提高了TCP端子与第二ITO膜之间的电连接。

公开(公告)号：US20090294962A1

公开(公告)日：2009-12-03

申请号：US12474654

申请日：2009-05-29

Applicant: Shih-Ping Hsu

Inventor： Shih-Ping Hsu

IPC: H01L23/488 ,  H01L21/60

CPC classification number: H05K3/243 ,  H01L23/49816 ,  H01L23/49866 ,  H01L24/16 ,  H01L24/45 ,  H01L24/48 ,  H01L25/0657 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01055 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01327 ,  H01L2924/181 ,  H05K1/111 ,  H05K3/3436 ,  H05K2201/0367 ,  H05K2201/0391 ,  H05K2203/049 ,  H05K2203/054 ,  H01L2224/05599 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A packaging substrate and a method for fabricating the same are proposed, including: providing a substrate body having a first surface and an opposing second surface, wherein the first surface has a plurality of flip-chip solder pads and wire bonding pads and the second surface has a plurality of solder ball pads; forming a first and a second solder mask layers on the first and second surfaces respectively and forming openings in the first and second solder mask layers to expose the flip-chip solder pads, the wire bonding pads and the solder ball pads; forming first bumps on the flip-chip solder pads; and forming an electroless Ni/Pd/Au layer on the first bumps and the wire bonding pads by electroless plating, wherein the electroless Ni/Pd/Au layer has a thickness tolerance capable of meeting evenness requirements for fine pitch applications.

Abstract translation: 提出了一种封装基板及其制造方法，包括：提供具有第一表面和相对的第二表面的基板主体，其中第一表面具有多个倒装芯片焊盘和引线接合焊盘，第二表面 具有多个焊球垫; 在第一和第二表面上形成第一和第二焊料掩模层，并在第一和第二焊料掩模层中形成开口以暴露倒装芯片焊盘，引线接合焊盘和焊球焊盘; 在倒装焊盘上形成第一凸点; 以及通过化学镀在所述第一凸块和所述引线接合焊盘上形成化学镀Ni / Pd / Au层，其中所述无电镀Ni / Pd / Au层具有能够满足细间距应用的均匀性要求的厚度公差。

公开(公告)号：US20090288861A1

公开(公告)日：2009-11-26

申请号：US12422629

申请日：2009-04-13

Applicant: Guo Cheng LIAO

Inventor： Guo Cheng LIAO

IPC: H05K1/02 ,  H05K3/00

CPC classification number: H05K3/243 ,  H05K3/20 ,  H05K3/428 ,  H05K2201/0367 ,  H05K2201/0376 ,  H05K2203/0542 ,  Y10T29/49124

Abstract: A circuit board with a buried conductive trace formed thereon according to the present invention is provided. A buried conductive trace layer is formed on the surface of a substrate and the pads of the conductive trace layer are plated with a layer of copper so that the pads are heightened to facilitate the subsequent process of molding.

Abstract translation: 提供了根据本发明的在其上形成有掩埋导电迹线的电路板。 掩埋的导电迹线层形成在衬底的表面上，并且导电迹线层的焊盘镀有一层铜，使得衬垫被加强以便于后续的模制工艺。

公开(公告)号：US07619305B2

公开(公告)日：2009-11-17

申请号：US11889693

申请日：2007-08-15

Applicant: Wen-Jeng Fan ,  Li-Chih Fang ,  Ron Iwata

Inventor： Wen-Jeng Fan ,  Li-Chih Fang ,  Ron Iwata

IPC: H01L23/02 ,  H01L23/52 ,  H01L23/48 ,  H01L29/40 ,  H01L23/488 ,  H01L23/485

CPC classification number: H05K3/3436 ,  H01L23/13 ,  H01L23/49811 ,  H01L24/16 ,  H01L24/29 ,  H01L24/48 ,  H01L25/105 ,  H01L2224/05571 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/73204 ,  H01L2224/73215 ,  H01L2224/73253 ,  H01L2224/83856 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01327 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H05K2201/0367 ,  H05K2201/0379 ,  Y02P70/613 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A stacked semiconductor device primarily comprises semiconductor packages with a plurality of micro contacts and solder paste to soldering the micro contacts. Each semiconductor package comprises a substrate and a chip disposed on the substrate. The micro contacts of the bottom semiconductor package are a plurality of top bumps located on the upper surface of the substrate. The micro contacts of the top semiconductor package are a plurality of bottom bumps located on the lower surface of the substrate. The bottom bumps are aligned with the top bumps and are electrically connected each other by the solder paste. Therefore, the top bumps and the bottom bumps have the same soldering shapes and dimensions for evenly soldering to avoid breakages of the micro bumps during stacking.

公开(公告)号：US20090250260A1

公开(公告)日：2009-10-08

申请号：US12155756

申请日：2008-06-09

Applicant: Myung Sam Kang

Inventor： Myung Sam Kang

IPC: H05K1/02 ,  B32B38/10 ,  B05D5/12 ,  C23F1/02

CPC classification number: H05K3/107 ,  H01L2924/0002 ,  H05K1/113 ,  H05K3/108 ,  H05K3/205 ,  H05K3/243 ,  H05K3/28 ,  H05K3/4007 ,  H05K3/4652 ,  H05K2201/0367 ,  H05K2201/0376 ,  H05K2201/09881 ,  H01L2924/00

Abstract: The present invention relates to a high density circuit board for increasing the density of a circuit by impregnating fine circuit patterns inside a top part of a substrate, and a method for manufacturing the same.In accordance with the present invention, a high density circuit board includes a substrate with fine circuit patterns impregnated inside top and bottom parts; a via formed inside the substrate to electrically conduct the fine circuit patterns of the top and bottom parts of the substrate each other; pads formed on the fine circuit patterns of the top part of the substrate; and solder resists formed on the top and bottom parts of the substrate, which can convert the circuit patterns into fine pitches and increase the degree of close adhesion between the substrate and the circuit patterns, thereby improving reliability.

Abstract translation: 高密度电路板及其制造方法技术领域本发明涉及一种用于通过在基板顶部浸渍精细电路图案来提高电路密度的高密度电路板及其制造方法。 根据本发明，高密度电路板包括具有浸渍在顶部和底部内部的精细电路图案的基板; 形成在基板内部的通孔，以使基板的顶部和底部的精细电路图案彼此导电; 衬垫形成在衬底的顶部的精细电路图案上; 以及形成在基板的顶部和底部上的阻焊剂，其可以将电路图案转换成细间距并增加基板和电路图案之间的紧密粘合度，从而提高可靠性。

公开(公告)号：US20090211790A1

公开(公告)日：2009-08-27

申请号：US12379518

申请日：2009-02-24

Applicant: Tsutomu Yokouchi

Inventor： Tsutomu Yokouchi

IPC: H05K1/00 ,  H05K3/30 ,  B41J2/14

CPC classification number: B41J2/14233 ,  B41J2002/14491 ,  H05K1/0393 ,  H05K3/361 ,  H05K2201/0367 ,  H05K2201/0382 ,  H05K2201/0394 ,  H05K2201/09036 ,  H05K2201/09063 ,  H05K2201/0969 ,  H05K2201/10083 ,  H05K2203/167 ,  Y10T29/49139

Abstract: The connecting structure of a flexible circuit board and electronic components, includes: the flexible circuit board having: a pattern of wires, holes passing through the flexible circuit board in a thickness direction of the wires at parts of the wires to which the electronic components are connected, and a weakened part arranged on a bending line in a bending part of the flexible circuit board on which the flexible circuit board bends when the wires are connected with the electronic components; and the electronic components respectively having projections on parts to which the wires are connected, wherein the wires are electrically connected with the electronic components in a state where the projections are inserted in the holes and the flexible circuit board bends on the weakened part.

Abstract translation: 柔性电路板和电子部件的连接结构包括：柔性电路板，其具有：电线图案，在电线部分处的电线部分处的导线的厚度方向穿过柔性电路板的孔 柔性电路板的弯曲部的弯曲线上设置的弱化部，柔性电路板在与电子部件连接时弯曲的弯曲部; 电子部件分别具有连接线的部件上的突起，其中，在突起插入孔中并且柔性电路板弯曲在弱化部上的状态下，电线与电子部件电连接。

公开(公告)号：US20090197437A1

公开(公告)日：2009-08-06

申请号：US12304680

申请日：2007-06-07

Applicant: Yasuhiro Ouchi ,  Shinichi Nikaido ,  Haruo Miyazawa

Inventor： Yasuhiro Ouchi ,  Shinichi Nikaido ,  Haruo Miyazawa

IPC: H01R4/58 ,  H01R12/00 ,  H01R43/16

CPC classification number: H05K7/1061 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2924/01004 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H05K3/326 ,  H05K3/427 ,  H05K2201/0133 ,  H05K2201/0367 ,  H05K2201/09081 ,  H05K2201/0949 ,  H05K2201/10378 ,  Y10T29/49204

Abstract: A socket includes an insulating elastomeric sheet having a penetration hole, metal circuits formed on at least one of the front and rear surfaces of the elastomeric sheet, and a through-hole having a metal film formed on an inner wall of the penetration hole. The metal circuit on the front surface of the elastomeric sheet is electrically connected to the metal circuit on the rear surface of the elastomeric sheet via the through-hole. With such a configuration of the socket, it is possible to provide a socket contact terminal and a semiconductor device having the same, which is suitable for low-resistance, large-current, and high-speed configurations.

Abstract translation: 插座包括具有穿透孔的绝缘弹性片，形成在弹性片的前表面和后表面中的至少一个上的金属电路，以及形成在穿透孔的内壁上的金属膜的通孔。 弹性片的前表面上的金属电路经由通孔与弹性片的后表面上的金属电路电连接。 通过插座的这种构造，可以提供适用于低电阻，大电流和高速配置的插座接触端子和具有该插座接触端子的半导体器件。

公开(公告)号：US07569939B2

公开(公告)日：2009-08-04

申请号：US11533485

申请日：2006-09-20

Applicant: Viren V. Khandekar ,  Chunho Kim

Inventor： Viren V. Khandekar ,  Chunho Kim

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L24/81 ,  H01L2224/10135 ,  H01L2224/10165 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16 ,  H01L2224/81136 ,  H01L2224/81141 ,  H01L2224/81203 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/83102 ,  H01L2224/92125 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H05K3/303 ,  H05K3/3436 ,  H05K2201/0367 ,  H05K2201/09781 ,  H05K2203/048 ,  H05K2203/167 ,  Y02P70/613 ,  H01L2224/0401

Abstract: Some embodiments of the present invention relate to an electronic assembly that includes a substrate and a die. The electronic assembly further includes an alignment bump on one of the die and the substrate and a group of mating bumps on the other of the die and the substrate. The group of mating bumps is positioned such that if the alignment bump engages each of the mating bumps, the die is appropriately positioned relative to the substrate at that location where the alignment bump engages the group of mating bumps. In some embodiments, the alignment bump extends from the substrate while in other embodiments the alignment bump extends from the die. The alignment bump on the substrate (or die) may be part of a plurality of alignment bumps such that each alignment bump engages a different group of mating bumps on the die (or substrate).

公开(公告)号：US07560016B1

公开(公告)日：2009-07-14

申请号：US12291277

申请日：2008-11-07

Applicant: Steven T. Mayer ,  John Stephen Drewery

Inventor： Steven T. Mayer ,  John Stephen Drewery

IPC: C25D5/02

CPC classification number: H05K3/243 ,  H05K3/108 ,  H05K2201/0367 ,  H05K2201/09745 ,  H05K2203/0392 ,  H05K2203/122

Abstract: To make a metal feature, a non-plateable layer is applied to a workpiece surface and then patterned to form a first plating region and a first non-plating region. Then, metal is deposited on the workpiece to form a raised field region in said first plating region and a recessed region in said first non-plating region. Then, an accelerator film is applied globally on the workpiece. A portion of the accelerator film is selectively removed from the field region, and another portion of the accelerator film remains in the recessed acceleration region. Then, metal is deposited onto the workpiece, and the metal deposits at an accelerated rate in the acceleration region, resulting in a greater thickness of metal in the acceleration region compared to metal in the non-activated field region. Then, metal is completely removed from the field region, thereby forming the metal feature.

Abstract translation: 为了制造金属特征，将不可镀层施加到工件表面，然后被图案化以形成第一镀层区域和第一非镀层区域。 然后，金属沉积在工件上，以在所述第一镀覆区域中形成凸起区域，并在所述第一非镀覆区域中形成凹陷区域。 然后，加工膜全部应用于工件上。 加速膜的一部分从场区域选择性地去除，并且加速膜的另一部分残留在凹入加速区域中。 然后，金属沉积在工件上，并且金属在加速区域中以加速的速率沉积，导致与非激活场区域中的金属相比，加速区域中的金属厚度更大。 然后，从场区域中完全去除金属，从而形成金属特征。