公开(公告)号：US20100032826A1

公开(公告)日：2010-02-11

申请号：US12517551

申请日：2007-12-05

Applicant: Kenya Tachibana ,  Masahiro Wada ,  Hitoshi Kawaguchi ,  Kensuke Nakamura

Inventor： Kenya Tachibana ,  Masahiro Wada ,  Hitoshi Kawaguchi ,  Kensuke Nakamura

IPC: H01L23/48 ,  C08G18/77

CPC classification number: H01L21/563 ,  C08L63/00 ,  H01L23/293 ,  H01L23/3735 ,  H01L23/3737 ,  H01L23/49822 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/10253 ,  H05K1/0271 ,  H05K3/305 ,  H05K3/4602 ,  H05K2201/068 ,  H05K2201/10674 ,  H05K2201/10977 ,  H01L2924/00 ,  H01L2224/0401

Abstract: A flip-chip semiconductor package includes a circuit board having a core layer and at least one buildup layer, a semiconductor device connected to the circuit board through a metal bump, and a cured member that is made of a sealing resin composition and enclosed between the semiconductor device and the circuit board. The coefficient of linear expansion at 25 to 75° C. of the cured member is 15 to 35 ppm/° C., the glass transition temperature of at least one buildup layer is 170° C. or more, and the coefficient of linear expansion of at 25 to 75° C. of the at least one buildup layer in the planar direction is 25 ppm or less. A highly reliable flip-chip semiconductor package, buildup layer material, core layer material, and sealing resin composition can be provided by preventing cracks and inhibiting delamination.

Abstract translation: 倒装芯片半导体封装包括具有芯层和至少一个堆积层的电路板，通过金属凸块连接到电路板的半导体器件，以及由密封树脂组合物制成的封装在其间的固化构件 半导体器件和电路板。 固化部件的25〜75℃的线膨胀系数为15〜35ppm /℃，至少一层积层的玻璃化转变温度为170℃以上，线膨胀系数 在平面方向上的至少一个堆积层的25〜75℃为25ppm以下。 可以通过防止裂纹和抑制分层而提供高度可靠的倒装芯片半导体封装，堆积层材料，芯层材料和密封树脂组合物。

公开(公告)号：US07656644B2

公开(公告)日：2010-02-02

申请号：US11972579

申请日：2008-01-10

Applicant: Cengiz A. Palanduz ,  Dustin P. Wood

Inventor： Cengiz A. Palanduz ,  Dustin P. Wood

IPC: H01G4/228

CPC classification number: H05K1/162 ,  H01G4/1209 ,  H01G4/20 ,  H01G4/33 ,  H01L2224/16225 ,  H05K1/0306 ,  H05K1/097 ,  H05K3/4629 ,  H05K3/4641 ,  H05K2201/0175 ,  H05K2201/0187 ,  H05K2201/0355 ,  H05K2201/068 ,  H05K2201/09309 ,  H05K2201/0969 ,  H05K2201/10015 ,  H05K2201/10545 ,  Y10T29/435

Abstract: A method including depositing a suspension of a colloid having an amount of nano-particles of a ceramic material on a substrate; and thermally treating the suspension to form a thin film. A method including depositing a plurality of nano-particles of a ceramic material to pre-determined locations across a surface of a substrate; and thermally treating the plurality of nano-particles to form a thin film. A system including a computing device having a microprocessor, the microprocessor coupled to a printed circuit board through a substrate, the substrate having at least one capacitor structure formed on a surface, the capacitor structure having a first electrode, a second electrode, and a ceramic material disposed between the first electrode and the second electrode, wherein the ceramic material has columnar grains.

Abstract translation: 一种方法，包括在衬底上沉积具有一定量的陶瓷材料的纳米颗粒的胶体的悬浮液; 并对悬浮液进行热处理以形成薄膜。 一种方法，包括将陶瓷材料的多个纳米颗粒沉积在衬底的表面上的预定位置; 并对多个纳米颗粒进行热处理以形成薄膜。 一种包括具有微处理器的计算设备的系统，所述微处理器通过衬底耦合到印刷电路板，所述衬底具有形成在表面上的至少一个电容器结构，所述电容器结构具有第一电极，第二电极和陶瓷 设置在第一电极和第二电极之间的材料，其中陶瓷材料具有柱状晶粒。

公开(公告)号：US20090308642A1

公开(公告)日：2009-12-17

申请号：US12503210

申请日：2009-07-15

Applicant: Katsuto MURATA ,  Koshin NAKAI ,  Makoto HAYASHI

Inventor： Katsuto MURATA ,  Koshin NAKAI ,  Makoto HAYASHI

IPC: H05K1/03 ,  C08L63/00 ,  C08K3/36 ,  B32B27/38

CPC classification number: H05K1/0353 ,  C08G2650/56 ,  C08J5/24 ,  C08J2363/00 ,  C08L63/00 ,  C08L71/00 ,  H05K3/4626 ,  H05K3/4652 ,  H05K3/4655 ,  H05K2201/0129 ,  H05K2201/0209 ,  H05K2201/068 ,  Y10T428/31511 ,  C08L2666/22

Abstract: A thermosetting resin composition contains, as essential components, (A) an epoxy resin having at least two epoxy groups in its molecule, (B) a thermoplastic polyhydroxy polyether resin having a fluorene skeleton, (C) an epoxy curing agent, and (D) a filler. A dry film is obtained by forming a thin film of the thermosetting resin composition on a supporting base film, and a prepreg is obtained by coating and/or impregnating a sheet-like fibrous base material with the thermosetting resin composition. Since they exhibit excellent adhesiveness to a substrate or a conductor and a cured film of the thermosetting resin composition has a relatively low thermal expansion coefficient and a high glass transition point and exhibits high resistance to heat and the capability of being roughened by a roughening treatment, they are useful as a resin insulating layer of a multilayer printed circuit board.

Abstract translation: 热固性树脂组合物含有：（A）分子中具有至少两个环氧基的环氧树脂，（B）具有芴骨架的热塑性多羟基聚醚树脂，（C）环氧固化剂，（D） ）填料。 通过在支撑基底膜上形成热固性树脂组合物的薄膜而获得干膜，并且通过用热固性树脂组合物涂布和/或浸渍片状纤维基材获得预浸料。 由于它们对基材或导体表现出优异的粘附性，并且热固性树脂组合物的固化膜具有相对较低的热膨胀系数和高的玻璃化转变点，并且表现出高的耐热性和通过粗糙化处理而变得粗糙的能力， 它们可用作多层印刷电路板的树脂绝缘层。

公开(公告)号：US20090273073A1

公开(公告)日：2009-11-05

申请号：US12309110

申请日：2008-03-28

Applicant: Kenya Tachibana ,  Masahiro Wada ,  Takuya Hatao

Inventor： Kenya Tachibana ,  Masahiro Wada ,  Takuya Hatao

IPC: H01L23/498 ,  H05K1/16 ,  C08G65/04 ,  C08G65/38 ,  C08G18/00 ,  C08G73/06 ,  C08G73/10 ,  C08G61/08 ,  C08G73/14

CPC classification number: H05K1/0271 ,  H01L21/563 ,  H01L23/293 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/16 ,  H01L2224/73203 ,  H01L2224/81801 ,  H01L2924/01004 ,  H01L2924/01012 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/10253 ,  H05K3/305 ,  H05K3/4602 ,  H05K2201/068 ,  H05K2201/10674 ,  H05K2201/10977 ,  H01L2924/00

Abstract: The invention provides a connecting structure for a flip-chip semiconductor package in which cracking and delamination are inhibited or reduced to improve reliability, and in which the potential range of designs is expanded for the inner circuitry of circuit boards and the inductance is reduced. The invention is a connecting structure for a flip-chip semiconductor package, including: a circuit board having a core layer and at least one build-up layer; a semiconductor element connected via metal bumps to the circuit board; and a sealing resin composition with which gaps between the semiconductor element and circuit board are filled, wherein a cured product of the sealing resin composition has a glass transition temperature between 60° C. and 150° C. and a coefficient of linear expansion from room temperature to the glass transition temperature being between 15 ppm/° C. and 35 ppm/° C., a cured product of the build-up layer has a the glass transition temperature of at least 170° C. and a coefficient of linear expansion in the in-plane direction up to the glass transition temperature being not more than 40 ppm/° C., and stacked vias are provided in the build-up layer on at least one side of the core layer.

Abstract translation: 本发明提供了一种用于倒装芯片半导体封装的连接结构，其中抑制或减少裂纹和分层以提高可靠性，并且其中电路板的内部电路扩展了设计的电位范围并且减小了电感。 本发明是用于倒装芯片半导体封装的连接结构，包括：具有芯层和至少一个堆积层的电路板; 通过金属凸块连接到电路板的半导体元件; 以及密封树脂组合物，其中填充有半导体元件和电路板之间的间隙，其中密封树脂组合物的固化产物的玻璃化转变温度为60℃至150℃，并且室内线性膨胀系数 温度至玻璃化转变温度在15ppm /℃至35ppm /℃之间，积聚层的固化产物的玻璃化转变温度至少为170℃，线膨胀系数 在面内方向直到玻璃化转变温度为40ppm /℃以下，堆积通孔设置在芯层的至少一侧上的堆积层中。

公开(公告)号：US20090233047A1

公开(公告)日：2009-09-17

申请号：US12474239

申请日：2009-05-28

Applicant: A. Cengiz Palanduz

Inventor： A. Cengiz Palanduz

IPC: B32B3/10

CPC classification number: H05K1/0271 ,  H01L21/4857 ,  H01L23/15 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/15312 ,  H05K1/0306 ,  H05K1/0313 ,  H05K3/4626 ,  H05K3/4688 ,  H05K2201/068 ,  H05K2201/10674 ,  Y10T29/49155 ,  Y10T428/24273 ,  Y10T428/24322 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A substrate and a method of making a substrate having a functionally gradient coefficient of thermal expansion are described herein. A system having a silicon die, an organic package substrate, and a substrate having a functionally gradient coefficient of thermal expansion, connecting the silicon die and the organic substrate is also described. The coefficient of thermal expansion at the upper surface of the substrate matches the coefficient of thermal expansion of the die, the coefficient of thermal expansion at the lower surface of the substrate matches the coefficient of thermal expansion of the package substrate, and the substrate has one or more coefficients of thermal expansion between the coefficients of thermal expansion of the upper and lower surfaces.

Abstract translation: 本文描述了基板和制造具有功能梯度热膨胀系数的基板的方法。 还描述了具有硅管芯，有机封装衬底和具有功能梯度的热膨胀系数的衬底，连接硅管芯和有机衬底的系统。 衬底上表面的热膨胀系数与管芯的热膨胀系数相匹配，衬底的下表面的热膨胀系数与封装衬底的热膨胀系数相匹配，并且衬底具有一个 或更高的上表面和下表面的热膨胀系数之间的热膨胀系数。

公开(公告)号：US20090218118A1

公开(公告)日：2009-09-03

申请号：US12393663

申请日：2009-02-26

Applicant: Motoaki TANI

Inventor： Motoaki TANI

IPC: H05K1/18 ,  H05K3/30

CPC classification number: H05K1/186 ,  H01L23/5389 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/83102 ,  H01L2224/92125 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12044 ,  H05K1/0366 ,  H05K3/429 ,  H05K3/4641 ,  H05K3/4652 ,  H05K2201/0323 ,  H05K2201/068 ,  H05K2201/10674 ,  H05K2203/063 ,  Y10T29/4913 ,  H01L2224/05599

Abstract: A board includes a core board, an electronic component arranged on the core board, and an intermediate layer that includes resin containing carbon fibers and that surrounds the electronic component from the side.

Abstract translation: 板包括芯板，布置在芯板上的电子部件和包含碳纤维的树脂并且从侧面包围电子部件的中间层。

公开(公告)号：US07566834B2

公开(公告)日：2009-07-28

申请号：US12140041

申请日：2008-06-16

Applicant: Tadanori Shimoto ,  Katsumi Kikuchi ,  Hideya Murai ,  Kazuhiro Baba ,  Hirokazu Honda ,  Keiichiro Kata

Inventor： Tadanori Shimoto ,  Katsumi Kikuchi ,  Hideya Murai ,  Kazuhiro Baba ,  Hirokazu Honda ,  Keiichiro Kata

IPC: H05K1/00

CPC classification number: H01L23/49816 ,  H01L21/4857 ,  H01L21/6835 ,  H01L23/145 ,  H01L23/49822 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L2221/68345 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/32014 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/83102 ,  H01L2224/92125 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06586 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/3011 ,  H05K1/0366 ,  H05K3/205 ,  H05K3/423 ,  H05K2201/0376 ,  H05K2201/068 ,  H05K2203/0733 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A wiring board has a base insulating film. The base insulating film has a thickness of 20 to 100 μm and is made of a heat-resistant resin which has a glass-transition temperature of 150° C. or higher and which contains reinforcing fibers made of glass or aramid. The base insulating film has the following physical properties (1) to (6) when an elastic modulus at a temperature of T° C. is given as DT (GPa) and a breaking strength at a temperature of T° C. is given as HT (MPa). (1) A coefficient of thermal expansion in the direction of thickness thereof is 90 ppm/K or less. (2) D23≧5 (3) D150≧2.5 (4) (D−65/D150)≦3.0 (5) H23≧140 (6) (H−65/H150)≦2.3.

Abstract translation: 布线板具有基底绝缘膜。 基底绝缘膜的厚度为20〜100μm，由玻璃化转变温度为150℃以上的含有玻璃或芳族聚酰胺的增强纤维的耐热性树脂构成。 当T℃温度下的弹性模量为DT（GPa）时，基体绝缘膜具有以下物理性质（1）〜（6）），在温度T℃下的断裂强度为 HT（MPa）。 （1）其厚度方向的热膨胀系数为90ppm / K以下。 （2）D23> = 5（3）D150> = 2.5（4）（D-65 / D150）<= 3.0（5）H23> = 140（6）（H-65 / H150）<= 2.3。

公开(公告)号：US20090178835A1

公开(公告)日：2009-07-16

申请号：US12318475

申请日：2008-12-30

Applicant: Shinji Matsuda

Inventor： Shinji Matsuda

IPC: H05K1/18

CPC classification number: H01L23/49833 ,  H01L23/13 ,  H01L23/49816 ,  H01L23/49827 ,  H01L2224/16 ,  H01L2924/00013 ,  H01L2924/00014 ,  H05K1/0203 ,  H05K1/0271 ,  H05K1/141 ,  H05K3/3436 ,  H05K2201/0116 ,  H05K2201/0195 ,  H05K2201/049 ,  H05K2201/068 ,  H05K2201/09063 ,  H05K2201/09781 ,  H05K2201/10378 ,  H05K2201/10734 ,  H05K2201/2036 ,  H05K2203/167 ,  Y02P70/613 ,  H01L2224/29099 ,  H01L2224/0401

Abstract: Conductive or solder bumps are stacked between a mounted component such as a BGA device and a printed wiring substrate in a multileveled printed circuit board unit. An interposer or relay substrate is interposed between the adjacent stacked conductive bumps. The interposer substrate is made of a porous material. When any difference in the expansion is caused between the printed wiring substrate and the mounted component, one side of the interposer substrate receives a relatively smaller displacement force while the other side of the interposer substrate receives a relatively larger displacement force. A shearing stress is induced in the interposer substrate. Deformation of the porous material serves to absorb the shearing stress in the interposer substrate. The conductive bumps bonded on one side of the interposer substrate as well as the conductive bumps bonded on the other side of the interposer substrate may be relieved from a shearing stress. Accordingly, the durability of the conductive bumps can be improved. The conductive bumps are allowed to keep a stronger bonding in a longer duration.

公开(公告)号：US20090178832A1

公开(公告)日：2009-07-16

申请号：US12353357

申请日：2009-01-14

Applicant: Satoru Amou ,  Hiroshi Shimizu ,  Akinori Hanawa

Inventor： Satoru Amou ,  Hiroshi Shimizu ,  Akinori Hanawa

IPC: H05K1/03 ,  B32B27/04

CPC classification number: H05K1/0366 ,  B32B3/08 ,  B32B3/18 ,  B32B5/022 ,  B32B5/024 ,  B32B15/02 ,  B32B15/14 ,  B32B15/20 ,  B32B17/02 ,  B32B2260/021 ,  B32B2260/046 ,  B32B2262/0253 ,  B32B2262/101 ,  B32B2307/202 ,  B32B2307/204 ,  B32B2307/306 ,  B32B2307/714 ,  B32B2457/00 ,  B32B2457/04 ,  B32B2457/08 ,  H05K3/4069 ,  H05K3/4652 ,  H05K2201/012 ,  H05K2201/0133 ,  H05K2201/0278 ,  H05K2201/068 ,  Y10T442/2475

Abstract: A prepreg comprising composite woven cloth or non-woven cloth composed of glass fiber and polyolefin fiber that are a main part of the cloth and a thermosetting resin composition that gives a cured product having a low thermal expansion coefficient, wherein the thermal expansion coefficient of the cured resin composition at 50 to 100 ° C. is 50 ppm/° C. or less. A printed circuit board, multi layered circuit board, and electronic part are disclosed.

Abstract translation: 包含作为布的主要部分的由玻璃纤维和聚烯烃纤维组成的复合织布或无纺布的预浸料，以及提供具有低热膨胀系数的固化产物的热固性树脂组合物，其中， 50〜100℃的固化树脂组合物为50ppm /℃以下。 公开了印刷电路板，多层电路板和电子部件。

公开(公告)号：US20090173426A1

公开(公告)日：2009-07-09

申请号：US12380617

申请日：2009-03-02

Applicant: Robert M. Japp ,  Voya R. Markovich ,  Kostas I. Papathomas ,  Mark D. Poliks

Inventor： Robert M. Japp ,  Voya R. Markovich ,  Kostas I. Papathomas ,  Mark D. Poliks

IPC: B32B37/12 ,  B44C1/22

CPC classification number: H01L23/145 ,  H01L23/3733 ,  H01L23/3735 ,  H01L23/4922 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/564 ,  H01L2924/0002 ,  H01L2924/12044 ,  H05K1/0366 ,  H05K1/0373 ,  H05K3/4602 ,  H05K3/4626 ,  H05K3/4652 ,  H05K3/4655 ,  H05K3/4688 ,  H05K2201/0209 ,  H05K2201/0278 ,  H05K2201/068 ,  Y10T29/4913 ,  Y10T156/10 ,  H01L2924/00

Abstract: A multilayered circuitized substrate including a plurality of dielectric layers each comprised of a p-aramid paper impregnated with a halogen-free, low moisture absorptivity resin including an inorganic filler but not including continuous or semi-continuous fiberglass fibers as part thereof, and a first circuitized layer positioned on a first of the dielectric layers. A method of making this substrate is also provided.

Abstract translation: 一种多层电路化基板，包括多个介电层，每个电介质层由浸渍有不含卤素的低吸湿性树脂的对芳族聚酰胺纸构成，所述不含卤素的低吸湿性树脂包括无机填料，但不包括连续或半连续的玻璃纤维作为其一部分， 电路层位于第一介电层上。 还提供了制造该基板的方法。