公开(公告)号：US08964400B2

公开(公告)日：2015-02-24

申请号：US14210697

申请日：2014-03-14

Applicant: SMA Solar Technology AG

Inventor： Regine Mallwitz

IPC: H05K1/18 ,  H01L23/66 ,  H02M7/00 ,  H05K1/02 ,  H05K1/16

CPC classification number: H05K1/181 ,  H01L23/66 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2924/3011 ,  H02M7/003 ,  H05K1/0228 ,  H05K1/0234 ,  H05K1/0263 ,  H05K1/165 ,  H05K2201/0723 ,  H05K2201/0792 ,  H05K2201/083 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A circuitry arrangement includes several electronic parts mounted to a circuit board, at least one conductor section extending between the electronic parts within a first conductor layer, and a closed conductor loop comprising at least one loop section running in parallel to the at least one conductor section within a second conductor layer neighboring the first conductor layer. The closed conductor loop is configured to reduce a tendency towards oscillations of a current flowing through the conductor section in operation of the circuitry arrangement. The conductor loop is closed via at least one electronic component mounted to an outer surface of the circuit board.

Abstract translation: 电路装置包括安装到电路板的几个电子部件，在第一导体层内的电子部件之间延伸的至少一个导体部分和闭合导体回路，该闭合导体回路包括至少一个与至少一个导体部分平行运行的回路部分 在与第一导体层相邻的第二导体层内。 闭合导体环路被配置为在电路装置的操作中减小流过导体部分的电流的振荡趋势。 通过安装到电路板的外表面的至少一个电子部件来闭合导体环路。

公开(公告)号：US20140353022A1

公开(公告)日：2014-12-04

申请号：US14290193

申请日：2014-05-29

Applicant: IBIDEN CO., LTD.

Inventor： Haruhiko MORITA

IPC: H05K1/02 ,  H05K1/18

CPC classification number: H05K1/165 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/15311 ,  H01L2924/3511 ,  H05K1/0225 ,  H05K1/0366 ,  H05K1/116 ,  H05K3/244 ,  H05K3/4602 ,  H05K2201/0191 ,  H05K2201/0293 ,  H05K2201/0347 ,  H05K2201/0723 ,  H05K2201/0792 ,  H05K2201/09136 ,  H05K2201/09263 ,  H05K2201/09454 ,  H05K2201/09527 ,  H05K2201/096 ,  H05K2201/09672 ,  H05K2201/09836

Abstract: A wiring board includes a substrate having a laminated-inductor forming portion and including multiple first insulation layers and a second insulation layer formed on a first side of the first insulation layers such that the first insulation layers have the laminated-inductor forming portion, and a planar conductor formed on the second insulation layer of the substrate and formed to shield electromagnetic force generated from the laminated-inductor forming portion of the substrate. The laminated-inductor forming portion of the substrate has multiple inductor patterns formed on the first insulation layers and multiple via conductors connecting the inductor patterns through the first insulation layers, and the inductor patterns include an uppermost inductor pattern formed between the second insulation layer and the first insulation layers such that the uppermost inductor pattern has a distance of 100 μm or more from the planar conductor.

Abstract translation: 布线基板包括具有层叠电感器形成部分并且包括多个第一绝缘层的基板和形成在第一绝缘层的第一侧上的第二绝缘层，使得第一绝缘层具有层叠电感器形成部分，以及 形成在基板的第二绝缘层上并形成以屏蔽从基板的层叠电感器形成部分产生的电磁力的平面导体。 衬底的层叠电感器形成部分具有形成在第一绝缘层上的多个电感器图案和通过第一绝缘层连接电感器图案的多个通孔导体，并且电感器图案包括形成在第二绝缘层和 第一绝缘层，使得最上层的电感器图案与平面导体的距离为100μm以上。

公开(公告)号：US20140049929A1

公开(公告)日：2014-02-20

申请号：US13960469

申请日：2013-08-06

Applicant: Canon Kabushiki Kaisha

Inventor： Hiroyuki Yamaguchi

IPC: H05K1/02

CPC classification number: H05K1/0216 ,  H05K1/0231 ,  H05K1/0233 ,  H05K1/0245 ,  H05K2201/0792 ,  H05K2201/09272 ,  H05K2201/09418 ,  H05K2201/10522 ,  H05K2201/10636 ,  Y02P70/611

Abstract: A filter circuit 103 includes capacitor elements 121 and 122. The capacitor element 121 returns a common mode current included in a signal output from, a signal output terminal 111 of a semiconductor element 102, to a ground terminal 113 of the semiconductor element 102. The capacitor element 122 returns a common mode current included in a signal output from a signal output terminal 112 of the semiconductor element 102, to the ground terminal 113 of the Semiconductor element 102. The capacitor elements 121 and 122 are arranged such that the mutual inductance between a parasitic inductance of the capacitor element 121 and a parasitic inductance of the capacitor element 122 for the common mode currents is a negative value. Accordingly, the effective inductances of the first and second capacitor elements for the common mode currents are reduced, which suppresses radiation noise.

Abstract translation: 滤波器电路103包括电容器元件121和122.电容器元件121将包括在从半导体元件102的信号输出端子111输出的信号中的共模电流返回到半导体元件102的接地端子113。 电容器元件122将包括在从半导体元件102的信号输出端子112输出的信号中的共模电流返回到半导体元件102的接地端子113.电容器元件121和122被布置成使得 电容器元件121的寄生电感和用于共模电流的电容器元件122的寄生电感为负值。 因此，减小了用于共模电流的第一和第二电容器元件的有效电感，这抑制了辐射噪声。

公开(公告)号：US20130334677A1

公开(公告)日：2013-12-19

申请号：US13517654

申请日：2012-06-14

Applicant: Ralf Otremba ,  Davide Chiola ,  Erich Griebl ,  Fabio Brucchi

Inventor： Ralf Otremba ,  Davide Chiola ,  Erich Griebl ,  Fabio Brucchi

IPC: H01L23/495 ,  H01L21/56 ,  H01L23/34

CPC classification number: H01L23/49562 ,  H01L21/565 ,  H01L23/3107 ,  H01L23/36 ,  H01L23/4952 ,  H01L24/06 ,  H01L24/48 ,  H01L24/49 ,  H01L25/11 ,  H01L2224/04042 ,  H01L2224/0603 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48464 ,  H01L2224/4903 ,  H01L2924/00014 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/181 ,  H05K1/0296 ,  H05K3/308 ,  H05K2201/0792 ,  H05K2201/10166 ,  H05K2201/10522 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/00012

Abstract: In accordance with an embodiment of the present invention, a semiconductor module includes a first semiconductor device having a first plurality of leads including a first gate/base lead, a first drain/collector lead, and a first source/emitter lead. The module further includes a second semiconductor device and a circuit board. The second semiconductor device has a second plurality of leads including a second gate/base lead, a second drain/collector lead, and a second source/emitter lead. The circuit board has a plurality of mounting holes, wherein each of the first plurality of leads and the second plurality of leads is mounted into a respective one of the plurality of mounting holes. At the plurality of mounting holes, a first distance from the first gate/base lead to the second gate/base lead is different from a second distance from the first source/emitter lead to the second source/emitter lead.

Abstract translation: 根据本发明的实施例，半导体模块包括具有包括第一栅极/基极引线，第一漏极/集电极引线和第一源极/发射极引线的第一多个引线的第一半导体器件。 该模块还包括第二半导体器件和电路板。 第二半导体器件具有包括第二栅极/基极引线，第二漏极/集电极引线和第二源极/发射极引线的第二多个引线。 电路板具有多个安装孔，其中第一多个引线和第二多个引线中的每一个安装到多个安装孔中的相应一个安装孔中。 在多个安装孔处，从第一栅极/基极引线到第二栅极/基极引线的第一距离与从第一源极/发射极引线到第二源极/发射极引线的第二距离不同。

公开(公告)号：US20130248236A1

公开(公告)日：2013-09-26

申请号：US13895675

申请日：2013-05-16

Applicant: International Business Machines Corporation

Inventor： Bhyrav M. Mutnury ,  Nam H. Pham ,  Terence Rodrigues

IPC: H05K3/42 ,  H05K1/11

CPC classification number: H05K3/42 ,  H05K1/024 ,  H05K1/0251 ,  H05K1/115 ,  H05K2201/0792 ,  H05K2201/09063 ,  Y10T29/49165

Abstract: A circuit board includes layers, a pair of vias filled with a conductive material and extending through the layers, first and second pairs of conductive signal paths, and holes extending at least partially through the layers and located between the pair of vias. The first pair of conductive paths is connected to the pair of vias within a first layer; the second pair of conductive paths is connected to the pair of vias within a second layer. The pair of vias has a pair of via stubs defined between the second layer and a bottom layer. A differential signal is to be transmitted between the first and second pairs of conductive signal paths via the pair of vias. The holes have a lower dielectric constant than the layers to increase a resonant frequency of the pair of via stubs beyond the frequency of the differential signal.

Abstract translation: 电路板包括层，填充有导电材料并延伸通过层的一对通孔，第一和第二对导电信号路径，以及至少部分延伸通过层并且位于该对通孔之间的孔。 第一对导电路径连接到第一层内的一对通孔; 第二对导电路径连接到第二层内的一对通孔。 一对通孔具有限定在第二层和底层之间的一对通孔短截线。 差分信号将经由一对通孔在第一和第二对导电信号路径之间传输。 这些孔具有比层更低的介电常数，以增加一对通孔短路的谐振频率超过差分信号的频率。

公开(公告)号：US08542494B2

公开(公告)日：2013-09-24

申请号：US12770691

申请日：2010-04-29

Applicant: Bhyrav M. Mutnury ,  Nam H. Pham ,  Terence Rodrigues

Inventor： Bhyrav M. Mutnury ,  Nam H. Pham ,  Terence Rodrigues

IPC: H05K1/00 ,  H05K1/18 ,  H05K7/00

CPC classification number: H05K3/42 ,  H05K1/024 ,  H05K1/0251 ,  H05K1/115 ,  H05K2201/0792 ,  H05K2201/09063 ,  Y10T29/49165

Abstract: A circuit board includes layers, a pair of vias filled with a conductive material and extending through the layers, first and second pairs of conductive signal paths, and holes extending at least partially through the layers and located between the pair of vias. The first pair of conductive paths is connected to the pair of vias within a first layer; the second pair of conductive paths is connected to the pair of vias within a second layer. The pair of vias has a pair of via stubs defined between the second layer and a bottom layer. A differential signal is to be transmitted between the first and second pairs of conductive signal paths via the pair of vias. The holes have a lower dielectric constant than the layers to increase a resonant frequency of the pair of via stubs beyond the frequency of the differential signal.

公开(公告)号：US08035036B2

公开(公告)日：2011-10-11

申请号：US11861297

申请日：2007-09-26

Applicant: Uei-Ming Jow ,  Min-Lin Lee ,  Shinn-Juh Lay ,  Chin-Sun Shyu ,  Chang-Sheng Chen ,  Ying-Jiunn Lai

Inventor： Uei-Ming Jow ,  Min-Lin Lee ,  Shinn-Juh Lay ,  Chin-Sun Shyu ,  Chang-Sheng Chen ,  Ying-Jiunn Lai

IPC: H05K1/16

CPC classification number: H05K1/167 ,  H05K1/0224 ,  H05K1/025 ,  H05K1/0298 ,  H05K2201/0792 ,  H05K2201/09681 ,  H05K2201/0969

Abstract: A complementary mirror image embedded planar resistor architecture is provided. In the architecture, a complementary hollow structure is formed on a ground plane or an electrode plane to minimize the parasitic resistance, so as to efficiently enhance the application frequency. In addition, in some cases, some signal transmission lines pass through the position below the embedded planar resistor, and if there is no shield at all, serious interference or cross talk phenomenon occurs. Therefore, the complementary hollow structure of the ground plane, the electrode plane, or a power layer adjacent to the embedded planar resistor is designed to be a mesh structure, so as to reduce the interference or cross talk phenomenon. In this manner, the whole resistor structure has preferable high frequency electrical characteristic in the circuit.

Abstract translation: 提供了一种互补镜像嵌入式平面电阻架构。 在该结构中，在接地平面或电极平面上形成互补的中空结构以最小化寄生电阻，从而有效地提高施加频率。 此外，在某些情况下，一些信号传输线通过嵌入式平面电阻器下方的位置，如果根本没有屏蔽，则会发生严重的干扰或串扰现象。 因此，将接地平面，电极平面或与嵌入式平面电阻器相邻的功率层的互补空心结构设计为网格结构，以减少干扰或串扰现象。 以这种方式，整个电阻器结构在电路中具有优选的高频电特性。

公开(公告)号：US20100290331A1

公开(公告)日：2010-11-18

申请号：US12727928

申请日：2010-03-19

Applicant: Yasuhiro KAIZAKI ,  Tetsuro Sawai ,  Sumitoshi Kawasaki

Inventor： Yasuhiro KAIZAKI ,  Tetsuro Sawai ,  Sumitoshi Kawasaki

IPC: G11B7/00 ,  H05K1/00

CPC classification number: G11B7/126 ,  H05K1/025 ,  H05K1/144 ,  H05K1/147 ,  H05K2201/0792

Abstract: A signal current wiring line is configured to carry a signal current from a first circuit block to a second circuit block. A return current wiring line is configured to carry a return current from the second circuit block to the first circuit block. The signal current wiring line and the return current wiring line are stacked with an offset in the width direction so as to form a region between the surface of the casing on the second wiring line side and the signal current wiring line where the signal current wiring line faces the surface of the casing on the second wiring line side without the return current wiring line intervening between them.

Abstract translation: 信号电流布线被配置为将信号电流从第一电路块传送到第二电路块。 返回电流布线被配置为承载从第二电路块到第一电路块的返回电流。 信号电流布线和回流布线在宽度方向上以偏移方式堆叠，以形成第二布线侧的壳体的表面与信号电流布线之间的区域 面对第二布线侧的壳体的表面，而不会在它们之间插入返回电流布线。

公开(公告)号：US07778040B2

公开(公告)日：2010-08-17

申请号：US11644892

申请日：2006-12-26

Applicant: Seung-young Ahn

Inventor： Seung-young Ahn

IPC: H05K7/10

CPC classification number: H05K1/0231 ,  H01P5/028 ,  H05K1/0233 ,  H05K1/0239 ,  H05K1/025 ,  H05K1/111 ,  H05K1/165 ,  H05K2201/0792 ,  H05K2201/09727 ,  H05K2201/10636 ,  Y02P70/611

Abstract: A printed circuit board assembly includes: a substrate; a main signal line formed on the substrate to transmit a signal; an SMD mounted on the substrate; a pad interposed between the SMD and the substrate; and a sub signal line provided on the substrate to electrically connect the main signal line with the pad, and having a width different from that of the main signal line. Thus, the printed circuit board assembly transmits a signal at a high speed and enhancing reliability and an economical efficiency of a product using the printed circuit board assembly.

Abstract translation: 印刷电路板组件包括：基板; 形成在基板上以传送信号的主信号线; 安装在基板上的SMD; 夹在SMD和衬底之间的衬垫; 以及设置在所述基板上的子信号线，以将所述主信号线与所述焊盘电连接，并且具有与所述主信号线的宽度不同的宽度。 因此，印刷电路板组件以高速度传输信号，并提高使用印刷电路板组件的产品的可靠性和经济效率。

公开(公告)号：US07773389B2

公开(公告)日：2010-08-10

申请号：US11080672

申请日：2005-03-16

Applicant: Hiroki Katayama ,  Yoshiaki Ishigami

Inventor： Hiroki Katayama ,  Yoshiaki Ishigami

IPC: H05K7/00

CPC classification number: H05K3/3442 ,  H05K1/0239 ,  H05K1/025 ,  H05K1/0253 ,  H05K1/181 ,  H05K2201/0792 ,  H05K2201/09072 ,  H05K2201/093 ,  H05K2201/0969 ,  H05K2201/10022 ,  H05K2201/1003 ,  H05K2201/10121 ,  H05K2201/10484 ,  H05K2201/10515 ,  H05K2201/1053 ,  H05K2201/10636 ,  H05K2201/10984 ,  H05K2201/2036 ,  Y02P70/611 ,  Y02P70/613

Abstract: An electronic component mounted structure has: a circuit board; two semiconductor elements that are mounted on the circuit board; and an AC coupling capacitor that is operable to cut off signals with a predetermined frequency or less and is provided between the two semiconductor elements. The AC coupling capacitor is mounted on the circuit board such that a part or a whole of the AC coupling capacitor is away from the surface of the circuit board.

Abstract translation: 电子部件安装结构具有：电路板; 安装在电路板上的两个半导体元件; 以及AC耦合电容器，其可操作以以预定频率或更小的频率切断信号，并且设置在两个半导体元件之间。 AC耦合电容器安装在电路板上，使得AC耦合电容器的一部分或全部远离电路板的表面。