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    Gap-coupling bus system
    121.
    发明授权
    Gap-coupling bus system 有权
    间隙耦合总线系统

    公开(公告)号：US06600790B1

    公开(公告)日：2003-07-29

    申请号：US09297359

    申请日：1999-04-30

    Applicant: Masaya Umemura ,  Hideki Osaka

    Inventor： Masaya Umemura ,  Hideki Osaka

    IPC: H04B300

    CPC classification number: G06F13/4072 ,  H05K1/0228 ,  H05K1/023 ,  H05K1/0245 ,  H05K2201/09263 ,  H05K2201/097 ,  H05K2201/10022

    Abstract: There is provided a gap coupling type bus system, which makes it possible to mutually transfer data between all the modules connected to the bus. The gap coupling type bus system comprises for at least three modules, each module being provided with at least one sending/receiving circuit for sending and receiving a signal: at least three signal lines (21-26) respectively connected to the at least three modules (11-16); and terminating resistors (31-36) connected to respective signal lines at the other ends of the signal lines, each terminating resistor having generally same value as characteristic impedance of the signal line. Those at least three signal lines (21-26) have portions (1-2, 1-3, 2-3, . . . ) laid in parallel with one another with a predetermined gap, correspondingly to every combination of different two modules out of those at least three modules (11-16).

    Abstract translation: 提供了一种间隙耦合型总线系统，这使得可以在连接到总线的所有模块之间相互传送数据。 间隙耦合型总线系统包括至少三个模块，每个模块设置有至少一个用于发送和接收信号的发送/接收电路：至少三个信号线（21-26），分别连接到至少三个模块 （11-16）; 以及连接到信号线的另一端的相应信号线的端接电阻器（31-36），每个终端电阻器具有与信号线的特征阻抗大致相同的值。 那些至少三条信号线（21-26）具有以预定间隙彼此平行放置的部分（1-2,1-3,3-3 ...），对应于不同的两个模块的每个组合 至少有三个模块（11-16）。

    EQUIPOTENTIAL FAULT TOLERANT INTEGRATED CIRCUIT HEATER
    124.
    发明申请
    EQUIPOTENTIAL FAULT TOLERANT INTEGRATED CIRCUIT HEATER 失效
    等离子体容错集成电路加热器

    公开(公告)号：US20020170901A1

    公开(公告)日：2002-11-21

    申请号：US09860872

    申请日：2001-05-18

    Inventor： James C. Lau

    IPC: H05B003/00

    CPC classification number: H05K7/20 ,  H01L23/345 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/15311 ,  H05K1/0212 ,  H05K1/0306 ,  H05K1/141 ,  H05K1/167 ,  H05K3/3494 ,  H05K3/368 ,  H05K3/4611 ,  H05K3/4629 ,  H05K2201/09263 ,  H05K2201/09681 ,  H05K2203/1115 ,  H05K2203/176 ,  H01L2924/00014

    Abstract: Fault tolerance is incorporated within the integral electric heaters of a reworkable electronic semiconductor component, such as a reworkable multi-chip module, to increase production yield and longevity of the rework feature. Components of the foregoing kind contain a multilayer substrate to bond to a printed wiring board, and, for rework, the component includes a plurality of electric heaters arranged side by side on a bottom layer of the substrate. When energized with current, the heaters generate sufficient heat to weaken the adhesive or solder bond to the printed wiring board without delaminating the layers of the substrate, allowing the electronic semiconductor component to be pulled away from the printed wiring board for rework. Additional circuitry is included to automatically route heater current around, that is bypass, any current-interrupting break(s) as may form in any of the electric heaters giving the heaters a fault tolerance.

    Abstract translation: 容错功能被集成在可再加工的电子半导体部件（例如可再加工的多芯片模块）的整体式电加热器内，以提高返工特征的生产成本和寿命。 上述类型的组件包含多个基板以与印刷电路板接合，并且为了返工，该部件包括并排布置在基板的底层上的多个电加热器。 当用电流通电时，加热器产生足够的热量以削弱与印刷线路板的粘合剂或焊料结合，而不会使基板的层分层，允许将电子半导体部件从印刷线路板拉出以进行返工。 包括额外的电路，用于自动路由加热器电流（旁路），任何电流中断中断可能会在任何电加热器中形成故障容限。

    High capacity memory module with higher density and improved manufacturability
    126.
    发明授权
    High capacity memory module with higher density and improved manufacturability 失效
    高容量内存模块，具有更高的密度和更高的可制造性

    公开(公告)号：US06449166B1

    公开(公告)日：2002-09-10

    申请号：US09645858

    申请日：2000-08-24

    Applicant: Thomas R. Sly ,  Kevin M. Quinn

    Inventor： Thomas R. Sly ,  Kevin M. Quinn

    IPC: H05K702

    CPC classification number: H05K1/0248 ,  G11C5/04 ,  G11C5/063 ,  H01L23/66 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K1/023 ,  H05K1/14 ,  H05K2201/09263 ,  H05K2201/10022 ,  H05K2201/10159 ,  H05K2203/1572 ,  H01L2924/00

    Abstract: The present invention provides a double-sided memory module with improved memory device density and improved manufacturability, and with optional bus terminations mounted directly on the memory module for use with high speed, impedance-controlled memory buses. It also allows the same memory devices to be used on both sides of the card, instead of requiring memory devices with mirrored I/O connections on a second side as on prior art double-sided memory cards. The memory module may be formed on a conventional printed circuit card using cost-effective printed circuit board line widths and spaces with unpacked or packed memory chips attached directly to the memory module, while maintaining good signal integrity. Using memory modules with bus terminations mounted directly on the module improves the signal quality and integrity even further and therefore enhances system performance. Such designs may also eliminate the need for bus exit connections, thereby allowing the freed-up connection capacity to be used to address additional memory capacity on the module.

    Abstract translation: 本发明提供了具有改进的存储器件密度和改进的可制造性的双面存储器模块，并且可选的总线端接件直接安装在存储器模块上，以用于与高速，阻抗控制的存储器总线一起使用。 它还允许在卡的两侧使用相同的存储器件，而不需要象现有技术的双面存储卡那样在第二面上需要具有镜像I / O连接的存储器件。 存储器模块可以使用具有成本效益的印刷电路板线宽度和空间形成在传统印刷电路卡上，所述印刷电路板线宽度和空间具有直接附接到存储器模块的未包装或打包的存储芯片，同时保持良好的信号完整性。 使用直接安装在模块上的总线端子的内存模块可以进一步提高信号质量和完整性，从而提高系统性能。 这样的设计也可以消除对总线出口连接的需要，从而允许自由连接容量用于解决模块上的附加存储器容量。

    Flat flexible cable with ground conductors
    128.
    发明授权
    Flat flexible cable with ground conductors 有权
    带有接地导体的扁平柔性电缆

    公开(公告)号：US06300846B1

    公开(公告)日：2001-10-09

    申请号：US09271538

    申请日：1999-03-18

    Applicant: David L. Brunker

    Inventor： David L. Brunker

    IPC: H01P302

    CPC classification number: H05K1/0228 ,  H01B7/0876 ,  H05K1/0219 ,  H05K1/0245 ,  H05K2201/09263 ,  H05K2201/09672 ,  H05K2201/097

    Abstract: A flexible circuit member includes first and second pseudo-twisted flexible conductors on a flexible dielectric substrate. The first pseudo-twisted conductor is on a first side of the substrate and the second pseudo-twisted conductor is on a second side of the substrate. Each pseudo-twisted conductor includes a periodic pattern with the first pseudo-twisted conductor being shifted longitudinally relative to the second pseudo-twisted conductor by one half of a period of the periodic pattern. A set of first and second additional conductors are also provided on the dielectric substrate. The first additional conductor is on the first side of the substrate and is spaced from and generally follows the shape of the first pseudo-twisted conductor. The second additional conductor is on the second side of the substrate and is spaced from and generally follows the shape of the second pseudo-twisted conductor. These first and second additional conductors may be coupled to reference or ground potential so as to provide a grounding system for the flexible circuit member.

    Abstract translation: 柔性电路部件包括在柔性电介质基板上的第一和第二伪扭绞柔性导体。 第一假捻导体位于衬底的第一侧上，而第二伪扭绞导体位于衬底的第二侧上。 每个假捻导体包括周期性图案，其中第一伪扭绞导体相对于第二假捻导体纵向移动周期图案周期的一半。 一组第一和第二附加导体也设置在电介质基片上。 第一附加导体位于衬底的第一侧上，并且与第一假捻导体的形状间隔开并且大体上遵循该形状。 第二附加导体位于衬底的第二侧上，并且与第二假捻导体的形状间隔开并且大体上遵循第二伪导体的形状。 这些第一和第二附加导体可以耦合到参考电压或地电位，以便为柔性电路构件提供接地系统。

    Method for designing a decoupling circuit
    129.
    发明申请
    Method for designing a decoupling circuit 失效
    设计去耦电路的方法

    公开(公告)号：US20010014963A1

    公开(公告)日：2001-08-16

    申请号：US09729852

    申请日：2000-12-06

    Inventor： Noriaki Ando ,  Hitoshi Irino ,  Hiroshi Wabuka ,  Hirokazu Tohya

    IPC: G06F017/50

    CPC classification number: H05K3/0005 ,  G06F17/5068 ,  H05K1/0231 ,  H05K2201/09263 ,  H05K2201/10689

    Abstract: A method for designing a decoupling circuit for a source line of a LSI includes the steps of determining the capacitance of the decoupling capacitor based on the electric charge necessary for one cycle operation of the LSI and the allowable fluctuation of the source voltage, and determining the inductance of the source line based on the impedance of the decoupling capacitor and the allowable minimum multiplexing ratio of the source current by the decoupling capacitor.

    Abstract translation: 设计用于LSI的源极线的去耦电路的方法包括以下步骤：基于LSI的一个周期操作所需的电荷和源极电压的允许波动来确定去耦电容器的电容，并且确定 基于去耦电容器的阻抗的源极线的电感和去耦电容器的源电流的允许的最小复用比。

    High-frequency bus system
    130.
    发明授权
    High-frequency bus system 失效
    高频总线系统

    公开(公告)号：US06266730B1

    公开(公告)日：2001-07-24

    申请号：US09507303

    申请日：2000-02-18

    Applicant: Donald V. Perino ,  Billy Wayne Garrett, Jr. ,  Haw-Jyh Liaw ,  David Nguyen ,  Srinivas Nimmagadda ,  James A. Gasbarro ,  Richard DeWitt Crisp

    Inventor： Donald V. Perino ,  Billy Wayne Garrett, Jr. ,  Haw-Jyh Liaw ,  David Nguyen ,  Srinivas Nimmagadda ,  James A. Gasbarro ,  Richard DeWitt Crisp

    IPC: H05K102

    CPC classification number: G11C5/063 ,  G06F13/1684 ,  G06F13/4086 ,  G06F13/409 ,  G06F13/4247 ,  G11C5/04 ,  G11C7/1048 ,  H05K1/023 ,  H05K1/0246 ,  H05K1/0248 ,  H05K1/14 ,  H05K7/1459 ,  H05K2201/044 ,  H05K2201/09263 ,  H05K2201/10022 ,  H05K2201/10159 ,  H05K2201/10689

    Abstract: A high frequency bus system which insures uniform arrival times of high-fidelity signals to the devices on the high frequency bus, despite the use of the bus on modules and connectors. A high frequency bus system includes a first bus segment having one or more devices connected between a first and a second end. The first bus segment has at least a pair of transmission lines for propagating high frequency signals and the devices are coupled to the pair of transmission lines. The high frequency bus system also includes a second bus segment which has no devices connected to it. The second bus segment also has at least a pair of transmission lines for propagating high frequency signals. The first end of the first segment and second end of the second segment are coupled in series to form a chain of segments and when two signals are introduced to the first end of the second bus segment at the substantially the same time, they arrive at each device connected to the first bus segment at substantially the same time. Also, when two signals originate at a device connected to the first bus segment at substantially the same time, they arrive at the first end of the second bus segment at substantially the same time. Uniform arrival times hold despite the use of connectors to couple the segments together, despite the segments being located on modules, without the need for stubs, despite the presence of routing turns in the segments and despite the type of information, such as address, data or control, carried by the signals.

    Abstract translation: 尽管在模块和连接器上使用了总线，但高频总线系统确保高保真信号的均匀到达时间到高频总线上的设备。 高频总线系统包括具有连接在第一和第二端之间的一个或多个设备的第一总线段。 第一总线段具有用于传播高频信号的至少一对传输线，并且该装置耦合到该对传输线。 高频总线系统还包括没有与其连接的设备的第二总线段。 第二总线段还具有用于传播高频信号的至少一对传输线。 第二段的第一段和第二端的第一端被串联耦合以形成链段，并且当两个信号在基本相同的时间被引入第二总线段的第一端时，它们到达每一个 设备在大致相同的时间连接到第一总线段。 而且，当两个信号在基本相同的时间起始于连接到第一总线段的设备时，它们在几乎相同的时间到达第二总线段的第一端。 尽管使用连接器将段连接在一起，尽管分段位于模块上，而不需要存根，尽管存在分段中的路由选择，并且尽管信息类型（例如地址，数据）也是均匀到达时间 或控制，由信号携带。

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