公开(公告)号：US20150091145A1

公开(公告)日：2015-04-02

申请号：US14566870

申请日：2014-12-11

Applicant: STATS ChipPAC, Ltd.

Inventor： Yaojian Lin ,  Pandi C. Marimuthu

IPC: H01L21/768 ,  H01L23/498

CPC classification number: H01L21/76829 ,  H01L21/4832 ,  H01L21/486 ,  H01L21/568 ,  H01L21/76879 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49861 ,  H01L23/5389 ,  H01L24/11 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/06182 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/20 ,  H01L2224/2101 ,  H01L2224/211 ,  H01L2224/215 ,  H01L2224/221 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H05K1/185 ,  H05K2201/10674 ,  H01L2924/00014 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00

Abstract: A semiconductor device has a semiconductor die mounted over the carrier. An encapsulant is deposited over the carrier and semiconductor die. The carrier is removed. A first interconnect structure is formed over the encapsulant and a first surface of the die. A second interconnect structure is formed over the encapsulant and a second surface of the die. A first protective layer is formed over the first interconnect structure and second protective layer is formed over the second interconnect structure prior to forming the vias. A plurality of vias is formed through the second interconnect structure, encapsulant, and first interconnect structure. A first conductive layer is formed in the vias to electrically connect the first interconnect structure and second interconnect structure. An insulating layer is formed over the first interconnect structure and second interconnect structure and into the vias. A discrete semiconductor component can be mounted to the first interconnect structure.

Abstract translation: 半导体器件具有安装在载体上的半导体管芯。 封装剂沉积在载体和半导体管芯上。 载体被移除。 在密封剂和模具的第一表面上形成第一互连结构。 在密封剂和模具的第二表面上形成第二互连结构。 在第一互连结构之上形成第一保护层，并且在形成通孔之前在第二互连结构上形成第二保护层。 通过第二互连结构，密封剂和第一互连结构形成多个通孔。 在通孔中形成第一导电层以电连接第一互连结构和第二互连结构。 绝缘层形成在第一互连结构和第二互连结构之上，并且形成在通孔中。 分立半导体部件可以安装到第一互连结构。

公开(公告)号：US20150084211A1

公开(公告)日：2015-03-26

申请号：US14560859

申请日：2014-12-04

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hsien-Wei Chen

IPC: H01L25/10 ,  H01L23/00

CPC classification number: H01L25/105 ,  H01L21/485 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49894 ,  H01L23/5382 ,  H01L23/5383 ,  H01L24/09 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L25/0655 ,  H01L2224/0362 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/08225 ,  H01L2224/09051 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/17051 ,  H01L2224/17515 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/81395 ,  H01L2224/81801 ,  H01L2224/81895 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/19042 ,  H01L2924/19105 ,  H05K1/0295 ,  H05K2201/09954 ,  H05K2201/10674 ,  H01L2924/014 ,  H01L2924/00014

Abstract: A device includes a first package component, and a second package component underlying the first package component. The second package component includes a first electrical connector at a top surface of the second package component, wherein the first electrical connector is bonded to the first package component. The second package component further includes a second electrical connector at the top surface of the second package component, wherein no package component is overlying and bonded to the second electrical connector.

Abstract translation: 一种装置包括第一包装部件和第一包装部件下面的第二包装部件。 第二包装部件包括在第二包装部件的顶表面处的第一电连接器，其中第一电连接器结合到第一包装部件。 第二包装组件还包括在第二包装部件的顶表面处的第二电连接器，其中没有包装部件覆盖并结合到第二电连接器。

公开(公告)号：US08971053B2

公开(公告)日：2015-03-03

申请号：US14160766

申请日：2014-01-22

Applicant: Ibiden Co., Ltd.

Inventor： Takashi Kariya ,  Toshiki Furutani

IPC: H05K1/18 ,  H05K1/02 ,  H01L23/538 ,  H05K3/00 ,  H05K3/46 ,  H01L23/498

CPC classification number: H05K1/0298 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5389 ,  H01L2224/16225 ,  H01L2224/1703 ,  H01L2924/15151 ,  H01L2924/15311 ,  H05K1/181 ,  H05K1/182 ,  H05K3/0047 ,  H05K3/4602 ,  H05K3/4623 ,  H05K3/4644 ,  H05K2201/10159 ,  H05K2201/10363 ,  H05K2201/10522 ,  H05K2201/1053 ,  H05K2201/10674 ,  Y02P70/611 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: A wiring board includes a first substrate having a penetrating hole penetrating through the first substrate, a built-up layer formed on a surface of the first substrate and including interlayer resin insulation layers and wiring layers, the built-up layer having an opening portion communicated with the penetrating hole of the first substrate and opened to the outermost surface of the built-up layer, an interposer accommodated in the opening portion of the built-up layer and including a second substrate and a wiring layer formed on the second substrate, the wiring layer of the interposer including conductive circuits for being connected to semiconductor elements, a filler filling the opening portion such that the interposer is held in the opening portion of the built-up layer, and mounting pads formed on the first substrate and positioned to mount the semiconductor elements. The mounting pads are positioned to form a matrix on the first substrate.

Abstract translation: 布线基板包括具有穿透第一基板的穿透孔的第一基板，形成在第一基板的表面上并且包括层间树脂绝缘层和布线层的积层，所述积层具有连通的开口部 所述第一基板的贯通孔向所述积层的最外表面开口，插入到所述积层的开口部，并且包括形成在所述第二基板上的第二基板和布线层， 所述插入器的布线层包括用于连接到半导体元件的导电电路，填充所述开口部的填充物，使得所述插入件保持在所述积层的开口部中，以及安装焊盘，其形成在所述第一基板上并且被定位成安装 半导体元件 定位安装垫以在第一基板上形成矩阵。

公开(公告)号：US20150016072A1

公开(公告)日：2015-01-15

申请号：US14367611

申请日：2012-12-18

Applicant: TAIYO INK MFG. CO., LTD. ,  Hiroshi IWAYAMA

Inventor： Gento Iwayama ,  Arata Endo ,  Shoji Minegishi ,  Masao Arima

IPC: H05K1/03 ,  H05K3/00 ,  G03F7/40 ,  H05K3/46

CPC classification number: H05K1/0353 ,  B32B27/08 ,  B32B27/16 ,  B32B27/20 ,  B32B2264/102 ,  B32B2264/104 ,  B32B2307/202 ,  B32B2307/206 ,  B32B2457/08 ,  G03F7/40 ,  H01L21/563 ,  H01L23/49816 ,  H01L23/49894 ,  H01L2224/73204 ,  H01L2224/92125 ,  H05K1/036 ,  H05K1/0373 ,  H05K3/0082 ,  H05K3/281 ,  H05K3/3436 ,  H05K3/4611 ,  H05K2201/0195 ,  H05K2201/10674 ,  H05K2201/10977 ,  Y10T428/24975 ,  Y10T428/31515

Abstract: The present invention provides a dry film capable of forming a cured coating film having an excellent laser processability and a desmear resistance, and a printed writing board using the same. Further, the present invention provides a method of producing a printed writing board for a flip-chip mounting substrate capable of simply and inexpensively forming a dam preventing from spreading an underfill, a printed writing board obtained by the method of producing, and a flip-chip mounting substrate in which a chip is subjected to flip chip mounting on the printed writing board.A dry film comprising: a carrier film and a photocurable resin composition layer (L1) formed by applying and drying a photocurable resin composition; and at least a thermosetting resin composition layer (L2) formed by applying and drying a thermosetting resin composition in a gap between the photocurable resin composition layer (L1) and the carrier film. A method of producing a printed writing board comprising: a process in which a resin insulation layer which includes a thermosetting resin composition layer (L2) and a photocurable resin composition layer (L1) in order from a side of a substrate surface is formed on the substrate surface; a process to perform patterning by photolithographic approach; and a process to perform patterning by laser processing.

Abstract translation: 本发明提供能够形成具有优异的激光加工性和耐去污性的固化涂膜的干膜和使用该干膜的印刷书写板。 此外，本发明提供了一种制造用于倒装芯片安装基板的印刷书写板的方法，其能够简单且廉价地形成防止扩散底部填充物的防止堤坝，通过制造方法获得的印刷书写板， 芯片安装基板，其中芯片经过倒装芯片安装在印刷的书写板上。 1.一种干膜，其特征在于，包括：载体膜和通过涂布和干燥光固化性树脂组合物形成的光固化性树脂组合物层（L1） 和至少一种通过在光固化树脂组合物层（L1）和载体膜之间的间隙中涂覆和干燥热固性树脂组合物形成的热固性树脂组合物层（L2）。 一种印刷书写板的制造方法，其特征在于，包括以下工序：从基板表面侧开始依次形成包含热固性树脂组合物层（L2）和光固化树脂组合物层（L1）的树脂绝缘层 基材表面; 通过光刻法进行图案化的工艺; 以及通过激光加工进行图案化的工序。

公开(公告)号：US20150000965A1

公开(公告)日：2015-01-01

申请号：US14317657

申请日：2014-06-27

Applicant: KYOCERA SLC TECHNOLOGIES CORPORATION

Inventor： Makoto SHIROSHITA

IPC: H05K1/02 ,  H05K1/11

CPC classification number: H05K1/113 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2224/131 ,  H01L2224/81193 ,  H05K1/025 ,  H05K2201/0175 ,  H05K2201/0317 ,  H05K2201/0338 ,  H05K2201/10674 ,  H01L2924/014

Abstract: A wiring board 10a according to the present invention is provided with an insulating board 1 laminated at least one insulating layer 1b having a via hole 8 on at least one surface of a core layer 1a, a via conductor 2b formed inside the via hole 8 and containing a low resistance material, and a connection pad formed at the surface of the insulating layer 1b and including a thin film resistor layer 3a containing a high resistance material, wherein the thin film resistor layer 3a is adhered to the insulating layer 1b in such a manner as to cover the via conductor 2b and the insulating layer 1b surrounding the via conductor 2b.

Abstract translation: 根据本发明的布线板10a设置有绝缘板1，其在芯层1a的至少一个表面上具有通孔8的至少一个绝缘层1b，形成在通孔8内的通孔导体2b和 含有低电阻材料的连接焊盘和形成在绝缘层1b的表面的连接焊盘，并且包括含有高电阻材料的薄膜电阻层3a，其中薄膜电阻层3a以这样的方式粘附到绝缘层1b上 以覆盖通孔导体2b和围绕通孔导体2b的绝缘层1b的方式。

公开(公告)号：US20140376197A1

公开(公告)日：2014-12-25

申请号：US14483934

申请日：2014-09-11

Applicant: HARRIS CORPORATION

Inventor： MICHAEL RAYMOND WEATHERSPOON ,  DAVID B. NICOL ,  LOUIS JOSEPH RENDEK, JR.

IPC: H05K1/03 ,  H05K3/46 ,  H05K3/32 ,  H05K3/40 ,  H05K1/11 ,  H05K1/18

CPC classification number: H01L23/4985 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/6835 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49894 ,  H01L23/5383 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2221/68363 ,  H01L2221/68381 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/48 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48229 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2924/01029 ,  H01L2924/0105 ,  H01L2924/01327 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1421 ,  H01L2924/1431 ,  H01L2924/1511 ,  H01L2924/1579 ,  H05K1/036 ,  H05K1/0393 ,  H05K1/115 ,  H05K1/181 ,  H05K1/189 ,  H05K3/32 ,  H05K3/3436 ,  H05K3/4038 ,  H05K3/4602 ,  H05K3/4632 ,  H05K3/467 ,  H05K3/4688 ,  H05K2201/0133 ,  H05K2201/0141 ,  H05K2201/10674 ,  Y10T29/4913 ,  Y10T29/49224 ,  Y10T428/24917 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A method is for making an electronic device and includes forming an interconnect layer stack on a sacrificial substrate and having a plurality of patterned electrical conductor layers, and a dielectric layer between adjacent patterned electrical conductor layers. The method also includes laminating and electrically joining through an intermetallic bond a liquid crystal polymer (LCP) substrate to the interconnect layer stack on a side thereof opposite the sacrificial substrate. The method further includes removing the sacrificial substrate to expose a lowermost patterned electrical conductor layer, and electrically coupling at least one first device to the lowermost patterned electrical conductor layer.

Abstract translation: 一种用于制造电子器件的方法，包括在牺牲衬底上形成互连层堆叠并且具有多个图案化的导电层，以及在相邻的图案化电导体层之间的介电层。 该方法还包括通过液晶聚合物（LCP）衬底的金属间键合层叠和电连接到与牺牲衬底相对的一侧上的互连层堆叠。 该方法还包括去除牺牲衬底以暴露最下图案化电导体层，并将至少一个第一器件电耦合到最下图案化电导体层。

公开(公告)号：US20140367155A1

公开(公告)日：2014-12-18

申请号：US14302975

申请日：2014-06-12

Applicant: MICROCOSM TECHNOLOGY CO., LTD.

Inventor： Tang-Chieh HUANG

IPC: H05K1/18 ,  H05K3/30

CPC classification number: H05K1/183 ,  H05K3/4655 ,  H05K3/4697 ,  H05K2201/09127 ,  H05K2201/10674 ,  H05K2203/0264 ,  H05K2203/107 ,  Y10T29/4913

Abstract: A method of forming a component-embedded printed circuit board includes: preparing a first layered structure; preparing a second layered structure that includes an adhesive film and a releasable film; attaching the second layered structure to the first layered structure to form a layered stack, the releasable film releasably covering a mounting region of the first layered structure;heating and pressing the layered stack; cutting the second layered structure through the adhesive film; removing the releasable film together with a portion of the adhesive film from the mounting region to form a hole in the second layered structure; and mounting an electronic component in the hole.

Abstract translation: 一种形成部件嵌入式印刷电路板的方法包括：制备第一层状结构; 制备包括粘合剂膜和可剥离膜的第二层状结构; 将第二层状结构附接到第一层状结构以形成层叠堆叠，所述可剥离膜可释放地覆盖第一层状结构的安装区域; 加热和压制叠层; 通过粘合膜切割第二层结构; 从所述安装区域将所述可剥离膜与一部分所述粘合剂膜一起移除以在所述第二层状结构中形成孔; 并将电子部件安装在孔中。

公开(公告)号：US20140363927A1

公开(公告)日：2014-12-11

申请号：US13912652

申请日：2013-06-07

Applicant: Zhuhai Advanced Chip Carriers & Electronic Substrate Solutions Technologies Co., Ltd.

Inventor： Dror Hurwitz ,  Alex Huang

IPC: H05K1/02 ,  H05K1/11 ,  H05K3/00 ,  H01L23/00

CPC classification number: H05K1/0298 ,  H01L23/49822 ,  H01L24/13 ,  H01L24/81 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/81815 ,  H01L2924/12042 ,  H01L2924/15788 ,  H05K1/115 ,  H05K3/0082 ,  H05K3/108 ,  H05K3/282 ,  H05K3/4007 ,  H05K2201/0347 ,  H05K2201/0367 ,  H05K2201/10378 ,  H05K2201/10674 ,  H05K2201/10734 ,  H05K2203/1476 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/014

Abstract: A method of attaching a chip to the substrate with an outer layer comprising via pillars embedded in a dielectric such as solder mask, with ends of the via pillars flush with said dielectric, the method comprising the steps of: (o) optionally removing organic varnish, (p) positioning a chip having legs terminated with solder bumps in contact with exposed ends of the via pillars, and (q) applying heat to melt the solder bumps and to wet the ends of the vias with solder.

Abstract translation: 一种将芯片附着到具有外层的方法，外层包括嵌入电介质如焊料掩模中的通孔，通孔的端部与所述电介质齐平，所述方法包括以下步骤：（o）任选地除去有机清漆 ，（p）将具有用焊料凸块端接的腿的芯片定位成与通孔柱的暴露端接触，和（q）施加热量以熔化焊料凸块并用焊料润湿通孔的端部。

公开(公告)号：US20140345924A1

公开(公告)日：2014-11-27

申请号：US13902149

申请日：2013-05-24

Applicant: Nokia Corporation

Inventor： Mark Lee ALLEN ,  Chris BOWER ,  Darryl COTTON

IPC: H05K1/02 ,  H05K1/09

CPC classification number: H05K1/0272 ,  H01L23/52 ,  H01L24/00 ,  H01L24/24 ,  H01L24/25 ,  H01L24/82 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/24101 ,  H01L2224/24226 ,  H01L2224/24997 ,  H01L2224/25171 ,  H01L2224/25175 ,  H01L2224/2919 ,  H01L2224/82101 ,  H01L2224/82138 ,  H01L2224/8284 ,  H01L2224/82862 ,  H01L2224/82874 ,  H01L2224/82877 ,  H01L2224/82986 ,  H01L2224/8385 ,  H01L2224/92144 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/12043 ,  H05K1/092 ,  H05K1/097 ,  H05K3/101 ,  H05K3/107 ,  H05K2201/0257 ,  H05K2201/0302 ,  H05K2201/09036 ,  H05K2201/09227 ,  H05K2201/10674 ,  H05K2203/1469 ,  Y10T29/49117 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A substrate including a fluid reservoir and a connected fluid channel, the fluid reservoir positioned away from a component region of the substrate, the fluid channel configured to extend from the fluid reservoir to guide an electrically conductive fluid from the fluid reservoir at a reservoir end of the fluid channel through the fluid channel to a component end of the fluid channel, the component end extending to the component region of the substrate to enable the formation of an electrical connection to a connector of an electronic component appropriately positioned in the component region, formation of the electrical connection allowing the electronic component to be interconnected to other electronic components using one or more of the fluid reservoir and fluid channel.

Abstract translation: 包括流体储存器和连接的流体通道的基板，所述流体储存器远离所述基板的部件区域定位，所述流体通道被配置为从所述流体储存器延伸以在所述流体储存器的储存器端部处从所述流体储存器引导导电流体 通过流体通道的流体通道流到流体通道的部件端，部件端部延伸到基板的部件区域，以使得能够形成与适当地定位在部件区域中的电子部件的连接器的电连接，形成 的电连接，允许使用一个或多个流体储存器和流体通道将电子部件互连到其他电子部件。

公开(公告)号：US08872335B2

公开(公告)日：2014-10-28

申请号：US11781282

申请日：2007-07-23

Applicant: Holger Huebner ,  Martin Franosch

Inventor： Holger Huebner ,  Martin Franosch

IPC: H01L23/48 ,  H01L23/31 ,  H01L21/56 ,  H05K3/30 ,  H01L23/00 ,  H01L23/498 ,  H05K3/28

CPC classification number: H05K3/305 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/49816 ,  H01L24/12 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L24/83 ,  H01L24/90 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/16225 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/83191 ,  H01L2224/83194 ,  H01L2224/8383 ,  H01L2224/83862 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01068 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/15788 ,  H05K3/284 ,  H05K2201/10674 ,  H05K2201/10977 ,  H05K2203/0783 ,  H05K2203/306 ,  Y02P70/613 ,  H01L2924/00

Abstract: It is proposed a method of manufacturing an electronic system wherein a first substrate comprising first connection elements on a first surface of the first substrate is provided; a second substrate comprising second connection elements on a first surface of the second substrate is provided; a polymer layer is applied to at least one of the two first surfaces; the first connection elements are attached to the second connection elements; and the polymer layer is caused to swell during or after the attachment.

Abstract translation: 提出了一种制造电子系统的方法，其中提供包括在第一基板的第一表面上的第一连接元件的第一基板; 提供包括在第二基板的第一表面上的第二连接元件的第二基板; 将聚合物层施加到两个第一表面中的至少一个上; 第一连接元件附接到第二连接元件; 并且在附着期间或之后使聚合物层膨胀。