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公开(公告)号：US09975754B2
公开(公告)日：2018-05-22
申请号：US15498009
申请日：2017-04-26
Inventor： Fu-Chun Huang , Li-Chen Yen , Tzu-Heng Wu , Yi-Heng Tsai , Chun-Ren Cheng
CPC classification number: B81B3/0086 , B81B3/0008 , B81B2203/0307 , B81B2207/015 , B81B2207/07 , B81C1/00246 , B81C2201/0132 , B81C2201/0181 , B81C2203/035
Abstract: A method of manufacturing a semiconductor structure includes receiving a first substrate including a dielectric layer disposed over the first substrate; forming a sensing structure and a bonding structure over the dielectric layer; disposing a conductive layer on the sensing structure; disposing a barrier layer over the dielectric layer; removing a first portion of the barrier layer to at least partially expose the conductive layer on the sensing structure; and removing a second portion of the barrier layer to at least partially expose the bonding structure.
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公开(公告)号：US20180065847A1
公开(公告)日：2018-03-08
申请号：US15807661
申请日：2017-11-09
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Stephen E. LUCE , Anthony K. STAMPER
CPC classification number: B81C1/00698 , B81C1/0015 , B81C1/00166 , B81C1/00523 , B81C2201/0132 , B81C2201/0133 , B81C2201/0145 , B81C2201/0154 , B81C2203/0145 , H01H1/0036 , H01H1/58 , H01H11/00 , H01H49/00 , H01H59/00 , H01H59/0009 , H01H2059/0018 , Y10T29/49105
Abstract: An approach includes a method of fabricating a switch. The approach includes forming a first cantilevered electrode over a first electrode, forming a second cantilevered electrode over a second electrode and operable to directly contact the first cantilevered electrode upon an application of a voltage to at least one of the first electrode and a second electrode, and the first cantilevered electrode includes an arm with an extending protrusion which extends upward from an upper surface of the arm.
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公开(公告)号：US20180044166A1
公开(公告)日：2018-02-15
申请号：US15556070
申请日：2016-03-04
Applicant: Endress + Hauser GmbH + Co. KG
Inventor： Rafael Teipen , Benjamin Lemke
CPC classification number: B81B3/0072 , B81B2201/0264 , B81B2203/0127 , B81B2203/0315 , B81B2203/04 , B81C1/00531 , B81C2201/0132 , G01L9/0048 , G01L9/0073 , G01L13/025 , G01L19/0618
Abstract: A MEMS sensor with improved overload resistance for metrological registering of a measured variable comprises a plurality of layers, especially silicon layers, arranged on one another. The layers include at least one inner layer, which is arranged between a first layer and a second layer, and in the inner layer there is provided extending perpendicularly to the plane of the inner layer through the inner layer at least one cavity, on which borders externally at least sectionally and forming a connecting element, a region of the inner layer, which is connected with the first layer and the second layer. A lateral surface of the connecting element externally at least sectionally bordering the cavity has in an end region facing the first layer a rounding decreasing the cross sectional area of the cavity in the direction of the first layer, and has in an end region facing the second layer a rounding decreasing the cross sectional area of the cavity in the direction of the second layer.
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公开(公告)号：US09884755B2
公开(公告)日：2018-02-06
申请号：US15006301
申请日：2016-01-26
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Yu-Jui Chen , I-Shi Wang , Ren-Dou Lee , Jen-Hao Liu
CPC classification number: B81B3/0005 , B81B3/001 , B81B2203/04 , B81B2207/012 , B81B2207/07 , B81C1/00984 , B81C2201/0132 , B81C2203/037 , B81C2203/0785
Abstract: The present disclosure relates to a MEMS package with a rough metal anti-stiction layer, to improve stiction characteristics, and an associated method of formation. In some embodiments, the MEMS package includes a MEMS IC bonded to a CMOS IC. The CMOS IC has a CMOS substrate and an interconnect structure disposed over the CMOS substrate. The interconnect structure includes a plurality of metal layers disposed within a plurality of dielectric layers. The MEMS IC is bonded to an upper surface of the interconnect structure and, in cooperation with the CMOS IC, enclosing a cavity between the MEMS IC and the CMOS IC. The MEMS IC has a moveable mass arranged in the cavity. The MEMS package further includes an anti-stiction layer disposed on the upper surface of the interconnect structure under the moveable mass. The anti-stiction layer is made of metal and has a rough top surface.
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公开(公告)号：US09862599B2
公开(公告)日：2018-01-09
申请号：US14829738
申请日：2015-08-19
Inventor： Sang Kyun Lee , Yil Suk Yang
IPC: B81C1/00 , H03H3/02 , H01L41/09 , H01L41/113 , H03H3/08 , H02N2/18 , H01M10/052 , B81B3/00 , H01M6/40 , H01M10/0585
CPC classification number: B81C1/00682 , B81B3/0051 , B81C1/0015 , B81C2201/0132 , B81C2201/053 , H01L41/094 , H01L41/1134 , H01L41/1136 , H01M6/40 , H01M10/052 , H01M10/0585 , H02N2/18 , H02N2/181 , H02N2/188 , H03H3/02 , H03H3/08 , Y02E60/122 , Y10T29/42 , Y10T29/43
Abstract: A method of manufacturing an apparatus for harvesting and storing piezoelectric energy includes forming a groove at a side on a substrate. The method further includes embedding and planarizing a polymer in the groove, forming a piezoelectric energy harvesting device, which converts and stores an external vibration into electric energy, onto the substrate, and forming a piezoelectric MEMS cantilever by forming a hole at a side of the piezoelectric energy harvesting device and by removing the polymer in the groove through the hole.
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Patent Agency Ranking
公开(公告)号：US09857229B1
公开(公告)日：2018-01-02
申请号：US15188116
申请日：2016-06-21
Applicant: MP High Tech Solutions Pty Ltd
Inventor： Marek Steffanson
CPC classification number: G01J5/10 , B81C1/00142 , B81C1/0019 , B81C2201/0132 , G01J5/045 , G01J5/0806 , G01J5/40
Abstract: A method of fabricating electromagnetic radiation detection devices including: forming a first mask on a substrate; forming a structural layer on the substrate using the first mask; forming a metallic layer overlying the structural layer; removing the first mask; forming a second mask on the substrate, the second mask comprising mask openings; selectively patterning the metallic layer using the mask openings; and removing the second mask.
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公开(公告)号：US20170341931A1
公开(公告)日：2017-11-30
申请号：US15650953
申请日：2017-07-16
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Bucknell C. Webb
CPC classification number: B81B3/0056 , B81B2201/012 , B81B2201/014 , B81B2203/0118 , B81B2203/0315 , B81B2203/04 , B81B2207/07 , B81C1/0015 , B81C1/00619 , B81C2201/0112 , B81C2201/0132 , B81C2201/0178 , B81C2203/0109 , B81C2203/0136 , H01H59/0009 , H01H2001/0078
Abstract: Deep via technology is used to construct an integrated silicon cantilever and cavity oriented in a vertical plane which creates an electrostatically-switched MEMS switch in a small wafer area. Another embodiment is a small wafer area electrostatically-switched, vertical-cantilever MEMS switch wherein the switch cavity is etched within a volume defined by walls grown internally within a silicon substrate using through vias.
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公开(公告)号：US20170341930A1
公开(公告)日：2017-11-30
申请号：US15650788
申请日：2017-07-14
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Bucknell C. Webb
CPC classification number: B81B3/0056 , B81B2201/012 , B81B2201/014 , B81B2203/0118 , B81B2203/0315 , B81B2203/04 , B81B2207/07 , B81C1/0015 , B81C1/00619 , B81C2201/0112 , B81C2201/0132 , B81C2201/0178 , B81C2203/0109 , B81C2203/0136 , H01H59/0009 , H01H2001/0078
Abstract: Deep via technology is used to construct an integrated silicon cantilever and cavity oriented in a vertical plane which creates an electrostatically-switched MEMS switch in a small wafer area. Another embodiment is a small wafer area electrostatically-switched, vertical-cantilever MEMS switch wherein the switch cavity is etched within a volume defined by walls grown internally within a silicon substrate using through vias.
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公开(公告)号：US09822000B2
公开(公告)日：2017-11-21
申请号：US15170154
申请日：2016-06-01
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chun-Wen Cheng , Chia-Hua Chu , Jung-Huei Peng
CPC classification number: B81C1/00238 , B81B3/001 , B81B7/007 , B81B2201/0235 , B81B2201/0242 , B81B2201/0264 , B81B2203/0315 , B81B2207/012 , B81B2207/07 , B81C2201/0132 , B81C2203/035 , B81C2203/037 , B81C2203/0792 , H01L2224/16
Abstract: The present disclosure relates an integrated chip having one or more MEMS devices. In some embodiments, the integrated chip has a carrier substrate with one or more cavities disposed within a first side of the carrier substrate. A dielectric layer is disposed between the first side of the carrier substrate and a first side of a micro-electromechanical system (MEMS) substrate. The dielectric layer has sidewalls that are laterally set back from sidewalls of openings extending through the MEMs substrate to the one or more cavities. A bonding structure, including an intermetallic compound having a plurality of metallic elements, abuts a second side of the MEMS substrate and is electrically connected to a metal interconnect layer within a dielectric structure disposed over a CMOS substrate.
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公开(公告)号：US20170313573A1
公开(公告)日：2017-11-02
申请号：US15142381
申请日：2016-04-29
Applicant: FREESCALE SEMICONDUCTOR, INC.
Inventor： RUBEN B. MONTEZ , ARVIND S. SALIAN , ROBERT F. STEIMLE
CPC classification number: B81B3/001 , B81B2201/0235 , B81B2203/0315 , B81C1/00976 , B81C2201/0132 , B81C2201/115 , B81C2203/0118
Abstract: A surface of a cavity of a MEMS device that is rough to reduce stiction. In some embodiments, the average roughness (Ra) of the surface is 5 nm or greater. In some embodiments, the rough surface is formed by forming one or more layers of a rough oxidizable material, then oxidizing the material to form an oxide layer with a rough surface. Another layer is formed over the oxide layer with the rough surface, wherein the roughness of the oxide layer is transferred to the another layer.
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