公开(公告)号：US08153503B2

公开(公告)日：2012-04-10

申请号：US12295997

申请日：2007-04-03

Applicant: Barbara Charlet ,  Hélène Le Poche ,  Yveline Gobil

Inventor： Barbara Charlet ,  Hélène Le Poche ,  Yveline Gobil

IPC: H01L21/322

CPC classification number: B81C1/00833 ,  B81B2203/0315 ,  B81C2201/019 ,  B81C2201/053 ,  H01J9/025

Abstract: The invention relates to a method for protecting the interior of at least one cavity (4) having a portion of interest (5) and opening onto a face of a microstructured element (1), consisting of depositing, on said face, a nonconformal layer (6) of a protective material, in which said nonconformal layer closes off the cavity without covering the portion of interest.The invention also relates to a method for producing a device comprising such a microstructured element.

Abstract translation: 本发明涉及一种用于保护具有感兴趣部分（5）的至少一个空腔（4）的内部的方法，并且在微结构化元件（1）的表面上开口，该方法包括在所述面上沉积非共形层 （6），其中所述非共形层在不覆盖感兴趣部分的情况下封闭空腔。 本发明还涉及一种用于制造包括这种微结构元件的器件的方法。

公开(公告)号：US20110127666A1

公开(公告)日：2011-06-02

申请号：US12855447

申请日：2010-08-12

Applicant: Chia-Lun TSAI ,  Chia-Ming CHENG ,  Long-Sheng YEOU

Inventor： Chia-Lun TSAI ,  Chia-Ming CHENG ,  Long-Sheng YEOU

IPC: H01L23/48 ,  H01L21/50

CPC classification number: H01L21/78 ,  B81B2207/07 ,  B81B2207/098 ,  B81C1/00825 ,  B81C2201/014 ,  B81C2201/053 ,  B81C2203/0118

Abstract: An embodiment of the present invention relates to a chip package and fabrication method thereof, which includes a chip protection layer or an additional etching stop layer to cover conducting pads to prevent dicing residue from damaging or scratching the conducting pads. According to another embodiment, a chip protection layer, an additional etching stop layer formed thereon, or a metal etching stop layer level with conducting pads or combinations thereof may be used when etching an intermetal dielectric layer at a structural etching region and a silicon substrate to form an opening for subsequent semiconductor manufacturing processes.

Abstract translation: 本发明的实施例涉及一种芯片封装及其制造方法，其包括芯片保护层或附加的蚀刻停止层，以覆盖导电焊盘，以防止切割残留物损坏或划伤导电焊盘。 根据另一个实施例，当蚀刻结构蚀刻区域和硅衬底上的金属间电介质层时，可以使用芯片保护层，其上形成的附加蚀刻停止层或具有导电焊盘或其组合的金属蚀刻停止层， 形成随后的半导体制造工艺的开口。

公开(公告)号：US07781850B2

公开(公告)日：2010-08-24

申请号：US11090911

申请日：2005-03-25

Applicant: Mark W. Miles ,  John Batey ,  Clarence Chui ,  Manish Kothari ,  Ming-Hau Tung

Inventor： Mark W. Miles ,  John Batey ,  Clarence Chui ,  Manish Kothari ,  Ming-Hau Tung

IPC: H01L27/14

CPC classification number: B81B3/0086 ,  B81C2201/0109 ,  B81C2201/014 ,  B81C2201/053 ,  G02B26/001

Abstract: In one embodiment, the invention provides a method for fabricating a microelectromechanical systems device. The method comprises fabricating a first layer comprising a film having a characteristic electromechanical response, and a characteristic optical response, wherein the characteristic optical response is desirable and the characteristic electromechanical response is undesirable; and modifying the characteristic electromechanical response of the first layer by at least reducing charge build up thereon during activation of the microelectromechanical systems device.

Abstract translation: 在一个实施例中，本发明提供一种用于制造微机电系统装置的方法。 该方法包括制造包括具有特征机电响应的膜的第一层和特征光学响应，其中特征光学响应是期望的，并且特征机电响应是不期望的; 以及通过在所述微机电系统装置的启动期间至少减少其上的电荷积累来修改所述第一层的特征机电响应。

公开(公告)号：US07560037B2

公开(公告)日：2009-07-14

申请号：US11213466

申请日：2005-08-26

Applicant: Bevan Staple ,  Jillian Buriak

Inventor： Bevan Staple ,  Jillian Buriak

IPC: H01B13/00

CPC classification number: B82Y30/00 ,  B81C1/00476 ,  B81C1/00801 ,  B81C2201/0114 ,  B81C2201/0133 ,  B81C2201/0139 ,  B81C2201/053

Abstract: A microelectromechanical structure is formed by depositing sacrificial and structural material over a substrate to form a structural layer on a component electrically attached with the substrate. The galvanic potential of the structural layer is greater than the galvanic potential of the component. At least a portion of the structural material is covered with a protective material that has a galvanic potential less than or equal to the galvanic potential of the component. The sacrificial material is removed with a release solution. At least one of the protective material and release solution is surfactanated, the surfactant functionalizing a surface of the component.

Abstract translation: 通过将牺牲和结构材料沉积在衬底上以在与衬底电连接的部件上形成结构层来形成微机电结构。 结构层的电位大于元件的电位。 结构材料的至少一部分被保护材料覆盖，该保护材料具有小于或等于部件的电位的电位。 牺牲材料用释放溶液除去。 保护材料和释放溶液中的至少一种被表面活性化，表面活性剂对组分的表面进行官能化。

公开(公告)号：US20090121299A1

公开(公告)日：2009-05-14

申请号：US12073392

申请日：2008-03-05

Applicant: Lung-Tai Chen ,  Chun-Hsun Chu ,  Tzong-Che Ho ,  Bor-Chen Tsai

Inventor： Lung-Tai Chen ,  Chun-Hsun Chu ,  Tzong-Che Ho ,  Bor-Chen Tsai

IPC: H01L29/00 ,  H01L21/00

CPC classification number: B81C1/00793 ,  B81B7/0054 ,  B81B2201/0292 ,  B81B2207/07 ,  B81C1/00182 ,  B81C2201/053 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/13023 ,  H01L2924/1461 ,  H01L2924/00

Abstract: A wafer level sensing package and manufacturing process thereof are described. The process includes providing a wafer having sensing chips, in which each sensing chip has a sensing area and pads; forming a stress release layer on a wafer surface; cladding a photoresist layer on the stress release layer; patterning the photoresist layer to expose the pads and a portion of the stress release layer, without exposing opening areas of the sensing areas; forming a conductive metal layer of re-distributed pads on the portion of the stress release layer exposed by the photoresist layer; removing the photoresist layer; forming a re-cladding photoresist layer on the stress release layer and the conductive metal layer; forming holes in the re-cladding photoresist layer above the re-distributed pad area; and forming conductive bumps in the holes to electrically connect to the conductive metal layer.

Abstract translation: 描述了晶片级感测封装及其制造工艺。 该过程包括提供具有感测芯片的晶片，其中每个感测芯片具有感测区域和焊盘; 在晶片表面上形成应力释放层; 在应力释放层上包覆光致抗蚀剂层; 图案化光致抗蚀剂层以暴露垫和应力释放层的一部分，而不暴露感测区域的开口区域; 在由光致抗蚀剂层暴露的应力释放层的部分上形成再分布焊盘的导电金属层; 去除光致抗蚀剂层; 在所述应力释放层和所述导电金属层上形成再包覆光致抗蚀剂层; 在再分布的焊盘区域上方的再包层光致抗蚀剂层中形成孔; 以及在所述孔中形成导电凸块以电连接到所述导电金属层。

公开(公告)号：US20080132037A1

公开(公告)日：2008-06-05

申请号：US11848423

申请日：2007-08-31

Applicant: Toshikazu FURUI

Inventor： Toshikazu FURUI

IPC: H01L21/00

CPC classification number: B81C1/00888 ,  B81C2201/053 ,  H01L21/78

Abstract: Prior to dicing, a volatile protective agent is applied to at least the face of the substrate in which the devices are fabricated. Then the devices are separated by dicing. After dicing, the surface of the volatile protective agent is cleaned, and then the volatile protective agent is evaporated.

Abstract translation: 在切割之前，将挥发性保护剂施加到至少其中制造器件的衬底的表面。 然后通过切割分离设备。 切割后，清洁挥发性保护剂的表面，然后蒸发挥发性保护剂。

公开(公告)号：US20070289940A1

公开(公告)日：2007-12-20

申请号：US11213466

申请日：2005-08-26

Applicant: Bevan Staple ,  Jillian Buriak

Inventor： Bevan Staple ,  Jillian Buriak

IPC: H01B13/00

CPC classification number: B82Y30/00 ,  B81C1/00476 ,  B81C1/00801 ,  B81C2201/0114 ,  B81C2201/0133 ,  B81C2201/0139 ,  B81C2201/053

Abstract: A microelectromechanical structure is formed by depositing sacrificial and structural material over a substrate to form a structural layer on a component electrically attached with the substrate. The galvanic potential of the structural layer is greater than the galvanic potential of the component. At least a portion of the structural material is covered with a protective material that has a galvanic potential less than or equal to the galvanic potential of the component. The sacrificial material is removed with a release solution. At least one of the protective material and release solution is surfactanated, the surfactant functionalizing a surface of the component.

Abstract translation: 通过将牺牲和结构材料沉积在衬底上以在与衬底电连接的部件上形成结构层来形成微机电结构。 结构层的电位大于元件的电位。 结构材料的至少一部分被保护材料覆盖，该保护材料具有小于或等于部件的电位的电位。 牺牲材料用释放溶液除去。 保护材料和释放溶液中的至少一种被表面活性化，表面活性剂对组分的表面进行官能化。

公开(公告)号：US20070281492A1

公开(公告)日：2007-12-06

申请号：US11447186

申请日：2006-06-05

Applicant: Jeffrey D. Chinn ,  Boris Kobrin ,  Romuald Nowak

Inventor： Jeffrey D. Chinn ,  Boris Kobrin ,  Romuald Nowak

IPC: H01L21/47

CPC classification number: H01L21/02126 ,  B81C1/00896 ,  B81C2201/053 ,  C23C16/44 ,  C23C16/455 ,  H01L21/02263 ,  H01L21/3121

Abstract: A method of protecting a substrate during fabrication of semiconductor, MEMS, or biotechnology devices. The method includes application of a protective thin film which typically has a thickness ranging from about 3 Å to about 1,000 Å, wherein precursor materials used to deposit the protective thin film are organic-based precursors which include at least one fluorine-comprising functional group at one end of a carbon back bone and at least one functional bonding group at the opposite end of a carbon backbone, and wherein the carbon backbone ranges in length from 4 carbons through about 12 carbons. In many applications at least a portion of the protective thin film is removed during fabrication of the devices.

Abstract translation: 一种在制造半导体，MEMS或生物技术设备期间保护衬底的方法。 该方法包括施加通常具有约3至约1000的厚度的保护性薄膜，其中用于沉积保护性薄膜的前体材料是有机基前体，其包括至少一个含氟官能团 碳骨架的一端和在碳骨架的相对端处的至少一个功能键合基团，其中碳骨架的长度为4个碳到约12个碳原子。 在许多应用中，在制造器件期间，保护薄膜的至少一部分被去除。

公开(公告)号：US20070146859A1

公开(公告)日：2007-06-28

申请号：US11639987

申请日：2006-12-15

Applicant: Jeong-Suong Yang ,  Yun-Jin Ko ,  Jong-Hyeong Song

Inventor： Jeong-Suong Yang ,  Yun-Jin Ko ,  Jong-Hyeong Song

IPC: G02B26/00

CPC classification number: G02B26/0858 ,  B81B2201/047 ,  B81C1/00793 ,  B81C2201/053 ,  G02B26/0808

Abstract: An optical modulator having a junction layer is disclosed. An optical modulator may be provided which includes a substrate, an insulation layer positioned on the substrate, a ribbon layer positioned with an intermediate portion spaced apart from the insulation layer by a predetermined distance, a protective layer positioned on both ends of the ribbon layer, a junction layer positioned on the protective layer which has an adhesive property and which prevents the diffusion of gas, and a piezoelectric element joined with the protective layer by way of the junction layer interposed in-between which moves the intermediate portion of the ribbon layer toward and away from the substrate. In certain embodiments of the invention, the light diffraction property and reliability of the overall optical modulator can be maximized, by positioning a junction layer, having improved adhesion and capable of preventing the diffusion of oxygen, on the lower surface of the piezoelectric elements.

Abstract translation: 公开了一种具有结层的光调制器。 可以提供光调制器，其包括基板，位于基板上的绝缘层，定位在与绝缘层隔开预定距离的中间部分的带层，位于带层两端的保护层， 位于保护层上的接合层，其具有粘合性并且防止气体的扩散;以及压电元件，其通过插入其间的接合层与保护层接合，从而使带状层的中间部分向着 并远离基板。 在本发明的某些实施例中，通过在压电元件的下表面上定位具有改进的附着力并且能够防止氧的扩散的接合层，可以最大化整个光学调制器的光衍射特性和可靠性。

公开(公告)号：US07235185B2

公开(公告)日：2007-06-26

申请号：US11163989

申请日：2005-11-07

Applicant: I-Ju Chen

Inventor： I-Ju Chen

IPC: B44C1/22 ,  H01L21/301

CPC classification number: B81C1/00896 ,  B81C2201/053 ,  Y10S438/928

Abstract: A wafer comprising a front surface and a back surface is provided. The wafer further includes a front pattern on the front surface, the front pattern having a plurality of holes. A low-viscosity fluid is formed on the front surface and filled into the holes. Following that, a high-viscosity fluid is formed and filled into the holes by diffusion.

Abstract translation: 提供了包括前表面和后表面的晶片。 晶片还包括前表面上的前图案，前图案具有多个孔。 在前表面上形成低粘度流体并填充到孔中。 之后，形成高粘度流体并通过扩散填充到孔中。