公开(公告)号：US06648208B2

公开(公告)日：2003-11-18

申请号：US10218051

申请日：2002-08-12

Applicant: Leu-Wen Tsay ,  Ren-Kae Shiue

Inventor： Leu-Wen Tsay ,  Ren-Kae Shiue

IPC: B23K3102

CPC classification number: C04B37/026 ,  B23K31/02 ,  B32B18/00 ,  B32B2311/06 ,  B32B2311/22 ,  B32B2311/30 ,  C04B2237/125 ,  C04B2237/343 ,  C04B2237/405 ,  C04B2237/406 ,  C04B2237/408 ,  C04B2237/62 ,  C04B2237/68 ,  H05K1/092 ,  H05K1/113 ,  H05K3/248 ,  H05K3/328 ,  H05K3/4061 ,  H05K2201/035 ,  H05K2201/0959 ,  H05K2201/09981

Abstract: A method of manufacturing a joint between metal and a ceramic substrate for a high temperature sensor. First, a predetermined hole is formed in the ceramic substrate to serve as a joint portion. A bonding layer is preferably disposed on the ceramic substrate to form on the inner surface and the surrounding portion of the hole. Next, the hole is filled with a supporting metal. Then, a conductive layer is formed on the supporting metal and the bonding layer. A metal signal conductive frame is then formed on the conductive layer. Next, a welding spot is formed through the metal signal conductive frame, the conductive layer and the supporting metal at the joint portion by a welding process.

公开(公告)号：US06631838B2

公开(公告)日：2003-10-14

申请号：US09832122

申请日：2001-04-11

Applicant: Nam-Jin Kim ,  Young-Cheol Ahn ,  Won-Jae Kim

Inventor： Nam-Jin Kim ,  Young-Cheol Ahn ,  Won-Jae Kim

IPC: B23K3524

CPC classification number: H05K3/0094 ,  H05K3/1216 ,  H05K3/28 ,  H05K3/4652 ,  H05K2201/09509 ,  H05K2201/0959 ,  H05K2203/0759 ,  H05K2203/085 ,  H05K2203/1476

Abstract: A method for fabricating a printed circuit board includes the steps of: fabricating a printed circuit board having at least one collapsed portion; depositing a first solder resist in the collapsed portion; exposing the first solder resist-coated printed circuit board at a pressure lower than atmospheric pressure for a predetermined time; coating a second solder resist on the entire surface of the printed circuit board; and drying and hardening the first and the second solder resists. With this method, when a solder resist is coated, since an air space does not remain in a blind via hole, the reliability of the attachment between a printed circuit board and the solder resist layer is increased.

Abstract translation: 制造印刷电路板的方法包括以下步骤：制造具有至少一个折叠部分的印刷电路板; 在折叠部分中沉积第一阻焊剂; 将第一耐焊锡涂布印刷电路板在低于大气压的压力下暴露预定时间; 在印刷电路板的整个表面上涂覆第二阻焊剂; 并干燥和硬化第一和第二阻焊剂。 利用这种方法，当涂覆阻焊剂时，由于空气空间不保留在盲孔中，所以印刷电路板和阻焊层之间的连接的可靠性增加。

公开(公告)号：US20030183421A1

公开(公告)日：2003-10-02

申请号：US10108219

申请日：2002-03-27

Inventor： Terrance J. Dishongh ,  Carolyn R. McCormick

IPC: H05K001/11

CPC classification number: H05K1/113 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H05K3/0094 ,  H05K3/3436 ,  H05K3/3452 ,  H05K3/429 ,  H05K2201/09545 ,  H05K2201/0959 ,  H05K2201/10234 ,  H05K2201/10734 ,  Y02P70/613 ,  Y10T29/49165 ,  Y10T29/49167

Abstract: A first signal routing layer may be formed on a first surface of a printed circuit board (PCB). An array of interconnections may formed on the first surface of the PCB, the array of interconnections comprising at least one padless via formed within the PCB, the at least one padless via extending from the first signal routing layer to at least one conductive plane and/or a second signal routing layer. The at least one padless via may be in electrical contact with the at least one conductive plane and/or a conductive trace on the second signal routing layer. A component may be attached to the PCB, with a solder interconnection between the at least one padless via and a contact pad on a bottom surface of the component. The component may be, for example, an electronic component such as a ball grid array (BGA) component or a leadless surface mount component.

Abstract translation: 第一信号布线层可以形成在印刷电路板（PCB）的第一表面上。 互连阵列可以形成在PCB的第一表面上，互连阵列包括形成在PCB内的至少一个无衬垫通孔，从第一信号布线层延伸到至少一个导电平面的至少一个无衬垫通孔和/ 或第二信号路由层。 所述至少一个无衬垫通孔可以与所述至少一个导电平面和/或所述第二信号布线层上的导电迹线电接触。 组件可以附接到PCB，其中焊料互连在该至少一个无衬垫通孔和该部件的底部表面上的接触焊盘之间。 组件可以是例如电子部件，例如球栅阵列（BGA）部件或无引线表面安装部件。

公开(公告)号：US20030173676A1

公开(公告)日：2003-09-18

申请号：US10375018

申请日：2003-02-28

Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.

Inventor： Yasuyoshi Horikawa

IPC: H01L023/48

CPC classification number: H05K1/0231 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2924/01004 ,  H01L2924/01078 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/19106 ,  H05K3/429 ,  H05K3/4602 ,  H05K2201/09481 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2201/10545 ,  H05K2201/10674

Abstract: A semiconductor device includes: a multi-layered wiring substrate in which a multiple wiring pattern layers are laminated through insulating layers. The multi-layered wiring substrate has a first, semiconductor element mounting face and a second face opposite to the first face. A semiconductor element is mounted on and connected to connecting pads on the first face. A chip-capacitor is arranged on and connected to the connecting pads on the second face. An electric power supply circuit includes the chip-capacitor for supplying electric power to the semiconductor element. Conductor paths for electrically connecting the first connecting pads with the second connecting pads are substantially extended vertically and penetrate through the multi-layered wiring substrate through so as to reduce the length of the conductor paths to a minimum, so that the chip-capacitor is located at the opposite side of the semiconductor element.

Abstract translation: 半导体器件包括：多层布线基板，其中通过绝缘层层叠多个布线图案层。 多层布线基板具有第一半导体元件安装面和与第一面相反的第二面。 半导体元件安装在第一面上并连接到第一面上的连接焊盘。 芯片电容器布置在第二面上并连接到第二面上的连接焊盘。 电源电路包括用于向半导体元件供电的芯片电容器。 用于将第一连接焊盘与第二连接焊盘电连接的导体路径基本上垂直延伸并穿过多层布线基板，以便将导体路径的长度减小到最小，使得芯片电容器位于 在半导体元件的相对侧。

公开(公告)号：US06613986B1

公开(公告)日：2003-09-02

申请号：US09787321

申请日：2001-05-17

Applicant: Naohiro Hirose ,  Honjin En

Inventor： Naohiro Hirose ,  Honjin En

IPC: H05K103

CPC classification number: H01L29/40 ,  H01L21/4763 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/15311 ,  H05K1/0224 ,  H05K1/0253 ,  H05K1/03 ,  H05K3/064 ,  H05K3/244 ,  H05K3/382 ,  H05K3/403 ,  H05K3/4602 ,  H05K2201/0347 ,  H05K2201/062 ,  H05K2201/093 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2201/09645 ,  H05K2201/09681 ,  H05K2203/1178

Abstract: Mesh holes 35a and 59a of upper solid layers 35 and upper solid layers 59 are formed to overlie on one another, so that the insulating properties of interlayer resin insulating layers 50 are not lowered. Here, the diameter of each mesh hole is preferably 75 to 300 &mgr;m. The reason is as follows. If the diameter of the mesh hole is less than 75 &mgr;m, it is difficult to overlay the upper and lower mesh holes on one another. If the diameter exceeds 300 &mgr;m, the insulating properties of the interlayer resin insulating layers deteriorate. In addition, the distance between the mesh holes is preferably 100 to 2000 &mgr;m. The reason is as follows. If the distance is less than 100 &mgr;m, the solid layer cannot function. If the distance exceeds 2000 &mgr;m, the deterioration of the insulating properties of the interlayer resin insulating film occurs.

公开(公告)号：US06612028B1

公开(公告)日：2003-09-02

申请号：US09699977

申请日：2000-10-30

Applicant: Masaharu Shirai

Inventor： Masaharu Shirai

IPC: H05K302

CPC classification number: H05K3/4661 ,  H05K3/0023 ,  H05K3/185 ,  H05K3/4602 ,  H05K2201/0959 ,  H05K2203/0796 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155

Abstract: Methods are provided for the manufacture of a conductive layer on an insulating layer and for the manufacture of a built-up circuit board, each include an innovative step of irradiating the surface of an insulating (resin) layer with ultraviolet light, so that a conventional swelling process can be eliminated or simplified.

Abstract translation: 提供了用于在绝缘层上制造导电层和用于制造积层电路板的方法，每个都包括用紫外线照射绝缘（树脂）层的表面的创新步骤，使得常规 膨胀过程可以消除或简化。

公开(公告)号：US06598291B2

公开(公告)日：2003-07-29

申请号：US09840251

申请日：2001-04-23

Applicant: John L. Parker, Jr. ,  Pamela L. Miscikowski

Inventor： John L. Parker, Jr. ,  Pamela L. Miscikowski

IPC: H05K310

CPC classification number: H05K3/426 ,  H01R12/523 ,  H05K1/113 ,  H05K3/0094 ,  H05K3/246 ,  H05K3/4069 ,  H05K2201/0347 ,  H05K2201/0355 ,  H05K2201/0959 ,  H05K2203/1461 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: An insulator substrate or printed circuit board (PCB) having a filled and plated via. A sidewall of the via and preferably opposite sides of the insulator substrate are first plated with a conductive material. The plated via is then filled with an electrically conductive fill composition. A conductive cap layer is preferably formed over both ends of the conductive fill composition and the opposite surfaces of the insulator substrate, and can be bonded to a surface mount contact as a land or a pad.

公开(公告)号：US06586682B2

公开(公告)日：2003-07-01

申请号：US09511194

申请日：2000-02-23

Applicant: Jan I. Strandberg

Inventor： Jan I. Strandberg

IPC: H05K103

CPC classification number: H05K3/4602 ,  H05K1/0237 ,  H05K3/0023 ,  H05K3/388 ,  H05K2201/09536 ,  H05K2201/0959

Abstract: The present invention provides a solution to the problem of controlling the inter-layer impedance of a deposited thin film layer stack accommodating high-density interconnects. The invention enables high-density signal lines to be routed over a reference plane to achieve a desired characteristic impedance. In one embodiment, a first thin-film metal layer is formed on a planarized layer fabricated from multiple thin film dielectric layers. The reduced pad footprint in the first thin-film metal layer allows a major portion of the first thin-film metal layer to serve as a reference, or ground, plane to signal lines formed in a second thin-film metal layer that is separated from the first thin-film metal layer by a thin dielectric layer.

公开(公告)号：US20030071014A1

公开(公告)日：2003-04-17

申请号：US10155027

申请日：2002-05-28

Applicant: S&S Technology Corporation

Inventor： Chong-Ren Maa ,  Wan-Kuo Chih ,  Ming-Sung Tsai

IPC: C03C015/00 ,  B44C001/22

CPC classification number: H05K3/0041 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49894 ,  H01L2924/0002 ,  H05K3/0094 ,  H05K3/28 ,  H05K2201/0191 ,  H05K2201/0959 ,  H05K2203/0152 ,  H05K2203/0376 ,  H05K2203/0554 ,  H05K2203/066 ,  H05K2203/1152 ,  Y10T29/49126 ,  Y10T29/49144 ,  Y10T29/49147 ,  Y10T29/49149 ,  Y10T29/49151 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T428/24917 ,  H01L2924/00

Abstract: A solder mask manufacturing method adapted to apply a solder mask on a surface of a substrate of a circuit board, said surface is provided with a conductor pattern having an unsheltered portion and a sheltered portion which is covered by said solder mask. The method comprises the steps of: a) disposing a layer of semi-solid solder mask material having an expansion coefficient substantially the same as that of the substrate on the surface of said substrate to cover said copper conductor pattern, and a metal foil covering the material layer; b) applying pressure to the metal foil and applying baking treatment to cure the solder mask material in to solid; c) utilizing chemical solution and plasma etching to remove the metal foil and the solid solder mask material above the unsheltered portion of said copper conductor pattern respectively such that the unsheltered portion can be exposed; and d) using chemical solution to remove the residual metal foil.

公开(公告)号：US20030057265A1

公开(公告)日：2003-03-27

申请号：US09957532

申请日：2001-09-21

Inventor： Raiyomand F. Aspandiar ,  Tom E. Pearson ,  Christopher Combs

IPC: B23K031/02 ,  B23K035/12

CPC classification number: H05K3/3494 ,  B23K1/085 ,  B23K1/20 ,  B23K3/085 ,  B23K2101/42 ,  H05K3/3436 ,  H05K3/3468 ,  H05K2201/0129 ,  H05K2201/0959 ,  H05K2201/10734 ,  H05K2203/0455 ,  H05K2203/0776 ,  H05K2203/122 ,  Y02P70/613

Abstract: A method of wave soldering a circuit board while avoiding reflow of a solder joint on the topside of the board from heat conducted from the solder wave through at least one via in the board in heat conducting relation with the topside solder joint, comprises subjecting the circuit board to a solder wave and absorbing heat being conducted from the solder wave through the at least one via with an endothermic material in the via hole which undergoes a heat absorbing reaction. The heat absorbing reaction of the endothermic material is preferably a phase change, such as melting. The melted endothermic material is retained in the via hole during wave soldering by capillary forces and a cap on the lower end of the via hole. A disclosed method of making the circuit board includes locating the endothermic material in the via hole by inserting a preform of the endothermic material into the via hole or hot dispensing the endothermic material into the via hole. An electronic board product for practicing the method/made by the method is also disclosed.