公开(公告)号：US07897880B1

公开(公告)日：2011-03-01

申请号：US11999796

申请日：2007-12-07

Applicant: Joel R. Goergen ,  Greg Hunt ,  Peter Tomaszewski ,  Joseph Pankow ,  Michael Laudon

Inventor： Joel R. Goergen ,  Greg Hunt ,  Peter Tomaszewski ,  Joseph Pankow ,  Michael Laudon

IPC: H05K1/11

CPC classification number: H05K1/0237 ,  H05K1/0245 ,  H05K1/0251 ,  H05K1/116 ,  H05K1/165 ,  H05K3/429 ,  H05K2201/093 ,  H05K2201/09636 ,  H05K2201/0969 ,  H05K2201/09718

Abstract: Plated through holes pass through clearances in a ground plane of a circuit board. A conductive collar/spoke arrangement is constructed on the ground plane adjacent the clearance, to provide an inductive component to the coupling between a plated through hole and the ground plane. The inductive component impedes the transfer of high-frequency noise between the through hole and the ground plane. Other embodiments are also described and claimed.

Abstract translation: 电镀通孔通过电路板接地平面内的间隙。 在靠近间隙的接地平面上构造导电套环/辐条装置，以向电镀通孔和接地平面之间的耦合提供电感元件。 感应元件阻碍了通孔与接地面之间高频噪声的传递。 还描述和要求保护其他实施例。

公开(公告)号：US07868257B2

公开(公告)日：2011-01-11

申请号：US10598134

申请日：2005-03-09

Applicant: Taras Kushta ,  Kaoru Narita ,  Hirokazu Tohya ,  Takanori Saeki ,  Tomoyuki Kaneko

Inventor： Taras Kushta ,  Kaoru Narita ,  Hirokazu Tohya ,  Takanori Saeki ,  Tomoyuki Kaneko

IPC: H01R12/04 ,  H05K1/11

CPC classification number: H05K1/0222 ,  H05K1/0269 ,  H05K3/429 ,  H05K2201/09536 ,  H05K2201/09618 ,  H05K2201/09718 ,  H05K2201/09809

Abstract: A via transmission line for a multilayer printed circuit board (PCB) in which a wave guiding channel is formed by a signal via or a number of signal vias, an assembly of ground vias surrounding the signal via or corresponding number of coupled signal vias, a set of ground plates from conductor layers of the multilayer PCB, and a clearance hole. In this via transmission line, the signal via, or the number of signal vias forms an inner conductive boundary, ground vias and ground plates from conductor layers of the multilayer PCB form an outer conductive boundary, and the clearance hole provides both isolation of the inner conductive boundary from the outer conductive boundary and high-performance broadband operation of the via transmission line by means of the predetermined clearance hole cross-sectional shape and dimensions where the cross-sectional shape of the clearance hole is defined by the arrangement of ground vias in the outer conductive boundary and dimensions of the clearance hole are determined according to a method to minimize frequency-dependent return losses caused by specific corrugations of the outer conductive boundary formed by ground plates in the wave guiding channel of the via transmission line.

Abstract translation: 一种用于多层印刷电路板（PCB）的通孔传输线，其中通过信号通道或多个信号通路形成波导通道，围绕信号通孔或相应数量的耦合信号通孔的接地通孔的组件， 多层PCB的导体层的接地板组以及间隙孔。 在这个通过传输线路中，信号通孔或信号通道的数量形成内部导电边界，从多层PCB的导体层形成的接地孔和接地板形成外部导电边界，并且间隙孔提供内部 通过外部导电边界的导电边界和通孔传输线的高性能宽带操作，借助于预定的间隙孔横截面形状和尺寸，其中间隙孔的横截面形状由接地通孔的布置 根据通过在通孔传输线的波导通道中由接地板形成的外导电边界的特定波纹引起的频率相关的返回损耗的方法来确定间隙孔的外导电边界和尺寸。

公开(公告)号：US20100270644A1

公开(公告)日：2010-10-28

申请号：US12763412

申请日：2010-04-20

Applicant: Lynne E. Dellis ,  Karl Hartmann Dietz ,  David Ross McGregor

Inventor： Lynne E. Dellis ,  Karl Hartmann Dietz ,  David Ross McGregor

IPC: H01L27/08 ,  H01L21/50

CPC classification number: H05K1/162 ,  H01L2224/16225 ,  H05K3/025 ,  H05K2201/0175 ,  H05K2201/0355 ,  H05K2201/083 ,  H05K2201/09309 ,  H05K2201/09536 ,  H05K2201/09718 ,  H05K2201/10674 ,  H05K2203/104

Abstract: Disclosed are methods of making a semiconductor package comprising at least one thin-film capacitor embedded into at least one build-up layer of said semiconductor package. A thin-film capacitor is provided wherein the thin-film capacitor has a first electrode and a second electrode separated by a dielectric. A temporary carrier layer is applied to the first electrode and the second electrode is patterned. A PWB core and a build-up material are provided, and the build-up material is placed between the PWB core and the patterned second electrode of said thin-film capacitor. The patterned electrode side of the thin-film capacitor is laminated to the PWB core by way of the build-up material, the temporary carrier layer is removed, and the first electrode is patterned.

Abstract translation: 公开了制造半导体封装的方法，该半导体封装包括嵌入到所述半导体封装的至少一个堆积层中的至少一个薄膜电容器。 提供了一种薄膜电容器，其中薄膜电容器具有由电介质隔开的第一电极和第二电极。 临时载体层被施加到第一电极并且第二电极被图案化。 提供PWB芯和堆积材料，并且积聚材料被放置在PWB芯和所述薄膜电容器的图案化的第二电极之间。 薄膜电容器的图案化电极侧通过积聚材料层叠到PWB芯上，去除临时载体层，并对第一电极进行图案化。

公开(公告)号：US20100243310A1

公开(公告)日：2010-09-30

申请号：US12430131

申请日：2009-04-27

Applicant: YU-CHANG PAI ,  CHIEN-HUNG LIU ,  PO-CHUAN HSIEH

Inventor： YU-CHANG PAI ,  CHIEN-HUNG LIU ,  PO-CHUAN HSIEH

IPC: H05K1/11

CPC classification number: H05K1/116 ,  H05K1/0251 ,  H05K3/429 ,  H05K2201/09309 ,  H05K2201/09454 ,  H05K2201/09718 ,  H05K2201/09781

Abstract: A printed circuit board (PCB) includes a power layer, a ground layer, a through hole, and a conductor. The through hole goes through the power layer and the ground layer. The conductor includes a hollow columnar main body and an extending portion. The main body is formed in a bounding wall of the through hole, and is conductively connected to one of the power layer and the ground layer, and insulated from the other one of the power layer and the ground layer by an insulation area. The extending portion extends out from the circumferential surface of the main body. The extending portion extends into the insulation area and is insulated from the other one of the power layer and the ground layer, to increase an area of the power layer facing the ground layer.

Abstract translation: 印刷电路板（PCB）包括功率层，接地层，通孔和导体。 通孔穿过电源层和接地层。 导体包括中空柱状主体和延伸部分。 主体形成在通孔的边界壁中，并且与功率层和接地层中的一个导电连接，并且通过绝缘区域与功率层和接地层中的另一个绝缘。 延伸部分从主体的圆周表面伸出。 延伸部分延伸到绝缘区域中并与功率层和接地层中的另一个绝缘，以增加面向接地层的功率层的面积。

公开(公告)号：US20100200285A1

公开(公告)日：2010-08-12

申请号：US12763455

申请日：2010-04-20

Applicant: Takashi KARIYA ,  Hironori Tanaka

Inventor： Takashi KARIYA ,  Hironori Tanaka

IPC: H05K1/16 ,  C23C14/34 ,  H01G4/06 ,  H01G4/008

CPC classification number: H05K1/162 ,  H01L21/4867 ,  H01L23/498 ,  H01L23/50 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K3/388 ,  H05K3/4602 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/0195 ,  H05K2201/09309 ,  H05K2201/09536 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2201/09718 ,  Y10T29/43 ,  Y10T29/435 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49155 ,  H01L2924/00

Abstract: A method of producing a capacitor for a printed circuit board includes producing high-dielectric sheets and selecting ones of the high-dielectric sheets, which are substantially free from a defect after the heat process. Each of the high-dielectric sheets is produced by providing a first electrode, forming a first sputter film on the first electrode, forming an intermediate layer on the first sputter film by calcining a sol-gel film, forming a second sputter film on the intermediate layer, and providing a second electrode on the second sputter film. The high-dielectric sheets are subjected to a heat process in which the high-dielectric sheets are subjected to a first temperature at least once and a second temperature higher than the first temperature at least once.

Abstract translation: 一种印刷电路板用电容器的制造方法，其特征在于，制造高介电质片材，并选择在热处理后基本上不存在缺陷的高电介质片材。 每个高电介质片通过提供第一电极来制造，在第一电极上形成第一溅射膜，通过煅烧溶胶 - 凝胶膜在第一溅射膜上形成中间层，在中间层上形成第二溅射膜 并且在第二溅射膜上提供第二电极。 对高电介质片材进行热处理，其中高电介质片材经受至少一次的第一温度和比第一温度高至少一次的第二温度。

公开(公告)号：US07755911B2

公开(公告)日：2010-07-13

申请号：US12081503

申请日：2008-04-16

Applicant: Masaoki Yoshida ,  Takuya Nakayama ,  Koji Ueyama

Inventor： Masaoki Yoshida ,  Takuya Nakayama ,  Koji Ueyama

IPC: H01R9/00

CPC classification number: H05K1/116 ,  H05K1/0256 ,  H05K3/3447 ,  H05K2201/09363 ,  H05K2201/09463 ,  H05K2201/0969 ,  H05K2201/09718 ,  H05K2201/10651 ,  H05K2203/1446

Abstract: A printed wiring board which can certainly prevent damage of conductive pattern caused by the terminal. The printed wiring board has a board, a conductive pattern, a through-hole and a non-conductive area. A lead wire of resistance mounted on the printed wiring board is inserted into the through-hole 4. The lead wire projects from a surface of the board, and is bent close to the surface. The non-conductive area is formed into a fan-shaped shape enlarging toward a tip of the lead wire from a center of the through-hole. Because the bent lead wire is arranged on the non-conductive area, the non-conductive area can prevent damage of the conductive pattern which is caused by touching the lead wire to the conductive pattern.

Abstract translation: 可以防止端子引起的导电图案的损坏的印刷电路板。 印刷电路板具有基板，导电图案，通孔和非导电区域。 安装在印刷线路板上的电阻引线插入到通孔4中。引线从板的表面突出并且靠近表面弯曲。 非导电区域形成为从通孔的中心向引线的尖端扩大的扇形形状。 由于弯曲的引线布置在非导电区域上，所以非导电区域可以防止由引线接触导电图案而导致的导电图案的损坏。

公开(公告)号：US07755166B2

公开(公告)日：2010-07-13

申请号：US12401127

申请日：2009-03-10

Applicant: Takashi Kariya

Inventor： Takashi Kariya

IPC: H01L29/00

CPC classification number: H01G4/30 ,  H01G4/232 ,  H01L23/49822 ,  H01L23/50 ,  H01L23/66 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/13099 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/81192 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/01041 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01056 ,  H01L2924/01057 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H05K1/113 ,  H05K1/162 ,  H05K3/4652 ,  H05K2201/0175 ,  H05K2201/09518 ,  H05K2201/096 ,  H05K2201/09718 ,  H05K2203/0152 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: When a package substrate with a built-in capacitor includes a first thin-film small electrode 41aa and a second thin-film small electrode 42aa that are electrically short-circuited to each other via a pinhole P in a high-dielectric layer 43, a power supply post 61a and a via hole 61b are not formed in the first thin-film small electrode 41aa, and a ground post 62a and a via hole 62b are not formed in the second thin-film small electrode 42aa, either. As a result, the short-circuited small electrodes 41aa and 42aa are electrically connected to neither a power supply line nor a ground line, and become a potential independent from a power supply potential and a ground potential. Therefore, in the thin-film capacitor 40, only the portion where the short-circuited small electrodes 41aa and 42aa sandwich the high dielectric layer 43 loses the capacitor function, and portions where other thin-film small electrodes 41a and 42a sandwich the high dielectric layer 43 maintain the capacitor function.

公开(公告)号：US07705246B1

公开(公告)日：2010-04-27

申请号：US11965811

申请日：2007-12-28

Applicant: Jason Pritchard ,  Michael Gnieski

Inventor： Jason Pritchard ,  Michael Gnieski

IPC: H01R12/04 ,  H05K1/11

CPC classification number: H05K1/0245 ,  H05K1/0222 ,  H05K3/429 ,  H05K2201/09236 ,  H05K2201/09636 ,  H05K2201/09718

Abstract: A differential signal via structure for a printed circuit board having a pair of signal vias extending vertically from a surface of the board to an interior region of the board to contact signal conductors disposed horizontally within the interior region of the board and a pair of ground vias extending vertically from a surface of the circuit board to an interior region of the board to contact ground conductors disposed horizontally within the interior region of the board.

Abstract translation: 一种用于印刷电路板的差分信号通孔结构，其具有从板的表面垂直延伸到板的内部区域的一对信号通孔，以接触水平放置在板的内部区域内的信号导体和一对接地通孔 从电路板的表面垂直延伸到板的内部区域以接触水平地布置在板的内部区域内的接地导体。

公开(公告)号：US07663892B2

公开(公告)日：2010-02-16

申请号：US11449408

申请日：2006-06-07

Applicant: Don Chul Choi ,  Jae Cheol Ju ,  Dong Hwan Lee ,  Sang Soo Park ,  Hee Soo Yoon

Inventor： Don Chul Choi ,  Jae Cheol Ju ,  Dong Hwan Lee ,  Sang Soo Park ,  Hee Soo Yoon

IPC: H05K1/18

CPC classification number: H05K1/023 ,  H01L24/24 ,  H01L24/82 ,  H01L2224/24226 ,  H01L2224/82039 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01033 ,  H01L2924/0104 ,  H01L2924/01046 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/04941 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30107 ,  H05K1/0233 ,  H05K1/112 ,  H05K1/16 ,  H05K1/162 ,  H05K3/4611 ,  H05K2201/09309 ,  H05K2201/09454 ,  H05K2201/09718 ,  H05K2201/10022 ,  H05K2201/1003 ,  H01L2924/00

Abstract: Disclosed herein is a printed circuit board having an RF module power stage circuit embedded therein. Specifically, this invention relates to a printed circuit board having an RF module power stage circuit embedded therein, in which a terminal pad for a resistor, a bead, or an inductor is defined or formed on a power supply plane of a multilayered wired board to connect the resistor, the bead, or the inductor to the power supply plane, and the resistor, the bead, or the inductor is connected in parallel with a decoupling capacitor by using a via hole or by embedding the resistor, the bead or the inductor perpendicular to the power supply plane, thus decreasing the size of the RF module and improving the performance thereof.

公开(公告)号：US20100019859A1

公开(公告)日：2010-01-28

申请号：US12180815

申请日：2008-07-28

Applicant: Lance Dion Lascari

Inventor： Lance Dion Lascari

IPC: H01P5/02 ,  H01P3/08

CPC classification number: H01P1/047 ,  H05K1/0222 ,  H05K3/429 ,  H05K2201/09309 ,  H05K2201/09454 ,  H05K2201/09618 ,  H05K2201/09718

Abstract: A microstripline transmission line arrangement carries a signal having a fundamental frequency. The arrangement includes a first microstripline transmission line, a second microstripline transmission line, and a coaxial electrically conductive conduit interconnecting the first transmission line and the second transmission line. The conduit includes a signal conductor and an electrically grounded shield substantially surrounding the signal conductor. The conductor and the shield are positioned relative to each other to thereby comprise a means for lowpass filtering the signal. A cutoff frequency of the lowpass filtering is less than a third harmonic of the fundamental frequency.

Abstract translation: 微带线传输线路布置具有基频的信号。 该装置包括第一微带线传输线，第二微带线传输线和互连第一传输线和第二传输线的同轴导电导管。 导管包括信号导体和基本上围绕信号导体的电接地屏蔽。 导体和屏蔽件相对于彼此定位，从而包括用于对信号进行低通滤波的装置。 低通滤波的截止频率小于基频的三次谐波。