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    Low cost and high speed 3 load printed wiring board bus topology
    131.
    发明授权
    Low cost and high speed 3 load printed wiring board bus topology 失效

    公开(公告)号：US06561410B2

    公开(公告)日：2003-05-13

    申请号：US10116503

    申请日：2002-04-03

    Applicant: Sanjay Dabral ,  Ming Zeng

    Inventor： Sanjay Dabral ,  Ming Zeng

    IPC: B23K3102

    CPC classification number: H05K1/0246 ,  G06F13/4086 ,  H05K1/0298 ,  H05K1/181 ,  H05K2201/09236 ,  H05K2201/10545 ,  H05K2201/10689 ,  H05K2201/10734 ,  Y02P70/611 ,  Y10T29/49144 ,  Y10T29/49155

    Abstract: A multi layer printed circuit board with a 3-load topology is disclosed. First, second, and third integrated circuit (IC) printed wiring board packages having first, second, and third sets of terminals respectively are mounted on opposite sides of the board so that the second set of terminals are directly opposite the third set of terminals. Each package contains an IC die coupled to the respective set of terminals. The IC die in the first package is substantially identical to the one contained in the second package, and different than the one contained in the third package. For improved fanout of the metal lines that interconnect the first package to the second and third packages, each of the first, second, and third sets of terminals in the packages is arranged in substantially a U-shape. Each set of terminals has the same set of signal assignments of a parallel bus implemented by metal lines in the board. The 3-load topology is particularly useful for personal computer motherboard units having twin processors and a bridge chip set, yielding a motherboard having significantly lower number of metal layers, a faster bus and significantly improved noise margin, all with high density IC packages on a wide parallel bus.

    Electronic assembly with vertically connected capacitors and manufacturing method
    132.
    发明申请
    Electronic assembly with vertically connected capacitors and manufacturing method 失效
    具有垂直连接电容器的电子组装及制造方法

    公开(公告)号：US20020195700A1

    公开(公告)日：2002-12-26

    申请号：US09892273

    申请日：2001-06-26

    Applicant: Intel Corporation

    Inventor： Yuan-Liang Li

    IPC: H01L021/44 ,  H01L023/24 ,  H01L029/40

    CPC classification number: H05K1/185 ,  H01J9/326 ,  H01J61/368 ,  H01J61/86 ,  H01L2224/16 ,  H01L2924/15311 ,  H05K1/0231 ,  H05K1/112 ,  H05K3/4602 ,  H05K2201/10545 ,  H05K2201/10734

    Abstract: An electronic assembly includes one or more discrete capacitors (506, 804, 1204), which are vertically connected to a housing, such as an integrated circuit package (1704). Surface mounted capacitors (506) are vertically connected to pads (602) on a top or bottom surface of the package. Embedded capacitors (804, 1204) are vertically connected to vias (808, 816, 1210, and/or 1212) or other conductive structures within the package. Vertically connecting a surface mounted or embedded capacitor involves aligning (1604) side segments (416) of some of the capacitor's terminals with the conductive structures (e.g., pads, vias or other structures) so that the side of the capacitor upon which the side segments reside is substantially parallel with the top or bottom surface of the package. Where a capacitor includes extended terminals (1208), the capacitor can be embedded so that the extended terminals provide additional current shunts through the package.

    Abstract translation: 电子组件包括垂直连接到诸如集成电路封装（1704）的壳体的一个或多个分立电容器（506,804,1204）。 表面安装电容器（506）垂直连接到封装的顶表面或底表面上的焊盘（602）。 嵌入式电容器（804,1204）垂直连接到封装内的通孔（808,816,1210和/或1212）或其他导电结构。 垂直连接表面安装或嵌入式电容器包括使一些电容器端子的侧面区段（416）与导电结构（例如，焊盘，通孔或其他结构）对准（1604），使得电容器的侧面 驻极体基本上平行于包装的顶部或底部表面。 在电容器包括延伸端子（1208）的情况下，可以嵌入电容器，使得延伸端子通过封装件提供额外的电流分路。

    High integration electronic assembly and method
    133.
    发明申请
    High integration electronic assembly and method 失效
    高集成电子组装及方法

    公开(公告)号：US20020180259A1

    公开(公告)日：2002-12-05

    申请号：US09871192

    申请日：2001-05-31

    Applicant: TRW Inc.

    Inventor： Mark D. Haller

    IPC: B60T013/66

    CPC classification number: H01R12/526 ,  B60T8/3675 ,  H05K1/18 ,  H05K2201/10545

    Abstract: An assembly (20) comprises a circuit board (30), a first component (40), and a second component (50). The circuit board (30) has a planar first surface (32) and a planar second surface (34) opposite the first surface (32). The first component (40) has a first set of connectors (42). The first set of connectors (42) engages a corresponding set of apertures (36) in the first surface (32) of the circuit board (30). The second component (50) has a second set of mechanical one-way connectors (52). The second set of connectors (52) engages a corresponding set of apertures (38) in the second surface (34) of the circuit board (30). The circuit board (30) further has a normal axis (39) perpendicular to both the first and second surfaces (32, 34). The normal axis (39) passes through both the first and second components (40, 50).

    Abstract translation: 组件（20）包括电路板（30），第一部件（40）和第二部件（50）。 电路板（30）具有与第一表面（32）相对的平面第一表面（32）和平面第二表面（34）。 第一组件（40）具有第一组连接器（42）。 第一组连接器（42）接合在电路板（30）的第一表面（32）中的对应的一组孔（36）。 第二组件（50）具有第二组机械单向连接器（52）。 第二组连接器（52）接合在电路板（30）的第二表面（34）中的对应的一组孔（38）。 电路板（30）还具有垂直于第一和第二表面（32,34）两者的法向轴线（39）。 法线轴（39）穿过第一和第二部件（40,50）。

    Wiring board
    134.
    发明申请
    Wiring board 审中-公开
    接线板

    公开(公告)号：US20020086561A1

    公开(公告)日：2002-07-04

    申请号：US10012312

    申请日：2001-12-12

    Applicant: NGK SPARK PLUG CO., LTD.

    Inventor： Kouki Ogawa ,  Yasuhiro Sugimoto

    IPC: H05K001/00

    CPC classification number: H01L23/49822 ,  H01L23/49838 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2924/01078 ,  H01L2924/09701 ,  H01L2924/15192 ,  H01L2924/19105 ,  H01L2924/19106 ,  H05K1/0231 ,  H05K1/113 ,  H05K2201/10545 ,  H05K2201/10636 ,  H05K2201/10734 ,  Y02P70/611

    Abstract: A wiring board simplifying connection of electronic parts mounted on a principal face side of the wiring board and chip capacitors mounted on a reverse face side thereof in such a manner that the wiring board 100 mounting the chip capacitors 160 on a reverse face 101c-side comprises bumps 129 capable of being connected to IC chip 10, first and second capacitor connecting pads 149p, 149g connecting the upper face parts 163 of the chip capacitors 160, a plurality of insulating layers 121, 111, 141 intervening the first and the second capacitor connecting pads, and first and second converting-conductor layers 146p, 146g in stripe pattern formed at interlayer 152, connected to the bumps 129 at the principal face 101b-side, connected to the first capacitor connecting pads 149p at the reverse face 10c-side or the second capacitor connecting pads 149g for changing the connecting positions or the connecting number at the principal face side and the reverse face side.

    Abstract translation: 布线板简化安装在布线板的主面侧的电子部件和安装在其背面侧的贴片电容器的连接，使得将贴片电容器160安装在反面101c侧上的布线板100包括 能够连接到IC芯片10的突起129，连接片状电容器160的上表面部分163的第一和第二电容器连接焊盘149p，149g，插入第一和第二电容器连接的多个绝缘层121,111,141 焊盘以及连接到主表面101b侧的凸点129连接到反面10c侧的第一电容器连接焊盘149p的中间层152处形成的条纹图案的第一和第二转换导体层146p，146g， 用于改变连接位置的第二电容器连接焊盘149g或主面侧和反面侧的连接数。

    Sub-package bypass capacitor mounting for an array packaged integrated circuit
    135.
    发明授权
    Sub-package bypass capacitor mounting for an array packaged integrated circuit 有权
    用于阵列封装集成电路的子封装旁路电容器安装

    公开(公告)号：US06400576B1

    公开(公告)日：2002-06-04

    申请号：US09286250

    申请日：1999-04-05

    Applicant: Howard L. Davidson

    Inventor： Howard L. Davidson

    IPC: H05K702

    CPC classification number: H01L23/66 ,  H01L23/642 ,  H01L25/162 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2924/01057 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/3011 ,  H05K1/0231 ,  H05K1/112 ,  H05K2201/10325 ,  H05K2201/10545 ,  H05K2201/10704 ,  H05K2201/10734 ,  Y10T29/49128 ,  Y10T29/4913 ,  H01L2924/00

    Abstract: Switching noise within an LGA-packaged or PGA-packaged IC Vdd and IC Vss nodes is reduced by spreading the electrical current in the bypass path to reduce the effective current loop area, and thus reduce the energy stored in the magnetic field surrounding the current path. This result is achieved by minimizing the horizontal components of the linkage paths between the IC nodes to be bypassed and the bypass capacitor. Since effective inductance Leff seen by the bypass capacitor is proportional to magnetic energy, Leff is reduced over a broad band of frequencies. For each bypass capacitor, a pair of conductive vias is formed. A first via is coupled to the LGA package Vcc plane and to the IC Vdd node, and a second via is coupled to the LGA package Vss plane and to the IC Vss node. These vias preferably are spaced-apart a distance &Dgr;X corresponding to the distance between first and second connections on the bypass capacitor although sub-mm offsets in a via at connections may be used to accommodate differing connection pitches. The bypass capacitor connections are coupled to the lower surfaces of the first and second vias, at the lower surface of the LGA package. When the package is inserted into a socket, the bypass capacitor extends into at least some of the otherwise unused recess in the socket. Multiple bypass capacitors are accommodated by forming additional spaced-apart vias that may be electrically parallel-coupled.

    Abstract translation: 在LGA封装或PGA封装的IC Vdd和IC Vss节点中的开关噪声通过在旁路通路中扩展电流来减少有效电流环路面积，从而减少存储在电流路径周围的磁场中的能量 。 通过最小化待旁路的IC节点与旁路电容器之间的连接路径的水平分量来实现该结果。 由于旁路电容器看到的有效电感Leff与磁能成比例，所以Leff在宽频带上减小。 对于每个旁路电容器，形成一对导电通孔。 第一通孔耦合到LGA封装Vcc平面和IC Vdd节点，并且第二通孔耦合到LGA封装Vss平面和IC Vss节点。 这些通孔优选地间隔开对应于旁路电容器上的第一和第二连接之间的距离的距离DELTA，尽管连接处的通孔中的mm-mm偏移可以用于适应不同的连接间距。 旁路电容器连接在LGA封装的下表面处连接到第一和第二通孔的下表面。 当封装插入插座时，旁路电容器延伸到插座中的其他未使用的凹部中的至少一些。 多个旁路电容器通过形成可以电并联耦合的附加间隔开的通孔来容纳。

    Memory system for use on a circuit board in which the number of loads are minimized
    137.
    发明授权
    Memory system for use on a circuit board in which the number of loads are minimized 有权
    在负载数量最小化的电路板上使用的存储器系统

    公开(公告)号：US06362997B1

    公开(公告)日：2002-03-26

    申请号：US09690170

    申请日：2000-10-16

    Applicant: Larry Fiedler ,  Simon Thomas ,  Barry Wagner

    Inventor： Larry Fiedler ,  Simon Thomas ,  Barry Wagner

    IPC: H01L2348

    CPC classification number: G11C5/06 ,  H05K1/181 ,  H05K2201/09236 ,  H05K2201/10545 ,  Y02P70/611

    Abstract: A memory system is disclosed. The memory system comprises a circuit board and at least two memory devices mounted on the circuit board. Each of the at least two memory devices includes a plurality of pins for receiving and providing signals. At least a first portion of the pins of one of the at least two memory devices are coupled to at least a second portion of the pins of the other at least two memory devices such that a pair of the first portion coupled to a pin of the second portion forms a coupled load. The coupled load then appears as one load. Accordingly, in a system in accordance with the present invention, at least two memory devices are provided on a circuit board. Each of the at least two memory devices includes a plurality of pins. At least a portion of the pins of one of the two memory devices is in close proximity to and coupled to the at least a portion of the pins of the other of the at least two memory devices such that a pin and one memory device is coupled to a pin on the other memory device to form a coupled load. The coupled load then appears as one load. This is accomplished in a preferred embodiment by allowing the pins which are on opposite sides (front and back) of a printed circuit board to be represented as one load and then remapping one of the oppositely disposed pins to have the same functionality as the other oppositely disposed pin.

    Abstract translation: 公开了一种存储系统。 存储器系统包括电路板和安装在电路板上的至少两个存储器件。 所述至少两个存储器件中的每一个包括用于接收和提供信号的多个引脚。 至少两个存储器件中的一个的至少第一部分的引脚被耦合到另一个至少两个存储器件的引脚的至少第二部分，使得一对第一部分耦合到 第二部分形成耦合的负载。 耦合负载随后显示为一个负载。 因此，在根据本发明的系统中，至少两个存储器件设置在电路板上。 所述至少两个存储器件中的每一个包括多个引脚。 两个存储器件中的一个的至少一部分引脚紧邻并耦合到至少两个存储器件中的另一个的引脚的至少一部分，使得引脚和一个存储器件耦合 到另一个存储设备上的引脚以形成耦合的负载。 耦合负载随后显示为一个负载。 这在一个优选实施例中通过允许印刷电路板的相对侧（正面和背面）上的销被表示为一个负载，然后将相对设置的引脚中的一个重新映射以具有与另一个相反的功能来实现 销钉。

    SUB-PACKAGE BYPASS CAPACITOR MOUNTING FOR AN ARRAY PACKAGED INTEGRATED CIRCUIT
    138.
    发明申请
    SUB-PACKAGE BYPASS CAPACITOR MOUNTING FOR AN ARRAY PACKAGED INTEGRATED CIRCUIT 有权
    用于阵列封装的集成电路的子封装旁路电容器安装

    公开(公告)号：US20020027773A1

    公开(公告)日：2002-03-07

    申请号：US09286250

    申请日：1999-04-05

    Inventor： HOWARD L. DAVIDSON

    IPC: H05K007/06 ,  H01L023/12

    CPC classification number: H01L23/66 ,  H01L23/642 ,  H01L25/162 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2924/01057 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/3011 ,  H05K1/0231 ,  H05K1/112 ,  H05K2201/10325 ,  H05K2201/10545 ,  H05K2201/10704 ,  H05K2201/10734 ,  Y10T29/49128 ,  Y10T29/4913 ,  H01L2924/00

    Abstract: Switching noise within an LGA-packaged or PGA-packaged IC Vdd and IC Vss nodes is reduced by spreading the electrical current in the bypass path to reduce the effective current loop area, and thus reduce the energy stored in the magnetic field surrounding the current path. This result is achieved by minimizing the horizontal components of the linkage paths between the IC nodes to be bypassed and the bypass capacitor. Since effective inductance Leff seen by the bypass capacitor is proportional to magnetic energy, Leff is reduced over a broad band of frequencies. For each bypass capacitor, a pair of conductive vias is formed. A first via is coupled to the LGA package Vcc plane and to the IC Vdd node, and a second via is coupled to the LGA package Vss plane and to the IC Vss node. These vias preferably are spaced-apart a distance nullX corresponding to the distance between first and second connections on the bypass capacitor although sub-mm offsets in a via at connections may be used to accommodate differing connection pitches. The bypass capacitor connections are coupled to the lower surfaces of the first and second vias, at the lower surface of the LGA package. When the package is inserted into a socket, the bypass capacitor extends into at least some of the otherwise unused recess in the socket. Multiple bypass capacitors are accommodated by forming additional spaced-apart vias that may be electrically parallel-coupled.

    Abstract translation: 在LGA封装或PGA封装的IC Vdd和IC Vss节点中的开关噪声通过在旁路通路中扩展电流来减少有效电流环路面积，从而减少存储在电流路径周围的磁场中的能量 。 通过最小化待旁路的IC节点与旁路电容器之间的连接路径的水平分量来实现该结果。 由于旁路电容器看到的有效电感Leff与磁能成比例，所以Leff在宽频带上减小。 对于每个旁路电容器，形成一对导电通孔。 第一通孔耦合到LGA封装Vcc平面和IC Vdd节点，并且第二通孔耦合到LGA封装Vss平面和IC Vss节点。 这些通孔优选地间隔开对应于旁路电容器上的第一和第二连接之间的距离的距离DELTA，尽管连接处的通孔中的mm-mm偏移可以用于适应不同的连接间距。 旁路电容器连接在LGA封装的下表面处连接到第一和第二通孔的下表面。 当封装插入插座时，旁路电容器延伸到插座中的其他未使用的凹部中的至少一些。 多个旁路电容器通过形成可以电并联耦合的附加间隔开的通孔来容纳。

    Direct-chip-attach (DCA) multiple chip module (MCM) with repair-chip ready site to simplify assembling and testing process
    139.
    发明授权
    Direct-chip-attach (DCA) multiple chip module (MCM) with repair-chip ready site to simplify assembling and testing process 有权
    直接芯片连接（DCA）多芯片模块（MCM）具有修复芯片就绪现场，简化了组装和测试过程

    公开(公告)号：US06301121B1

    公开(公告)日：2001-10-09

    申请号：US09287218

    申请日：1999-04-05

    Applicant: Paul T. Lin

    Inventor： Paul T. Lin

    IPC: H05K702

    CPC classification number: H01L23/5382 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/15311 ,  H05K1/0292 ,  H05K1/0298 ,  H05K2201/10545 ,  H05K2201/10674 ,  H05K2201/10734 ,  H01L2924/00014

    Abstract: The present invention comprises a single-substrate multiple chip module (MCM) assembly. The MCM assembly includes a repair-package-site ready MCM board having a top surface and a bottom surface, the top surface further includes a plurality of chip connection trace lines include a chip-select line. The MCM assembly further includes a plurality of bare integrated circuit (IC) chips mounted directly on the top surface of the MCM board each chip connected to the plurality of chip connection trace lines on the top surface. The repair-package-site ready MCM board further includes at least a repair-package-site disposed on the bottom surface having a plurality of connection terminals arranged according to a standard repair packaged-chip footprint. Each of the connection terminals is connected to a via connector disposed in the MCM board for electrically connecting to the conductive trace lines on the top surface. The MCM assembly further includes a chip-select jumper means for disconnecting the chip select line for one of the bare IC chips as a disconnected chip and to connect to one of the repair-package-site provided for mounting a repair packaged-chip onto the bottom surface.

    Abstract translation: 本发明包括单片多芯片模块（MCM）组件。 MCM组件包括具有顶表面和底表面的修复包装现场准备的MCM板，顶表面还包括多个芯片连接迹线，包括芯片选择线。 MCM组件还包括直接安装在MCM板的顶表面上的多个裸芯片集成电路芯片，每个芯片连接到顶表面上的多个芯片连接迹线。 修理包装现场准备的MCM板还包括至少设置在底表面上的修理包装部位，其具有根据标准修复封装芯片占用面排列的多个连接端子。 每个连接端子连接到设置在MCM板中的通孔连接器，用于电连接到顶表面上的导电迹线。 MCM组件还包括芯片选择跳线装置，用于断开作为断开的芯片的裸IC芯片之一的芯片选择线，并连接到用于将修复封装芯片安装到所述修复包装部位上的一个 底面。

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