公开(公告)号：US08872334B2

公开(公告)日：2014-10-28

申请号：US13636324

申请日：2011-03-22

Applicant: Shintaro Yamamichi ,  Katsumi Kikuchi ,  Yoshiki Nakashima ,  Kentaro Mori

Inventor： Shintaro Yamamichi ,  Katsumi Kikuchi ,  Yoshiki Nakashima ,  Kentaro Mori

IPC: H01L23/48 ,  H01L23/538 ,  H05K3/46 ,  H05K1/18 ,  H01L23/00 ,  H01L23/66 ,  H01L23/498

CPC classification number: H05K1/185 ,  H01L23/49816 ,  H01L23/5384 ,  H01L23/5389 ,  H01L23/66 ,  H01L24/18 ,  H01L24/19 ,  H01L2224/04105 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/18 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73267 ,  H01L2224/82 ,  H01L2224/92244 ,  H01L2924/01004 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/3511 ,  H05K3/4605 ,  H05K2201/09581 ,  H05K2201/10674 ,  H05K2203/1469 ,  H01L2924/00

Abstract: In a manufacturing method of a semiconductor device incorporating a semiconductor element in a multilayered wiring structure including a plurality of wiring layers and insulating layers, a semiconductor element is mounted on a silicon support body whose thickness is reduced to a desired thickness and which are equipped with a plurality of through-vias running through in the thickness direction; an insulating layer is formed to embed the semiconductor element; then, a plurality of wiring layers is formed on the opposite surfaces of the silicon support body in connection with the semiconductor element. Thus, it is possible to reduce warping which occurs in proximity to the semiconductor element in manufacturing, thus improving a warping profile in the entirety of a semiconductor device. Additionally, it is possible to prevent semiconductor elements from becoming useless, improve a yield rate, and produce a thin-type semiconductor device with high-density packaging property.

Abstract translation: 在包括多个布线层和绝缘层的多层布线结构中的包含半导体元件的半导体器件的制造方法中，将半导体元件安装在硅支撑体上，该硅支撑体的厚度减小到期望的厚度并且配备有 多个穿过厚度方向的通孔; 形成绝缘层以嵌入半导体元件; 那么在与硅半导体元件相连的硅支撑体的相对表面上形成多个布线层。 因此，可以减少在制造中在半导体元件附近发生的翘曲，从而改善整个半导体器件的翘曲轮廓。 此外，可以防止半导体元件变得无用，提高成品率，并且可以生产具有高密度封装性能的薄型半导体器件。

公开(公告)号：US08870472B2

公开(公告)日：2014-10-28

申请号：US13676376

申请日：2012-11-14

Applicant: International Business Machines Corporation

Inventor： Stefano Sergio Oggioni ,  Jonas R. Weiss ,  Bert Jan Offrein

IPC: G02B6/36 ,  G02B6/13 ,  H05K1/18 ,  H05K1/02 ,  H05K13/00 ,  G02B6/43 ,  G02B6/42 ,  G02B6/38 ,  H05K3/34

CPC classification number: G02B6/42 ,  G02B6/13 ,  G02B6/3885 ,  G02B6/4214 ,  G02B6/43 ,  G02B2006/12166 ,  H05K1/0274 ,  H05K1/184 ,  H05K1/189 ,  H05K3/3405 ,  H05K13/00 ,  H05K2201/09081 ,  H05K2201/10121 ,  H05K2201/10674 ,  H05K2203/0195 ,  Y10T29/49002 ,  Y10T29/49037 ,  Y10T29/49124 ,  Y10T29/49826 ,  Y10T29/53

Abstract: A computer program product for fabricating an optical assembly, having a computer readable storage medium having computer readable program code embodied therewith, the computer readable program code includes a first computer readable program code configured to horizontally position a flexible portion of a substrate including a waveguide, the waveguide exposed at one end edge of the substrate; a second computer readable program code configured to bend the flexible portion of the substrate to place the waveguide exposed end in approximately a vertical position; a third computer readable program code configured to vertically position a flip-chip bonder bond head containing an optical component upon the waveguide exposed substrate edge to optically mate the optical component with the exposed waveguide; and a fourth computer readable program code configured to fixably mount the optical component to the substrate edge.

Abstract translation: 一种用于制造光学组件的计算机程序产品，具有计算机可读存储介质，其具有实施的计算机可读程序代码，所述计算机可读程序代码包括第一计算机可读程序代码，其被配置为水平地定位包括波导的基板的柔性部分， 所述波导在所述基板的一个端部边缘处暴露; 第二计算机可读程序代码，被配置为弯曲所述基板的柔性部分以将所述波导暴露端放置在大致垂直位置; 第三计算机可读程序代码，被配置为在所述波导暴露的基板边缘上垂直地定位包含光学部件的倒装焊接接合头，以将所述光学部件与所述暴露的波导光学匹配; 以及第四计算机可读程序代码，其被配置为将所述光学部件可固定地安装到所述基板边缘。

公开(公告)号：US20140313681A1

公开(公告)日：2014-10-23

申请号：US14321030

申请日：2014-07-01

Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.

Inventor： Takaharu YAMANO ,  Hajime IIZUKA ,  Hideaki SAKAGUCHI ,  Toshio KOBAYASHI ,  Tadashi ARAI ,  Tsuyoshi KOBAYASHI ,  Tetsuya KOYAMA ,  Kiyoaki IIDA ,  Tomoaki MASHIMA ,  Koichi TANAKA ,  Yuji KUNIMOTO ,  Takashi YANAGISAWA

IPC: H05K1/18

CPC classification number: H01L23/5389 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/56 ,  H01L21/563 ,  H01L21/565 ,  H01L21/6835 ,  H01L23/3114 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/552 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/85 ,  H01L24/97 ,  H01L25/105 ,  H01L25/16 ,  H01L25/162 ,  H01L2221/68345 ,  H01L2224/0401 ,  H01L2224/1134 ,  H01L2224/13144 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81005 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2224/83101 ,  H01L2224/83102 ,  H01L2224/83192 ,  H01L2224/85 ,  H01L2224/92125 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00011 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/07811 ,  H01L2924/12042 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19104 ,  H01L2924/19105 ,  H01L2924/207 ,  H01L2924/3025 ,  H01L2924/3511 ,  H05K1/185 ,  H05K1/186 ,  H05K3/20 ,  H05K3/4614 ,  H05K3/462 ,  H05K3/4644 ,  H05K2201/10007 ,  H05K2201/10378 ,  H05K2201/10674 ,  H05K2201/10977 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49146 ,  H01L2924/00

Abstract: An electronic part embedded substrate is disclosed. The electronic part embedded substrate includes a first substrate, a second substrate, an electronic part, an electrically connecting member, and a sealing member. A method of producing an electronic part embedded substrate is also disclosed. The method includes mounting an electronic part onto a first substrate, laminating a second substrate on the first substrate through an electrically connecting member; and filling a space between the first substrate and the second substrate with a sealing member to seal the electronic part.

Abstract translation: 公开了一种电子部件嵌入式基板。 电子部件嵌入式基板包括第一基板，第二基板，电子部件，电连接部件和密封部件。 还公开了一种制造电子部件嵌入式基板的方法。 该方法包括将电子部件安装到第一基板上，通过电连接部件将第二基板层压在第一基板上; 以及用密封构件填充第一基板和第二基板之间的空间以密封电子部件。

公开(公告)号：US20140311771A1

公开(公告)日：2014-10-23

申请号：US14247355

申请日：2014-04-08

Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.

Inventor： Noriyoshi SHIMIZU ,  Hitoshi SAKAGUCHI ,  Wataru KANEDA ,  Masato TANAKA ,  Akio ROKUGAWA

IPC: H05K1/02

CPC classification number: H05K1/0298 ,  H01L23/5383 ,  H01L23/5384 ,  H01L2924/0002 ,  H05K1/0271 ,  H05K1/112 ,  H05K1/181 ,  H05K3/4007 ,  H05K3/4602 ,  H05K3/4644 ,  H05K2201/0195 ,  H05K2201/0367 ,  H05K2201/10674 ,  H05K2203/025 ,  H01L2924/00

Abstract: A wiring board includes first insulating layers and second insulating layers formed on a core layer in this order; a third insulating layer and a solder resist layer formed on another surface of the core layer in this order, first wiring layers and second wiring layers formed in the first insulating layers and the second insulating layers, respectively, wherein a first end surface of the first via wiring exposes from the first surface of the outermost first insulating layer to be directly connected with an outermost second wiring layer, the first via wiring and the outermost second wiring layer being separately formed, the first surface of the outermost first insulating layer and the first end surface of the first via wiring are polished surfaces, smooth surfaces and are flush with each other, and the wiring density of the second wiring layers is higher than that of the first wiring layers.

Abstract translation: 布线板依次包括在芯层上形成的第一绝缘层和第二绝缘层; 依次形成在芯层的另一表面上的第三绝缘层和阻焊层，分别形成在第一绝缘层和第二绝缘层中的第一布线层和第二布线层，其中第一绝缘层和第一绝缘层的第一端面 通过布线从最外侧的第一绝缘层的第一表面暴露出来，与最外层的第二布线层直接连接，第一通孔布线和最外层的第二布线层被分开地形成，最外面的第一绝缘层的第一表面和第一 第一通孔布线的端面是抛光表面，光滑的表面并且彼此齐平，并且第二布线层的布线密度高于第一布线层的布线密度。

公开(公告)号：US08866021B2

公开(公告)日：2014-10-21

申请号：US13614630

申请日：2012-09-13

Applicant: Hidenobu Nishikawa ,  Daido Komyoji

Inventor： Hidenobu Nishikawa ,  Daido Komyoji

IPC: H05K1/00

CPC classification number: H05K3/321 ,  G06K19/07749 ,  H01L21/6835 ,  H01L23/49855 ,  H01L24/11 ,  H01L24/12 ,  H01L24/28 ,  H01L24/29 ,  H01L24/83 ,  H01L24/90 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/11001 ,  H01L2224/11003 ,  H01L2224/1134 ,  H01L2224/1182 ,  H01L2224/13099 ,  H01L2224/13144 ,  H01L2224/16225 ,  H01L2224/29036 ,  H01L2224/2929 ,  H01L2224/29299 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/83192 ,  H01L2224/838 ,  H01L2224/90 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0781 ,  H01L2924/14 ,  H05K1/189 ,  H05K3/305 ,  H05K2201/10674 ,  H05K2201/10977 ,  H05K2201/10984 ,  Y10T29/49002 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49146 ,  H01L2924/00015 ,  H01L2924/00 ,  H01L2224/29099 ,  H01L2224/29199 ,  H01L2224/05599

Abstract: The invention includes: applying an anisotropic conductive resin including conductive particles only to a plurality of bumps of an electronic component; placing the electronic component above a main surface of a flexible wiring board via the anisotropic conductive resin; and pressurizing the electronic component to the wiring board and curing the anisotropic conductive resin applied to the plurality of bumps to join the plurality of bumps to the electrodes of the wiring board. This can prevent a defective mounting of the electronic component.

Abstract translation: 本发明包括：将仅包含导电颗粒的各向异性导电树脂施加到电子部件的多个凸块; 通过各向异性导电树脂将电子部件放置在柔性布线板的主表面上方; 并将所述电子部件加压到所述布线基板，并固化施加到所述多个凸块的各向异性导电树脂，以将所述多个凸块接合到所述布线板的电极。 这可以防止电子部件的安装不良。

公开(公告)号：US08853557B2

公开(公告)日：2014-10-07

申请号：US12893142

申请日：2010-09-29

Applicant: Hidetoshi Yugawa

Inventor： Hidetoshi Yugawa

IPC: H05K1/03 ,  H05K1/09 ,  H05K3/42 ,  H05K3/46 ,  H05K3/38

CPC classification number: H05K3/388 ,  H05K3/381 ,  H05K3/421 ,  H05K3/4602 ,  H05K3/4644 ,  H05K2201/0175 ,  H05K2201/0323 ,  H05K2201/10674 ,  H05K2203/095

Abstract: A circuit board provided with a first resin layer and with a first conductive layer formed on the first resin layer. The first conductive layer has a metal carbide layer containing a carbide of a transition metal selected from Group IV, Group V, or Group VI in the Periodic Table and bonded to the first resin layer. The first resin layer has a first region to which the metal carbide layer is bonded and a second region located in an inner portion of the first resin layer from the first region. The first region has a larger ratio of number of atoms of nitrogen relative to number of atoms of carbon than in the second region.

Abstract translation: 一种具有第一树脂层和形成在第一树脂层上的第一导电层的电路板。 第一导电层具有包含周期表中选自IV族，V族或VI族的过渡金属的碳化物并与第一树脂层结合的金属碳化物层。 第一树脂层具有接合金属碳化物层的第一区域和位于第一区域的第一树脂层的内部的第二区域。 第一区域的氮原子数相对于碳原子数的比例大于第二区域。

公开(公告)号：US20140291866A1

公开(公告)日：2014-10-02

申请号：US13852876

申请日：2013-03-28

Applicant: Toong Erh Ooi ,  Bok Eng Cheah ,  Nitesh Nimkar

Inventor： Toong Erh Ooi ,  Bok Eng Cheah ,  Nitesh Nimkar

IPC: H01L23/498 ,  H01L23/00

CPC classification number: H01L24/82 ,  H01L21/4846 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/498 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/50 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/24 ,  H01L24/73 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/82005 ,  H01L2224/82039 ,  H01L2224/821 ,  H01L2224/82345 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2225/1076 ,  H01L2924/12042 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18162 ,  H05K1/185 ,  H05K3/4682 ,  H05K2201/10674 ,  H01L2924/00012 ,  H01L2924/00

Abstract: An apparatus including a die; and a build-up carrier including alternating layers of conductive material and dielectric material disposed on a device side of the die and dielectric material embedding a portion of a thickness dimension of the die; and a plurality of carrier contact points disposed at a gradation between the device side of the die and the embedded thickness dimension of the die and configured for connecting the carrier to a substrate. A method including disposing a die on a sacrificial substrate with a device side of the die opposite the sacrificial substrate; forming a build-up carrier adjacent a device side of a die, wherein the build-up carrier includes a dielectric material defining a gradation between the device side of the die and a backside of the die, the gradation including a plurality of carrier contact points; and separating the die and the carrier from the sacrificial substrate.

Abstract translation: 一种包括模具的设备; 以及堆叠载体，其包括设置在所述管芯的器件侧上的交替的导电材料层和介电材料层，以及包埋所述管芯的厚度尺寸的一部分的电介质材料; 以及多个载体接触点，其设置在所述管芯的器件侧和所述管芯的嵌入的厚度尺寸之间的灰度处，并且被配置为将所述载体连接到衬底。 一种方法，包括在牺牲衬底上设置管芯，其中模具的器件侧与牺牲衬底相对; 在模具的器件侧附近形成堆积载体，其中所述积聚载体包括在所述管芯的器件侧和所述管芯的背面之间限定灰度的介电材料，所述等级包括多个载体接触点 ; 以及将所述管芯和所述载体与所述牺牲衬底分离。

公开(公告)号：US20140268574A1

公开(公告)日：2014-09-18

申请号：US14290173

申请日：2014-05-29

Applicant: FUJIKURA LTD.

Inventor： Kazuhisa Itoi ,  Masahiro Okamoto

IPC: H05K1/02 ,  H05K3/10

CPC classification number: H05K3/10 ,  H01L21/4857 ,  H01L23/367 ,  H01L23/3677 ,  H01L23/5389 ,  H01L24/19 ,  H01L2224/02311 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05569 ,  H01L2224/08237 ,  H01L2224/11312 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/11416 ,  H01L2224/11418 ,  H01L2224/12105 ,  H01L2224/13009 ,  H01L2224/1329 ,  H01L2224/13294 ,  H01L2224/13309 ,  H01L2224/13311 ,  H01L2224/13313 ,  H01L2224/13316 ,  H01L2224/13324 ,  H01L2224/13339 ,  H01L2224/13344 ,  H01L2224/13347 ,  H01L2224/13355 ,  H01L2224/1336 ,  H01L2224/1339 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/16503 ,  H01L2224/2929 ,  H01L2224/32225 ,  H01L2224/73201 ,  H01L2224/73251 ,  H01L2224/73253 ,  H01L2224/80203 ,  H01L2224/80447 ,  H01L2224/80903 ,  H01L2224/81192 ,  H01L2224/81203 ,  H01L2224/8185 ,  H01L2224/81862 ,  H01L2224/81907 ,  H01L2224/83192 ,  H01L2224/83203 ,  H01L2224/8349 ,  H01L2224/8385 ,  H01L2224/83862 ,  H01L2224/9211 ,  H01L2224/9221 ,  H01L2924/07811 ,  H01L2924/12042 ,  H01L2924/15153 ,  H05K1/0206 ,  H05K1/0207 ,  H05K1/186 ,  H05K3/0061 ,  H05K3/4602 ,  H05K3/4614 ,  H05K2201/0969 ,  H05K2201/10674 ,  Y10T29/49126 ,  H01L2924/00014 ,  H01L2924/0665 ,  H01L2924/0635 ,  H01L2924/069 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2224/80 ,  H01L2224/16 ,  H01L2224/08 ,  H01L2224/32 ,  H01L2924/00

Abstract: A component built-in board comprises stacked therein a plurality of printed wiring bases having a wiring pattern and a via formed on/in a resin base thereof, and comprises an electronic component built in thereto, wherein at least a portion of the plurality of printed wiring bases include a thermal wiring in the wiring pattern and include a thermal via in the via, at least one of the plurality of printed wiring bases has formed therein an opening where the electronic component is built, and has formed therein a heat-conducting layer and closely attached to a surface on an opposite side to an electrode formation surface of the electronic component built in to the opening, and the electronic component is fixed in the opening by an adhesive layer stacked on the heat-conducting layer, via a hole formed in a region facing onto the opening of the heat-conducting layer.

Abstract translation: 一种组件内置板，其中堆叠有多个印刷布线基底，其具有形成在其树脂基底上的布线图案和通孔，并且包括内置于其中的电子部件，其中多个印刷的至少一部分 布线基底包括布线图案中的热布线，并且在通孔中包括热通孔，多个印刷布线基底中的至少一个在其中形成有电子部件构建的开口，并且在其中形成有导热层 并且紧贴在与内置于开口部的电子部件的电极形成面相反一侧的面上，电子部件通过形成有孔的层叠在导热层上的粘接层固定在开口部 在面向导热层的开口的区域中。

公开(公告)号：US08826527B2

公开(公告)日：2014-09-09

申请号：US13620153

申请日：2012-09-14

Applicant: Jin Seon Park

Inventor： Jin Seon Park

IPC: H05K3/30 ,  H01L23/498 ,  H01L23/13 ,  H05K1/18 ,  H01L21/48 ,  H01L23/538 ,  H01L23/00 ,  H05K3/46

CPC classification number: H05K1/185 ,  H01L21/4846 ,  H01L23/13 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/24 ,  H01L2224/18 ,  H05K3/4602 ,  H05K2201/10674 ,  H05K2203/0191 ,  Y10T29/4913 ,  Y10T29/49139 ,  Y10T29/49146 ,  Y10T29/49155

Abstract: Disclosed herein is a printed circuit board, including: a substrate including an insulation layer in which a cavity is formed; an electronic component mounted in the cavity of the substrate and having connection terminals; an insulation material layer formed on one side of the substrate to bury the electronic component; a first circuit layer formed on the other side of the substrate and including a connection pattern connecting with the connection terminals of the electronic component; and a second circuit layer formed on the insulation material layer. The printed circuit board is advantageous in that it can prevent the warpage thereof and ensure the reliability of electrical connection between an electronic component and a circuit layer by adjusting the thickness, thermal expansion coefficient and elastic modulus of insulation layer or the insulating material.

Abstract translation: 本文公开了一种印刷电路板，包括：基板，包括其中形成空腔的绝缘层; 安装在基板的空腔中并具有连接端子的电子部件; 绝缘材料层，形成在所述基板的一侧以埋置所述电子部件; 形成在所述基板的另一侧上并包括与所述电子部件的连接端子连接的连接图案的第一电路层; 以及形成在所述绝缘材料层上的第二电路层。 印刷电路板的优点在于可以通过调节绝缘层或绝缘材料的厚度，热膨胀系数和弹性模量来防止其翘曲并确保电子部件和电路层之间的电连接的可靠性。

公开(公告)号：US20140225257A1

公开(公告)日：2014-08-14

申请号：US14258300

申请日：2014-04-22

Applicant: STATS ChipPAC, Ltd.

Inventor： Rajendra D. Pendse

IPC: H01L23/00 ,  H01L23/488

CPC classification number: H01L24/14 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/488 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/48 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/13016 ,  H01L2224/13023 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16 ,  H01L2224/48105 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/4823 ,  H01L2224/73203 ,  H01L2224/73265 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15174 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H05K3/3436 ,  H05K3/3452 ,  H05K2201/09909 ,  H05K2201/10674 ,  Y02P70/613 ,  H01L2924/0105 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A semiconductor device has a semiconductor die with die bump pads and substrate with trace lines having integrated bump pads. A solder mask patch is formed interstitially between the die bump pads or integrated bump pads. The solder mask patch contains non-wettable material. Conductive bump material is deposited over the integrated bump pads or die bump pads. The semiconductor die is mounted over the substrate so that the conductive bump material is disposed between the die bump pads and integrated bump pads. The bump material is reflowed without a solder mask around the integrated bump pads to form an interconnect between the semiconductor die and substrate. The solder mask patch confines the conductive bump material within a footprint of the die bump pads or integrated bump pads during reflow. The interconnect can have a non-fusible base and fusible cap.

Abstract translation: 半导体器件具有具有管芯凸块焊盘的半导体管芯和具有集成凸块焊盘的迹线的衬底。 在芯片凸块焊盘或集成凸块焊盘之间间隙地形成焊接掩模贴片。 焊接掩模贴片包含不可润湿的材料。 导电凸块材料沉积在集成的凸块焊盘或模具凸块焊盘上。 半导体管芯安装在衬底上，使得导电凸块材料设置在管芯凸块焊盘和集成凸块焊盘之间。 凸块材料在集成的凸块焊盘周围没有焊接掩模的情况下回流以形成半导体管芯和衬底之间的互连。 焊接掩模贴片将导电凸块材料限制在回流焊中芯片凸块焊盘或集成凸块焊盘的占位面积内。 互连可以具有不可熔的基底和易熔盖。