公开(公告)号：US09650237B2

公开(公告)日：2017-05-16

申请号：US14778514

申请日：2014-04-17

Applicant: Agency for Science, Technology and Research

Inventor： Ilker E. Ocak ,  Julius Ming Lin Tsai ,  Navab Singh

IPC: B81B7/00 ,  H01L25/00 ,  G01C19/56 ,  G01R33/00 ,  G01R33/028 ,  G01P15/08 ,  G01P15/125 ,  B81C1/00

CPC classification number: B81B7/0048 ,  B81B2201/0235 ,  B81B2201/0242 ,  B81B2201/0271 ,  B81B2201/0292 ,  B81B2203/04 ,  B81B2207/07 ,  B81C1/00285 ,  B81C2203/0118 ,  B81C2203/0172 ,  G01C19/56 ,  G01P15/0802 ,  G01P15/125 ,  G01P2015/0814 ,  G01P2015/0828 ,  G01R33/00 ,  G01R33/0052 ,  G01R33/0286 ,  H01L25/00 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An electromechanical device and method of fabrication thereof comprising: providing a first wafer with a circuit arrangement on a first surface thereof and a first electrode on a second surface thereof; forming first and second via structures from the first surface to the second surface of the first wafer, said first via electrically connecting the first electrode with the circuit arrangement; providing a second wafer with a suspended structure on a first surface thereof; forming a second electrode on the suspended structure; forming an interconnect structure on the first surface of the second wafer that electrically connects with the second electrode; bonding the first wafer to the second wafer with the second surface of the first wafer facing the first surface of the second wafer, with the second via structure electrically connecting the circuit arrangement to the interconnect structure, and the first and second electrodes forming a capacitive structure.

公开(公告)号：US09641153B2

公开(公告)日：2017-05-02

申请号：US14932303

申请日：2015-11-04

Applicant: Infineon Technologies Dresden GmbH

Inventor： Thoralf Kautzsch ,  Heiko Froehlich ,  Mirko Vogt ,  Maik Stegemann ,  Thomas Santa ,  Markus Burian

IPC: H03H9/24 ,  H03H9/02 ,  B81B3/00 ,  B81C1/00 ,  H03H3/007

CPC classification number: H03H9/2452 ,  B81B3/0078 ,  B81B2201/0271 ,  B81C1/00158 ,  B81C1/00246 ,  B81C1/00301 ,  B81C1/00396 ,  B81C2203/0145 ,  H03H3/0072 ,  H03H3/0073 ,  H03H9/02259 ,  H03H9/2463 ,  H03H2009/02291 ,  H03H2009/02307 ,  H03H2009/0233 ,  H03H2009/02496

Abstract: A method of forming a resonator by providing a first layer; forming a sacrificial layer on the first layer; forming a capping layer on the sacrificial layer; forming at least one etching aperture in the capping layer; forming at least one additional aperture having a different size than the at least one etching aperture; forming a cavity and releasing a resonator structure within the cavity by removing the sacrificial layer by etching via the at least one etching aperture; sealing the at least one etching aperture; and forming a lining in the at least one additional aperture.

公开(公告)号：US09631929B2

公开(公告)日：2017-04-25

申请号：US15037532

申请日：2014-10-21

Applicant: SAFRAN ELECTRONICS & DEFENSE

Inventor： Alain Jeanroy ,  Philippe Onfroy

IPC: G01C19/574 ,  G01C19/5769 ,  G01C19/5733 ,  B81B3/00 ,  B81C1/00

CPC classification number: G01C19/574 ,  B81B3/0021 ,  B81B2201/0242 ,  B81B2201/0271 ,  B81B2203/0109 ,  B81C1/00547 ,  B81C2201/013 ,  G01C19/5733 ,  G01C19/5769

Abstract: An inertial sensor comprising a frame to which at least two seismic bodies are connected by resilient means so as to be movable in a suspension plane, and transducers to keep the seismic bodies vibrating and to determine a relative movement of the seismic bodies relative to one another, characterized in that the seismic bodies have a single shape and a single mass, and in that the seismic bodies comprise interlocking parts such that the seismic bodies are nested inside one another while being movable in the suspension plane relative to the other of the seismic bodies, with the seismic bodies having centers of gravity that coincide with one another. A method for manufacturing such a sensor.

公开(公告)号：US09612040B2

公开(公告)日：2017-04-04

申请号：US14362285

申请日：2012-11-29

Applicant: Commissariat à l'énergie atomique et aux énergies alternatives

Inventor： Fabrice Casset

IPC: F24J3/00 ,  F03G7/06 ,  B81B3/00 ,  H02N2/18 ,  H01L41/113

CPC classification number: F24V99/00 ,  B81B3/0024 ,  B81B3/0081 ,  B81B2201/0271 ,  B81B2201/031 ,  B81B2201/032 ,  F03G7/06 ,  H01L41/1136 ,  H02N2/18

Abstract: A device for generating a second temperature variation ΔT2 from a first use temperature variation ΔT1, includes an elastocaloric material layer, having an internal temperature which is able to vary by ΔT2 in response to a given mechanical stress variation Δσ applied to the elastocaloric material layer. The variation Δσ being induced by the first use temperature variation ΔT1 There is a suspended element in mechanical contact with the elastocaloric material layer so as to apply to this layer a mechanical stress that varies in response to the use temperature variation ΔT1. The suspended element is arranged so as to make the mechanical stress applied to the elastocaloric material layer vary by Δσ in response to the temperature variation ΔT1, to generate the second temperature variation ΔT2.

公开(公告)号：US09564836B2

公开(公告)日：2017-02-07

申请号：US14129908

申请日：2012-06-26

Applicant: Seung-Mok Lee

Inventor： Seung-Mok Lee

IPC: H02N1/00 ,  G01N29/24 ,  B06B1/02 ,  B81C1/00 ,  G01H11/06 ,  H01L29/84

CPC classification number: H02N1/00 ,  B06B1/0292 ,  B81B2201/0271 ,  B81B2207/015 ,  B81C1/00246 ,  B81C2203/031 ,  B81C2203/075 ,  G01H11/06 ,  G01N29/2406 ,  H01L29/84

Abstract: A transducer, and a method for manufacturing the transducer are provided. The transducer includes a substrate-side electrode provided in one side of an insulative substrate and an opposite plate including an opposite electrode disposed opposite to the substrate-side electrode, and which performs a function such as a reduction in impedance, conversion of capacitance, signal amplification, thereby achieving size reduction of the transducer itself. An upper plate is made of a silicon monocrystal and is arranged so as to face a substrate-side electrode. In the upper plate, an integrated circuit section which is an impurity region of an IC circuit is formed by a thermal diffusion method or an ion implantation method. By this transducer, an improvement in conversion efficiency, an improvement in productivity, and a size reduction of a mount system are achieved.

Abstract translation: 提供换能器和用于制造换能器的方法。 换能器包括设置在绝缘基板的一侧的基板侧电极和与基板侧电极相对设置的相对电极的相对板，并且其执行阻抗减小，电容转换，信号 从而实现换能器本身的尺寸减小。 上板由硅单晶制成，并与基板侧电极相对配置。 在上板中，通过热扩散法或离子注入法形成作为IC电路的杂质区域的集成电路部。 通过该传感器，实现了转换效率的提高，生产率的提高和安装系统的尺寸减小。

公开(公告)号：US20170033049A1

公开(公告)日：2017-02-02

申请号：US15206926

申请日：2016-07-11

Applicant: SEIKO EPSON CORPORATION

Inventor： Takahiko YOSHIZAWA

IPC: H01L23/535 ,  H01L21/3105 ,  H01L23/532 ,  H01L21/306 ,  H01L21/3065

CPC classification number: H01L21/31053 ,  B81B2201/0271 ,  B81C1/00293 ,  B81C2203/0136 ,  B81C2203/0145 ,  H01L23/53214

Abstract: An electronic apparatus according to the invention includes a substrate, a side wall that is disposed directly on the substrate or via an insulation film and forms a hollow, a functional element that is disposed within the hollow, a first layer that is disposed on the side wall so as to cover the hollow and has a first through hole that communicates with the hollow, a second layer that is disposed on the first layer so as to cover the hollow and has a second through hole that has a diameter smaller than a diameter of the first through hole and at least partially overlaps the first through hole as viewed in plan view, and a third layer that is disposed on the second layer so as to seal at least the second through hole.

Abstract translation: 根据本发明的电子设备包括基板，侧壁，其直接设置在基板上或经由绝缘膜形成中空的功能元件，其设置在中空部内，第一层设置在侧面 壁，以覆盖中空部并具有与中空部连通的第一通孔，第二层设置在第一层上以覆盖中空部，并具有直径小于直径的第二通孔 第一通孔并且在平面图中至少部分地与第一通孔重叠，以及设置在第二层上以至少密封第二通孔的第三层。

公开(公告)号：US20170022052A1

公开(公告)日：2017-01-26

申请号：US15125070

申请日：2014-10-13

Applicant: INDUSTRY-UNIVERSITY COOPERATION FOUNDATION SOGANG UNIVERSITY

Inventor： Jung Chul LEE ,  Joo Hyun KIM

IPC: B81C1/00 ,  G01N29/02 ,  G01N29/036 ,  G01N5/00

CPC classification number: B81C1/00071 ,  B81B2201/0271 ,  B81B2201/058 ,  B81C1/0015 ,  G01N5/00 ,  G01N9/002 ,  G01N29/022 ,  G01N29/036 ,  G01N2291/0256 ,  H01L31/0352

Abstract: Provided is a method for manufacturing a microchannel resonator capable of measuring a mass and characteristics of an object using a principle in which a resonance frequency is changed according to a mass of a moving material, the method including: providing a silicon substrate; forming a cavity channel inside the silicon substrate; forming a hollow silicon oxide structure on the inner wall surface of the cavity channel by oxidizing the inner wall surface of the cavity channel; and partially removing the periphery of the hollow silicon oxide structure such that the hollow silicon oxide structure can resonate with respect to the silicon substrate.

Abstract translation: 提供一种用于制造能够使用根据移动材料的质量改变共振频率的原理来测量物体的质量和特性的微通道谐振器的方法，所述方法包括：提供硅衬底; 在硅衬底内形成空腔通道; 通过氧化空腔通道的内壁表面在空腔通道的内壁表面上形成中空氧化硅结构; 并且部分地去除中空氧化硅结构的周边，使得中空氧化硅结构可以相对于硅衬底共振。

公开(公告)号：US20160362293A1

公开(公告)日：2016-12-15

申请号：US14738745

申请日：2015-06-12

Applicant: InvenSense, Inc.

Inventor： Peter SMEYS ,  Martin LIM

IPC: B81B7/00

CPC classification number: B81B7/007 ,  B81B2201/0207 ,  B81B2201/0214 ,  B81B2201/0228 ,  B81B2201/0235 ,  B81B2201/0242 ,  B81B2201/0257 ,  B81B2201/0264 ,  B81B2201/0271 ,  B81B2201/0278 ,  B81B2203/0315 ,  B81B2207/012 ,  B81C1/00238 ,  B81C2203/0785 ,  B81C2203/0792 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: A sensor chip combining a substrate comprising at least one CMOS circuit, a MEMS substrate and another substrate comprising at least one CMOS circuit in one package that is vertically stacked is disclosed. The package comprises a sensor chip further comprising a first substrate with a first surface and a second surface comprising at least one CMOS circuit; a MEMS substrate with a first surface and a second surface; and a second substrate comprising at least one CMOS circuit. Where the first surface of the first substrate is attached to a packaging substrate and the second surface of the first substrate is attached to the first surface of the MEMS substrate. The second surface of the MEMS substrate is attached to the second substrate. The first substrate, the MEMS substrate, the second substrate and the packaging substrate are mechanically attached and provided with electrical inter-connects.

Abstract translation: 公开了一种传感器芯片，其组合包括至少一个CMOS电路，MEMS基板和包括垂直堆叠的一个封装中的至少一个CMOS电路的另一基板的基板。 所述封装包括传感器芯片，还包括具有第一表面的第一基板和包括至少一个CMOS电路的第二表面; 具有第一表面和第二表面的MEMS衬底; 以及包括至少一个CMOS电路的第二衬底。 其中第一衬底的第一表面附接到封装衬底，并且第一衬底的第二表面附接到MEMS衬底的第一表面。 MEMS基板的第二表面附接到第二基板。 第一基板，MEMS基板，第二基板和封装基板机械地连接并设置有电连接。

公开(公告)号：US09510069B2

公开(公告)日：2016-11-29

申请号：US14276930

申请日：2014-05-13

Applicant: CANON KABUSHIKI KAISHA

Inventor： Toshio Tomiyoshi ,  Kazutoshi Torashima ,  Takahiro Akiyama

IPC: H02N1/00 ,  H04R19/00 ,  H04R1/00 ,  B06B1/02 ,  B81C1/00

CPC classification number: H04R1/00 ,  B06B1/0292 ,  B81B2201/0271 ,  B81B2203/04 ,  B81C1/00626 ,  H04R2201/003

Abstract: An electromechanical transducer includes a substrate, a first electrode disposed on the substrate, and a vibration film including a membrane disposed on the first electrode with a space therebetween and a second electrode disposed on the membrane so as to oppose the first electrode. The first electrode has a surface roughness value of 6 nm RMS or less.

Abstract translation: 机电换能器包括基板，设置在基板上的第一电极以及设置在第一电极上的具有间隔的膜的振动膜和设置在膜上以与第一电极相对的第二电极。 第一电极的表面粗糙度值为6nm RMS以下。

公开(公告)号：US09505610B2

公开(公告)日：2016-11-29

申请号：US14129541

申请日：2013-09-25

Applicant: Weng Hong Teh ,  Tarek A Ibrahim ,  Sarah K Haney ,  Daniel N Sobieski ,  Parshuram B Zantye ,  Chad E Mair ,  Telesphor Kamgaing

Inventor： Weng Hong Teh ,  Tarek A Ibrahim ,  Sarah K Haney ,  Daniel N Sobieski ,  Parshuram B Zantye ,  Chad E Mair ,  Telesphor Kamgaing

IPC: H01L21/00 ,  B81C1/00

CPC classification number: B81C1/00246 ,  B81B2201/0271 ,  B81C1/00261 ,  B81C1/00277 ,  H01L21/568 ,  H01L24/19 ,  H01L2224/04105 ,  H01L2224/73267 ,  H01L2924/01079

Abstract: Techniques and mechanisms for providing precisely fabricated structures of a semiconductor package. In an embodiment, a build-up carrier of the semiconductor package includes a layer of porous dielectric material. Seed copper and plated copper is disposed on the layer of porous dielectric material. Subsequent etching is performed to remove copper adjacent to the layer of porous dielectric material, forming a gap separating a suspended portion of a MEMS structure from the layer of porous dielectric material. In another embodiment, the semiconductor package includes a copper structure disposed between portions of an insulating layer or portions of a layer of silicon nitride material. The layer of silicon nitride material couples the insulating layer to another insulating layer. One or both of the insulating layers are each protected from desmear processing with a respective release layer structure.

Abstract translation: 用于提供半导体封装的精确制造结构的技术和机构。 在一个实施例中，半导体封装的积聚载体包括多孔介电材料层。 种子铜和电镀铜设置在多孔电介质材料层上。 进行随后的蚀刻以去除邻近多孔介电材料层的铜，形成将MEMS结构的悬置部分与多孔介电材料层分开的间隙。 在另一个实施例中，半导体封装包括设置在绝缘层的一部分之间或者氮化硅材料层的一部分的铜结构。 氮化硅材料层将绝缘层耦合到另一绝缘层。 每个绝缘层中的一个或两个保护层不受去离子处理的剥离层结构的剥离。