公开(公告)号：US07246435B2

公开(公告)日：2007-07-24

申请号：US11138467

申请日：2005-05-27

Applicant: Keishiro Okamoto ,  Tomoyuki Abe ,  Motoaki Tani ,  Nobuyuki Hayashi

Inventor： Keishiro Okamoto ,  Tomoyuki Abe ,  Motoaki Tani ,  Nobuyuki Hayashi

IPC: H01K3/10

CPC classification number: H05K3/445 ,  H05K1/056 ,  H05K3/426 ,  H05K2201/0179 ,  H05K2201/0195 ,  H05K2201/0323 ,  H05K2201/09581 ,  H05K2203/135 ,  Y10T29/49117 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: The wiring board comprises a plate-shaped conductive core material 10 with a through-hole 12 formed in, an insulation layer 14 formed on the surface of the conductive core material 10 and on the inside wall of the through-hole 12, a resin 18 buried in the through-hole 12 with the insulation layer 14 formed in, wirings 22a, 22b formed on the upper surface and the undersurface of the conductive core material 10 with the insulation layer 14 formed on, and an wiring 22d formed in the through-hole 20 formed in the resin 18 and electrically connected to the wirings 22a, 22b.

Abstract translation: 布线板包括具有形成在其中的通孔12的板状导电芯材10，形成在导电芯材10的表面上的绝缘层14和通孔12的内壁上的树脂18 埋置在通孔12中，其中形成有绝缘层14，形成在形成有绝缘层14的导电芯材10的上表面和下表面上的布线22a，22b以及形成在其中的布线22d 通孔20形成在树脂18中并电连接到布线22a，22b。

公开(公告)号：US20070146980A1

公开(公告)日：2007-06-28

申请号：US11681457

申请日：2007-03-02

Applicant: Jin-Yong Ahn ,  Chang-Sup Ryu ,  Suk-Hyeon Cho ,  Seok-Kyu Lee ,  Jong-Kuk Hong ,  Ho-Sik Jun

Inventor： Jin-Yong Ahn ,  Chang-Sup Ryu ,  Suk-Hyeon Cho ,  Seok-Kyu Lee ,  Jong-Kuk Hong ,  Ho-Sik Jun

IPC: H04R17/00

CPC classification number: H05K1/162 ,  H01G4/1209 ,  H01G4/1218 ,  H01G4/248 ,  H01G4/33 ,  H05K3/4652 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/0195 ,  H05K2201/09509 ,  H05K2201/09763 ,  H05K2201/09881 ,  H05K2203/0568 ,  H05K2203/1366 ,  Y10T29/42

Abstract: Disclosed is a PCB including embedded capacitors and a method of fabricating the same. A dielectric layer is formed using a ceramic material having a high capacitance, thereby assuring that the capacitors each have a high dielectric constant corresponding to the capacitance of a decoupling chip capacitor.

Abstract translation: 公开了一种包括嵌入式电容器的PCB及其制造方法。 使用具有高电容的陶瓷材料形成电介质层，从而确保电容器各自具有对应于去耦芯片电容器的电容的高介电常数。

公开(公告)号：US20070141800A1

公开(公告)日：2007-06-21

申请号：US11393910

申请日：2006-03-31

Applicant: Kazuaki Kurihara ,  Takeshi Shioga ,  John Baniecki ,  Masatoshi Ishii

Inventor： Kazuaki Kurihara ,  Takeshi Shioga ,  John Baniecki ,  Masatoshi Ishii

IPC: H01L21/20

CPC classification number: H01L23/5223 ,  H01G4/33 ,  H01L23/3114 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/50 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L28/55 ,  H01L28/65 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/05155 ,  H01L2224/05552 ,  H01L2224/0557 ,  H01L2224/0603 ,  H01L2224/06102 ,  H01L2224/1147 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/14 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/2518 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00013 ,  H01L2924/0002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/0104 ,  H01L2924/01041 ,  H01L2924/01042 ,  H01L2924/01044 ,  H01L2924/01045 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01056 ,  H01L2924/01068 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/15787 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/19103 ,  H01L2924/30105 ,  H01L2924/30107 ,  H05K1/0231 ,  H05K1/162 ,  H05K1/185 ,  H05K2201/0179 ,  H05K2201/09481 ,  H05K2201/10712 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2924/00

Abstract: The thin-film capacitor comprises a capacitor part 20 formed over a base substrate 10 and including a first capacitor electrode 14, a capacitor dielectric film 16 formed over the first capacitor electrode 14, and a second capacitor electrode 18 formed over the capacitor dielectric film 16; leading-out electrodes 26a, 26b lead from the first capacitor electrode 14 or the second capacitor electrode 18 and formed of a conducting barrier film which prevents the diffusion of hydrogen or water; and outside connection electrodes 34a, 34b for connecting to outside and connected to the leading-out electrodes 26a, 26b.

Abstract translation: 薄膜电容器包括形成在基底基板10上并包括第一电容器电极14，形成在第一电容器电极14上的电容器电介质膜16的电容器部分20和形成在电容器电介质膜16上的第二电容器电极18 ; 引出电极26a，26b从第一电容器电极14或第二电容器电极18引出，并由阻止氢或水扩散的导电阻挡膜形成; 以及用于连接到外部并连接到引出电极26a，26b的外部连接电极34a，34b。

公开(公告)号：US20070131142A1

公开(公告)日：2007-06-14

申请号：US11537957

申请日：2006-10-02

Applicant: William Borland ,  Jon Ihlefeld ,  Jon-Paul Maria

Inventor： William Borland ,  Jon Ihlefeld ,  Jon-Paul Maria

IPC: C23C16/40 ,  B05D5/12

CPC classification number: H01L21/02205 ,  C01G23/006 ,  C01G25/00 ,  C01P2006/42 ,  C04B35/4682 ,  C04B35/49 ,  C04B35/632 ,  C04B2235/3215 ,  C04B2235/3293 ,  C04B2235/441 ,  C04B2235/449 ,  C04B2235/6584 ,  C04B2235/663 ,  C23C18/1216 ,  C23C18/1241 ,  C23C18/1279 ,  C23C18/1295 ,  H01G4/1227 ,  H01G4/33 ,  H01L21/02197 ,  H01L21/02282 ,  H01L21/31691 ,  H01L28/55 ,  H05K1/162 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/0355

Abstract: Disclosed are high permittivity (dielectric constant), thin film CSD barium titanate based dielectric compositions that have titanium partially substituted by zirconium, tin or hafnium. The compositions show capacitance as a function of temperature that better satisfies the X7R requirements.

Abstract translation: 公开了具有部分被锆，锡或铪取代的钛的高介电常数（介电常数）薄膜CSD钛酸钡基电介质组合物。 该组合物显示出更好地满足X7R要求的电容作为温度的函数。

公开(公告)号：US20070097596A1

公开(公告)日：2007-05-03

申请号：US11583067

申请日：2006-10-19

Applicant: Hajime Kuwajima ,  Masahiro Miyazaki ,  Akira Furuya

Inventor： Hajime Kuwajima ,  Masahiro Miyazaki ,  Akira Furuya

IPC: H01G4/06

CPC classification number: H01G4/33 ,  H01G4/01 ,  H05K1/162 ,  H05K3/244 ,  H05K2201/0179 ,  H05K2201/0347 ,  Y10T29/435

Abstract: A thin-film device comprises a substrate and a capacitor provided on the substrate. The capacitor incorporates: a lower conductor layer disposed on the substrate; a dielectric film disposed on the lower conductor layer; and an upper conductor layer disposed on the dielectric film. The thickness of the dielectric film falls within a range of 0.02 to 1 μm inclusive and is smaller than the thickness of the lower conductor layer. The surface roughness in maximum height of the top surface of the lower conductor layer is equal to or smaller than the thickness of the dielectric film.

Abstract translation: 薄膜器件包括衬底和设置在衬底上的电容器。 电容器包括：设置在基板上的下导体层; 设置在下导体层上的电介质膜; 以及设置在电介质膜上的上导体层。 电介质膜的厚度在0.02〜1μm的范围内，小于下导体层的厚度。 下导体层的上表面的最大高度的表面粗糙度等于或小于电介质膜的厚度。

公开(公告)号：US20070094871A1

公开(公告)日：2007-05-03

申请号：US11592169

申请日：2006-11-03

Applicant: Jin Moon ,  Yul Chung ,  Seung Sohn

Inventor： Jin Moon ,  Yul Chung ,  Seung Sohn

IPC: H01G7/00

CPC classification number: H01G4/10 ,  H01G4/33 ,  H05K1/162 ,  H05K3/181 ,  H05K2201/0175 ,  H05K2201/0179 ,  Y10T29/435 ,  Y10T29/4913 ,  Y10T29/49133

Abstract: The invention provides a method for manufacturing a printed circuit board with a film capacitor embedded therein and a printed circuit board obtained thereby. In the method, a lower electrode is formed on an insulating substrate. An amorphous dielectric film is formed on the lower electrode by low temperature film formation. Also, a metal seed layer is formed on the dielectric film by electroless plating. An upper electrode is formed on the metal seed layer by electrolytic plating.

Abstract translation: 本发明提供一种制造其中嵌有薄膜电容器的印刷电路板和由此获得的印刷电路板的方法。 在该方法中，在绝缘基板上形成下电极。 通过低温成膜在下电极上形成非晶电介质膜。 此外，通过化学镀在电介质膜上形成金属种子层。 通过电解电镀在金属籽晶层上形成上电极。

公开(公告)号：US20070090546A1

公开(公告)日：2007-04-26

申请号：US11338857

申请日：2006-01-25

Applicant: Takeshi Shioga ,  Yoshikatsu Ishizuki ,  Kanae Nakagawa ,  Taiji Sakai ,  Masataka Mizukoshi ,  John Baniecki ,  Kazuaki Kurihara

Inventor： Takeshi Shioga ,  Yoshikatsu Ishizuki ,  Kanae Nakagawa ,  Taiji Sakai ,  Masataka Mizukoshi ,  John Baniecki ,  Kazuaki Kurihara

IPC: H01L23/29

CPC classification number: H01L23/50 ,  H01L21/4846 ,  H01L21/4857 ,  H01L21/6835 ,  H01L23/49822 ,  H01L23/642 ,  H01L23/645 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/3011 ,  H05K1/162 ,  H05K1/165 ,  H05K3/0023 ,  H05K3/0044 ,  H05K3/20 ,  H05K3/4614 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/0317 ,  H05K2201/09481 ,  H05K2201/09509 ,  H05K2201/096 ,  H05K2201/09763 ,  H05K2201/10674 ,  H05K2203/016 ,  H05K2203/0733 ,  Y10T29/42 ,  Y10T29/435 ,  Y10T29/49002 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49156 ,  H01L2224/05599

Abstract: The interposer comprises a base 8 formed of a plurality of resin layers 68, 20, 32, 48; thin-film capacitors 18a, 18b buried between a first resin layer 68 of said plurality of resin layers and a second resin layer 20 of said plurality of resin layers, which include first capacitor electrodes 12a, 12b, second capacitor electrodes 16 opposed to the first capacitor electrode 12a, 12b and the second capacitor electrode 16, and a capacitor dielectric film 14 of a relative dielectric constant of 200 or above formed between the first capacitor electrode 12a, 12b and the second capacitor electrode 16; a first through-electrode 77a formed through the base 8 and electrically connected to the first capacitor electrode 12a, 12b; and a second through-electrode 77b formed through the base 8 and electrically connected to the second capacitor electrode 16.

Abstract translation: 插入件包括由多个树脂层68,20,32,48形成的基座8; 掩埋在所述多个树脂层的第一树脂层68和所述多个树脂层的第二树脂层20之间的薄膜电容器18a，18b，其包括第一电容器电极12a，12b，第二电容器电极16 与第一电容器电极12a，12b和第二电容器电极16相对，以及形成在第一电容器电极12a，12b和第二电容器电极16之间的相对介电常数为200或更大的电容器电介质膜14 ; 通过基座8形成并电连接到第一电容器电极12a，12b的第一贯通电极77a; 以及通过基底8形成并电连接到第二电容器电极16的第二贯通电极77b。

公开(公告)号：US20070020955A1

公开(公告)日：2007-01-25

申请号：US11490230

申请日：2006-07-21

Applicant: Won Song ,  Yul Chung ,  Sung Lim

Inventor： Won Song ,  Yul Chung ,  Sung Lim

IPC: H01L21/31

CPC classification number: H01L21/02197 ,  H01G4/33 ,  H01L21/02186 ,  H01L21/02282 ,  H01L21/31683 ,  H01L21/31691 ,  H05K1/162 ,  H05K2201/0175 ,  H05K2201/0179

Abstract: The invention relates to a fabrication method of a composite metal oxide dielectric film containing at least two metallic elements on a substrate, and a composite metal oxide dielectric film fabricated thereby. The method includes: forming an amorphous film containing at least one of the metallic elements; preparing a hydrothermal solution where a precursor of the remaining element of the metallic elements is mixed; immersing the amorphous film into the hydrothermal solution; and hydrothermally treating the amorphous film so that the remaining one of the metallic elements is synthesized to the amorphous film, thereby forming a crystallized composite metal oxide film.

Abstract translation: 本发明涉及在基板上含有至少两种金属元素的复合金属氧化物电介质膜的制造方法以及由此制造的复合金属氧化物电介质膜。 该方法包括：形成含有至少一种金属元素的非晶膜; 制备其中混合金属元素的剩余元素的前体的水热溶液; 将非晶膜浸入水热溶液中; 对该非晶质膜进行水热处理，使残留的金属元素与非晶质膜合成，从而形成结晶化复合金属氧化物膜。

公开(公告)号：US20060292813A1

公开(公告)日：2006-12-28

申请号：US11494327

申请日：2006-07-27

Applicant: Kazuyoshi Honda ,  Noriyasu Echigo ,  Masaru Odagiri ,  Takanori Sugimoto

Inventor： Kazuyoshi Honda ,  Noriyasu Echigo ,  Masaru Odagiri ,  Takanori Sugimoto

IPC: H01L21/20

CPC classification number: H01G4/33 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/50 ,  H01L2224/16 ,  H01L2924/15311 ,  H01L2924/3011 ,  H05K1/0231 ,  H05K1/0289 ,  H05K1/141 ,  H05K1/162 ,  H05K3/0026 ,  H05K3/403 ,  H05K3/467 ,  H05K2201/0179 ,  H05K2201/049 ,  H05K2201/09236 ,  H05K2201/10734

Abstract: Electrode layers (1, 2) are arranged on both sides of a dielectric layer (3) facing each other so as to configure a capacitor. Lead electrodes (4, 5) are formed in the electrode layers (1, 2). A penetrating electrode (6) that is insulated from the electrode layers (1, 2) is formed. An electronic component (10) configured in this manner is mounted on a wiring board, and a semiconductor chip can be mounted thereon. Along with connecting the semiconductor chip to the wiring board via the penetrating electrode (6), the semiconductor chip or the wiring board is connected to the lead electrodes (4, 5). In this manner, while suppressing the size increase of a mounted area, the capacitor or the like can be arranged near the semiconductor chip. Thus, the semiconductor chip is driven with high frequency more easily.

Abstract translation: 电极层（1,2）布置在相互面对的介质层（3）的两侧，以构成电容器。 在电极层（1,2）中形成引线电极（4,5）。 形成与电极层（1,2）绝缘的穿透电极（6）。 以这种方式配置的电子部件（10）安装在布线板上，并且可以在其上安装半导体芯片。 通过穿透电极（6）将半导体芯片与布线板连接，半导体芯片或布线基板与引线电极（4,5）连接。 以这种方式，在抑制安装区域的尺寸增加的同时，电容器等可以布置在半导体芯片附近。 因此，更容易地以高频率驱动半导体芯片。

公开(公告)号：US07138330B2

公开(公告)日：2006-11-21

申请号：US10671996

申请日：2003-09-26

Applicant: Rajiv Shah ,  Shaun Pendo

Inventor： Rajiv Shah ,  Shaun Pendo

IPC: H01L21/4763

CPC classification number: H05K3/467 ,  H01L21/4857 ,  H01L21/4867 ,  H01L2924/0002 ,  H01L2924/19107 ,  H05K1/162 ,  H05K3/048 ,  H05K3/4053 ,  H05K3/4061 ,  H05K3/4664 ,  H05K2201/0179 ,  H05K2203/0278 ,  H05K2203/085 ,  H05K2203/1476 ,  H05K2203/308 ,  H01L2924/00

Abstract: A multilayer circuit substrate for multi-chip modules or hybrid circuits includes a dielectric base substrate, conductors formed on the base substrate and a vacuum deposited dielectric thin film formed over the conductors and the base substrate. The vacuum deposited dielectric thin film is patterned using sacrificial structures formed by shadow mask techniques. Substrates formed in this manner enable significant increases in interconnect density and significant reduction of over-all substrate thickness.