公开(公告)号：US20100122840A1

公开(公告)日：2010-05-20

申请号：US12694322

申请日：2010-01-27

Applicant: Motoo ASAI ,  Dongdong Wang ,  Takahiro Mori

Inventor： Motoo ASAI ,  Dongdong Wang ,  Takahiro Mori

IPC: H05K1/02 ,  H05K1/03

CPC classification number: H05K3/423 ,  H01L21/486 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/15312 ,  H05K1/036 ,  H05K3/0032 ,  H05K3/0035 ,  H05K3/0038 ,  H05K3/108 ,  H05K3/181 ,  H05K3/381 ,  H05K3/385 ,  H05K3/387 ,  H05K3/388 ,  H05K3/426 ,  H05K3/427 ,  H05K3/4602 ,  H05K2201/0195 ,  H05K2201/0352 ,  H05K2201/0355 ,  H05K2201/0394 ,  H05K2201/09536 ,  H05K2201/09563 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2201/09736 ,  H05K2201/09881 ,  H05K2203/0315 ,  H05K2203/0733 ,  H05K2203/0773 ,  H05K2203/1476 ,  Y10T29/49126 ,  Y10T29/49144 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2224/05599

Abstract: A multi-layer printed circuit board including a core structure including resin layers and conductor circuits sandwiched by the resin layers, the core structure having a first surface and a second surface on an opposite side of the first surface, a first conductor layer including conductor circuits formed on the first surface of the core structure, and a second conductor layer including conductor circuits formed on the second surface of the core structure. The core structure includes a first via hole and a second via hole, the first via hole and the second via hole sandwich one or more conductor circuits in the core substrate and are positioned vertically to form a through hole electrically connecting respective ones of the conductor circuits of the first and the second conductor layers, and the first via hole and the second via hole are deviated from each other in a vertical direction.

Abstract translation: 一种多层印刷电路板，包括由树脂层和由树脂层夹在的导体电路的芯结构，芯结构具有在第一表面的相对侧的第一表面和第二表面，第一导体层包括导体电路 形成在芯结构的第一表面上，以及第二导体层，包括形成在芯结构的第二表面上的导体电路。 芯结构包括第一通孔和第二通孔，第一通孔和第二通孔夹着芯基板中的一个或多个导体电路并垂直定位，以形成电连接各个导体电路的通孔 的第一和第二导体层，并且第一通孔和第二通孔在垂直方向上彼此偏离。

公开(公告)号：US20100116528A1

公开(公告)日：2010-05-13

申请号：US12475764

申请日：2009-06-01

Applicant: Chang-han Shim ,  Sung-il Kang ,  Se-chuel Park

Inventor： Chang-han Shim ,  Sung-il Kang ,  Se-chuel Park

IPC: H05K1/03 ,  C25D7/12

CPC classification number: H05K3/384 ,  C25D5/12 ,  H05K1/0346 ,  H05K1/0393 ,  H05K2201/0154 ,  H05K2201/0355 ,  H05K2203/0307 ,  H05K2203/0723 ,  Y10T428/12514 ,  Y10T428/12861 ,  Y10T428/12868 ,  Y10T428/1291 ,  Y10T428/12944 ,  Y10T428/24917

Abstract: Provided is a printed circuit board (PCB) with multiple metallic layers and a method of manufacturing the PCB to improve adhesion between a metal film and a polymer film, on which a circuit pattern is formed. The PCB includes: a first metal film; a polymer film formed on one surface of the first metal film; and a second metal film, interposed between the first metal film and the polymer film, having a first surface facing the first metal film and a second surface facing the polymer film, wherein the second surface is rougher than the first surface.

Abstract translation: 提供了具有多个金属层的印刷电路板（PCB）和制造PCB以提高金属膜和形成电路图案的聚合物膜之间的粘附性的方法。 PCB包括：第一金属膜; 形成在所述第一金属膜的一个表面上的聚合物膜; 以及介于所述第一金属膜和所述聚合物膜之间的第二金属膜，具有面向所述第一金属膜的第一表面和面向所述聚合物膜的第二表面，其中所述第二表面比所述第一表面更粗糙。

公开(公告)号：US20100078800A1

公开(公告)日：2010-04-01

申请号：US12557896

申请日：2009-09-11

Applicant: Zaid Aboush ,  Peter John Robinson

Inventor： Zaid Aboush ,  Peter John Robinson

IPC: H01L23/498 ,  H05K1/09 ,  B05D5/12 ,  H01L21/56

CPC classification number: H05K3/0023 ,  H01L23/3128 ,  H01L23/4985 ,  H01L24/32 ,  H01L24/48 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/07811 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K1/0393 ,  H05K2201/0355 ,  H05K2201/0394 ,  H01L2924/01028 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A low cost flexible substrate is described which comprises a thin metal foil and a layer of solder mask. The metal foil layer is patterned to create tracks and lands for solder bonding and/or wirebonding and the layer of solder mask is patterned to create openings for solder bonding, wirebonding and/or for mounting the die. The substrate may be used as a package substrate to create a packaged die or may be used as a replacement for more expensive flexible printed circuit boards.

Abstract translation: 描述了一种低成本的柔性基板，其包括薄金属箔和一层阻焊层。 图案化金属箔层以产生用于焊接和/或引线接合的轨道和焊盘，并且图案化阻焊层以产生用于焊接，引线键合和/或用于安装管芯的开口。 衬底可以用作封装衬底以形成封装的裸片，或者可以用来代替更昂贵的柔性印刷电路板。

公开(公告)号：US07688569B2

公开(公告)日：2010-03-30

申请号：US10801257

申请日：2004-03-16

Applicant: William J. Borland ,  Alton Bruce Jones, III ,  Olga L. Renovales ,  Kenneth Warren Hang

Inventor： William J. Borland ,  Alton Bruce Jones, III ,  Olga L. Renovales ,  Kenneth Warren Hang

IPC: H01G4/06

CPC classification number: C04B35/468 ,  C04B2235/445 ,  C04B2235/6562 ,  H01G4/008 ,  H01G4/1227 ,  H01G4/33 ,  H05K1/162 ,  H05K3/1291 ,  H05K2201/017 ,  H05K2201/0355 ,  H05K2201/09763 ,  H05K2203/1126

Abstract: Dielectric powder and thick-film paste compositions are formed having high dielectric constants, low loss tangents, and other desirable electrical and physical properties. Conductive powder and paste compositions are formed having desirable electrical and physical properties. The dielectric powder and thick-film paste compositions can be used in combination with the conductive powder and paste compositions to form capacitors and other fired-on-foil passive circuit components.

Abstract translation: 形成介电粉末和厚膜糊组合物，其具有高介电常数，低损耗切线和其它所需的电学和物理性能。 形成具有所需电学和物理性质的导电粉末和糊剂组合物。 电介质粉末和厚膜糊剂组合物可以与导电粉末和糊剂组合物组合使用，以形成电容器和其它无卤电路元件。

公开(公告)号：US07687366B2

公开(公告)日：2010-03-30

申请号：US11601101

申请日：2006-11-17

Applicant: Yongki Min

Inventor： Yongki Min

IPC: H01L21/20 ,  H01G9/00

CPC classification number: H01L23/49822 ,  H01G4/228 ,  H01G4/33 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/12044 ,  H01L2924/15311 ,  H05K1/162 ,  H05K3/048 ,  H05K3/4652 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/0355 ,  H05K2201/09763 ,  Y10T29/417 ,  H01L2924/00

Abstract: An embedded passive structure, its method of formation, and its integration onto a substrate during fabrication are disclosed. In one embodiment, the embedded passive structure is a thin film capacitor (TFC) formed using a thin film laminate that has been mounted onto a substrate. The TFC's capacitor dielectric and/or lower electrode layers are patterned in such a way as to reduce damage and improve cycle time. In one embodiment, the capacitor dielectric has a high dielectric constant and the substrate is an organic packaging substrate.

Abstract translation: 公开了嵌入式被动结构，其形成方法及其在制造过程中与衬底的集成。 在一个实施例中，嵌入式无源结构是使用已经安装在基板上的薄膜层叠体形成的薄膜电容器（TFC）。 TFC的电容器电介质和/或下电极层被图案化以减少损坏并改善循环时间。 在一个实施例中，电容器电介质具有高介电常数，并且衬底是有机封装衬底。

公开(公告)号：US20100073845A1

公开(公告)日：2010-03-25

申请号：US12237409

申请日：2008-09-25

Applicant: SEIGI SUH ,  Esther Kim ,  William J. Borland ,  Christopher Allen Gross ,  Omega N. Mack ,  Timothy R. Overcash

Inventor： SEIGI SUH ,  Esther Kim ,  William J. Borland ,  Christopher Allen Gross ,  Omega N. Mack ,  Timothy R. Overcash

IPC: H01G4/00 ,  B05D5/12

CPC classification number: H01G4/12 ,  H01G13/00 ,  H05K1/162 ,  H05K2201/0175 ,  H05K2201/0195 ,  H05K2201/0355 ,  H05K2203/1126 ,  Y10T29/43 ,  Y10T29/435 ,  Y10T29/49128 ,  Y10T29/49147 ,  Y10T29/49155 ,  Y10T29/49163

Abstract: Disclosed are methods of making a dielectric on a metal foil, and a method of making a large area capacitor that includes a dielectric on a metal foil. A first dielectric layer is formed over the metal foil by physical vapor deposition, and a dielectric precursor layer is formed over the first dielectric layer by chemical solution deposition. The metal foil, first dielectric layer and dielectric precursor layer are prefired at a prefiring temperature in the range of 350 to 650° C. The prefired dielectric precursor layer, the first dielectric layer and the base metal foil are subsequently fired at a firing temperature in the range of 700 to 1200° C.

Abstract translation: 公开了在金属箔上制造电介质的方法，以及制造在金属箔上包含电介质的大面积电容器的方法。 通过物理气相沉积在金属箔上形成第一电介质层，并且通过化学溶液沉积在第一介电层上形成电介质前体层。 金属箔，第一电介质层和电介质前体层在预热温度为350至650℃的范围内预烧制。预烧电介质前体层，第一介电层和贱金属箔随后在焙烧温度 范围700〜1200℃

公开(公告)号：US07679925B2

公开(公告)日：2010-03-16

申请号：US11489544

申请日：2006-07-20

Applicant: Yoshitaka Fukuoka ,  Tooru Serizawa ,  Hiroshi Yagi ,  Osamu Shimada ,  Hiroyuki Hirai ,  Yuji Yamaguchi

Inventor： Yoshitaka Fukuoka ,  Tooru Serizawa ,  Hiroshi Yagi ,  Osamu Shimada ,  Hiroyuki Hirai ,  Yuji Yamaguchi

IPC: H05K1/18

CPC classification number: H05K1/162 ,  H05K1/095 ,  H05K1/165 ,  H05K1/167 ,  H05K3/4069 ,  H05K3/4614 ,  H05K3/4652 ,  H05K2201/0187 ,  H05K2201/0355 ,  H05K2201/086 ,  H05K2201/09763 ,  H05K2203/0338 ,  H05K2203/1189 ,  Y10T29/4902 ,  Y10T29/49099 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155

Abstract: A fabricating method of a wiring board provided with passive elements is disclosed. The fabricating method includes coating one or both of resistive paste and dielectric paste on at least any one of first surfaces of a first metal foil and a second metal foil each of which has a first surface and a second surface; arranging an insulating board having thermo-plasticity and thermo-setting properties so as to face the first surface of the first metal foil, and arranging the first surface side of the second metal foil so as to face a surface different from a surface to which the first metal foil faces of the insulating board; forming a double-sided wiring board by stacking, pressurizing and heating the arranged first metal foil, insulating board, and second metal foil, and thereby integrating these; and patterning the first metal foil and/or the second metal foil.

Abstract translation: 公开了一种具有无源元件的布线板的制造方法。 制造方法包括在第一金属箔和第二金属箔的至少一个第一表面上涂覆电阻浆料和电介质浆料中的一种或两种，每个第一表面具有第一表面和第二表面; 布置具有热塑性和热固性的绝缘板，以便面对第一金属箔的第一表面，并且将第二金属箔的第一表面侧布置成面对不同于表面的表面 绝缘板的第一金属箔面; 通过对所配置的第一金属箔，绝缘板和第二金属箔进行堆叠，加压和加热来形成双面布线板，从而将它们集成; 以及图案化第一金属箔和/或第二金属箔。

公开(公告)号：US20100043942A1

公开(公告)日：2010-02-25

申请号：US12614576

申请日：2009-11-09

Applicant: Hironori Tanaka ,  Kazuhiro Yoshikawa ,  Naoaki Fujii ,  Atsunari Yamashita

Inventor： Hironori Tanaka ,  Kazuhiro Yoshikawa ,  Naoaki Fujii ,  Atsunari Yamashita

IPC: B32B38/00 ,  B32B38/10

CPC classification number: H05K1/185 ,  H01L24/19 ,  H01L24/82 ,  H01L2223/54426 ,  H01L2224/04105 ,  H01L2224/32225 ,  H01L2224/82039 ,  H01L2224/82047 ,  H01L2224/92144 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30107 ,  H05K1/0231 ,  H05K1/188 ,  H05K3/382 ,  H05K3/427 ,  H05K3/4602 ,  H05K2201/0187 ,  H05K2201/0209 ,  H05K2201/0355 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/09781 ,  H05K2201/09918 ,  H05K2201/10636 ,  H05K2203/063 ,  Y02P70/611 ,  Y10T29/4913 ,  Y10T29/49133 ,  Y10T29/49146 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: A printed wiring board is manufactured by a method in which a laminate body having a first insulation layer and a conductive film is provided. An alignment mark is formed in the laminate body by removing at least a portion of the conductive film. An electronic component is placed on an adhesive layer provided on the first insulation layer at a position determined based on the alignment mark. After the electronic component is enclosed inside an opening of the second insulation layer, a via hole exposing a terminal of the electronic component is formed at a position determined based on the alignment mark used to determine the position of the electronic component. A via conductor is formed in the via hole, and a conductive layer is formed on the conductive film and patterned to form a conductive circuit connected to the via conductor.

Abstract translation: 通过提供具有第一绝缘层和导电膜的层叠体的方法制造印刷线路板。 通过去除导电膜的至少一部分，在层压体中形成对准标记。 将电子部件放置在基于对准标记确定的位置上设置在第一绝缘层上的粘合剂层上。 在将电子部件封装在第二绝缘层的开口内之后，在基于用于确定电子部件的位置的对准标记确定的位置处形成暴露电子部件的端子的通孔。 通孔导体形成在通孔中，导电层形成在导电膜上并被图案化以形成连接到通孔导体的导电电路。

公开(公告)号：US20100018762A1

公开(公告)日：2010-01-28

申请号：US12502268

申请日：2009-07-14

Applicant: Hideaki YOSHIMURA ,  Norikazu OZAKI ,  Kenji IIDA ,  Tomoyuki ABE

Inventor： Hideaki YOSHIMURA ,  Norikazu OZAKI ,  Kenji IIDA ,  Tomoyuki ABE

IPC: H05K1/11 ,  H05K3/36 ,  B23P23/00

CPC classification number: H05K1/036 ,  H05K1/0366 ,  H05K3/06 ,  H05K3/107 ,  H05K3/108 ,  H05K3/421 ,  H05K3/426 ,  H05K3/4644 ,  H05K2201/0195 ,  H05K2201/0355 ,  H05K2201/0376 ,  H05K2201/0394 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2203/0278 ,  H05K2203/1476 ,  Y10T29/49126 ,  Y10T29/51

Abstract: A printed circuit board includes a first insulation layer that is formed of a resin material into which fiber cloth is embedded. A second insulation layer is formed of a resin material, and is stacked on a front surface of the first insulation layer on which a heating process has been performed. A conductive land is formed on a front surface of the second insulation layer. A via is provided in a through hole penetrating through the first insulation layer and the second insulation layer. The through hole is filled with a conductive material, and the via is connected to the conductive land.

Abstract translation: 印刷电路板包括由嵌入有纤维布的树脂材料形成的第一绝缘层。 第二绝缘层由树脂材料形成，并且堆叠在已经进行了加热处理的第一绝缘层的前表面上。 导电焊盘形成在第二绝缘层的前表面上。 通孔设置在穿过第一绝缘层和第二绝缘层的通孔中。 通孔填充有导电材料，并且通孔连接到导电焊盘。

公开(公告)号：US07638418B2

公开(公告)日：2009-12-29

申请号：US11676869

申请日：2007-02-20

Applicant: Michael Bauer ,  Rainer Steiner ,  Holger Woerner

Inventor： Michael Bauer ,  Rainer Steiner ,  Holger Woerner

IPC: H01L21/44

CPC classification number: H05K1/111 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/562 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/15173 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K1/0271 ,  H05K1/114 ,  H05K2201/0133 ,  H05K2201/0187 ,  H05K2201/0355 ,  H05K2201/091 ,  H05K2203/0278 ,  Y02P70/611 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A wiring substrate of a semiconductor component includes: an underside with a wiring structure; a top side with cutouts; a rubber-elastic material arranged in the cutouts; and external contact pads arranged on the rubber-elastic material and configured to be coupled to external contacts. A method for producing a wiring substrate of this type, involves pressing the rubber-elastic material pads into a precursor of a polymer plastic during the production process.

Abstract translation: 半导体部件的布线基板包括：具有布线结构的下侧; 顶部有切口; 布置在所述切口中的橡胶弹性材料; 以及设置在橡胶弹性材料上并且被配置为联接到外部触点的外部接触垫。 制造这种布线基板的方法涉及在生产过程中将橡胶弹性材料垫压入聚合物塑料的前体中。