公开(公告)号：US20090075469A1

公开(公告)日：2009-03-19

申请号：US11855236

申请日：2007-09-14

Applicant: Bruce K. Furman ,  Jae-Woong Nah

Inventor： Bruce K. Furman ,  Jae-Woong Nah

IPC: H01L21/44

CPC classification number: H05K3/3436 ,  H01L21/563 ,  H01L21/6835 ,  H01L24/11 ,  H01L24/12 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/05001 ,  H01L2224/05026 ,  H01L2224/0508 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05571 ,  H01L2224/05644 ,  H01L2224/11003 ,  H01L2224/11334 ,  H01L2224/11901 ,  H01L2224/13082 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/1357 ,  H01L2224/13611 ,  H01L2224/13644 ,  H01L2224/13655 ,  H01L2224/16 ,  H01L2224/73203 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/81801 ,  H01L2924/00013 ,  H01L2924/01006 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H05K3/328 ,  H05K2201/0367 ,  H05K2201/0379 ,  H05K2201/10234 ,  H05K2201/10734 ,  H05K2201/10977 ,  H05K2203/0338 ,  Y02P70/613 ,  Y10T29/49155 ,  H01L2924/00014 ,  H01L2224/13099

Abstract: An electrical structure and method for forming electrical interconnects. The method includes positioning a sacrificial carrier substrate such that a first surface of a non-solder metallic core structure within the sacrificial carrier substrate is in contact with a first electrically conductive pad. The first surface is thermo-compression bonded to the first electrically conductive pad. The sacrificial carrier substrate is removed from the non-solder metallic core structure. A solder structure is formed on a second electrically conductive pad. The first substrate comprising the non-solder metallic core structure is positioned such that a second surface of the non-solder metallic core structure is in contact with the solder structure. The solder structure is heated to a temperature sufficient to cause the solder structure to melt and form an electrical and mechanical connection between the second surface of the non-solder metallic core structure and the second electrically conductive pad.

Abstract translation: 一种用于形成电互连的电结构和方法。 该方法包括定位牺牲载体衬底，使得牺牲载体衬底内的非焊料金属芯结构的第一表面与第一导电焊盘接触。 第一表面被热压接合到第一导电焊盘。 从非焊接金属芯结构去除牺牲载体衬底。 在第二导电焊盘上形成焊料结构。 包括非焊料金属芯结构的第一衬底定位成使得非焊料金属芯结构的第二表面与焊料结构接触。 将焊料结构加热到足以使焊料结构熔化并在非焊接金属芯结构的第二表面和第二导电焊盘之间形成电和机械连接的温度。

公开(公告)号：US20090071707A1

公开(公告)日：2009-03-19

申请号：US12228537

申请日：2008-08-13

Applicant: Kimitaka Endo ,  Philip Damberg ,  Craig S. Mitchell ,  Sean Moran ,  Christopher Wade ,  Belgacem Haba ,  John Riley

Inventor： Kimitaka Endo ,  Philip Damberg ,  Craig S. Mitchell ,  Sean Moran ,  Christopher Wade ,  Belgacem Haba ,  John Riley

IPC: H05K1/11 ,  C25D5/02

CPC classification number: H05K3/4007 ,  C25D5/02 ,  H01L21/4846 ,  H01L24/73 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/4824 ,  H01L2224/73204 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/04941 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K1/112 ,  H05K3/06 ,  H05K3/20 ,  H05K3/243 ,  H05K3/421 ,  H05K3/423 ,  H05K3/4644 ,  H05K2201/0367 ,  H05K2201/09563 ,  H05K2203/0152 ,  H05K2203/0376 ,  H05K2203/0384 ,  H05K2203/0733 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05599

Abstract: A method is provided for manufacturing a multilayer substrate. An insulating layer can have a hole overlying a patterned second metal layer. In turn, the second metal layer can overlie a first metal layer. A third metal layer can be electroplated onto the patterned second metal layer within the hole, the third metal layer extending from the second metal layer onto a wall of the hole. When plating the third metal layer, the first and second metal layers can function as a conductive commoning element.

Abstract translation: 提供了制造多层基板的方法。 绝缘层可以具有覆盖图案化的第二金属层的孔。 反过来，第二金属层可以覆盖在第一金属层上。 第三金属层可以电镀在孔内的图案化的第二金属层上，第三金属层从第二金属层延伸到孔的壁上。 当电镀第三金属层时，第一和第二金属层可以用作导电共用元件。

公开(公告)号：US20090071705A1

公开(公告)日：2009-03-19

申请号：US12007688

申请日：2008-01-14

Applicant: Moon-Il Kim ,  Young-Do Kweon

Inventor： Moon-Il Kim ,  Young-Do Kweon

IPC: H01R12/06 ,  H05K3/42

CPC classification number: H05K1/185 ,  H01L21/568 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/19 ,  H01L2224/20 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06582 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/07802 ,  H01L2924/18162 ,  H05K2201/0367 ,  H05K2201/10159 ,  H05K2201/10515 ,  H05K2201/10674 ,  H05K2203/0156 ,  H05K2203/1469 ,  Y10T29/4913 ,  Y10T29/49165 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2224/83005

Abstract: A PCB (printed circuit board) having embedded components and a method for manufacturing thereof are disclosed. The PCB may include a dielectric substrate having a cavity formed in one side, a first component inserted in the cavity such that an electrode of the first component faces the one side of the dielectric substrate, a second component mounted on one side of the first component such that an electrode of the second component faces the same direction as the electrode of the first component, a first dielectric layer formed on one side of the dielectric substrate such that the first dielectric layer covers the second component, and a second dielectric layer formed on the other side of the dielectric substrate such that the second dielectric layer covers the first component. In this PCB, multiple components of differing thickness can be mounted, and vias can be formed more easily.

Abstract translation: 公开了具有嵌入部件的PCB（印刷电路板）及其制造方法。 PCB可以包括具有在一侧形成的空腔的电介质基板，插入空腔中的第一部件，使得第一部件的电极面向电介质基板的一侧，第二部件安装在第一部件的一侧 使得第二部件的电极面向与第一部件的电极相同的方向，形成在电介质基板的一侧上的第一电介质层，使得第一电介质层覆盖第二部件，第二电介质层形成在 电介质基板的另一侧使得第二介电层覆盖第一部件。 在该PCB中，可以安装不同厚度的多个部件，并且可以更容易地形成通孔。

公开(公告)号：US20090070999A1

公开(公告)日：2009-03-19

申请号：US12270956

申请日：2008-11-14

Applicant: Gareth G. Hougham ,  Brian S. Beaman ,  Evan G. Colgan ,  Paul W. Coteus ,  Stefano S. Oggioni ,  Enrique Vargas

Inventor： Gareth G. Hougham ,  Brian S. Beaman ,  Evan G. Colgan ,  Paul W. Coteus ,  Stefano S. Oggioni ,  Enrique Vargas

IPC: H01R43/16

CPC classification number: H01R12/714 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01R12/52 ,  H05K3/326 ,  H05K3/4007 ,  H05K7/1061 ,  H05K2201/0133 ,  H05K2201/0367 ,  H05K2201/09481 ,  H05K2201/09745 ,  H05K2201/10378 ,  H05K2201/10734 ,  Y10T29/49002 ,  Y10T29/49121 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49147 ,  Y10T29/49149 ,  Y10T29/49151 ,  Y10T29/49155 ,  Y10T29/49158 ,  Y10T29/49165 ,  Y10T29/49204 ,  Y10T29/49208 ,  Y10T29/49213 ,  Y10T29/49218 ,  Y10T29/49222 ,  H01L2924/00

Abstract: A method of producing a module arrangement which includes a land grid array (LGA) interposer structure, including an electrically insulating carrier plane, and at least one interposer mounted on a first surface of said carrier plane. The interposer possesses a hemi-toroidal configuration in transverse cross-section and is constituted of a dielectric elastomeric material. A plurality of electrically-conductive elements are arranged about the surface of the at least one hemi-toroidal interposer and extend radically inwardly and downwardly from an uppermost end thereof into electrical contact with at least one component located on an opposite side of the electrically insulating carrier plane.

Abstract translation: 一种制造模块装置的方法，其包括包括电绝缘载体平面的平面栅格阵列（LGA）插入器结构以及安装在所述载体平面的第一表面上的至少一个插入器。 插入件在横截面中具有半环形结构，并由介电弹性体材料构成。 多个导电元件围绕至少一个半环形插入器的表面布置并且从其最上端向内和向下自由地延伸至与位于电绝缘载体的相对侧上的至少一个部件的电接触 飞机

公开(公告)号：US20090050359A1

公开(公告)日：2009-02-26

申请号：US12229422

申请日：2008-08-21

Applicant: Wen-Hung Hu ,  Wen-Yuan Chi

Inventor： Wen-Hung Hu ,  Wen-Yuan Chi

IPC: H05K1/02 ,  H05K3/46

CPC classification number: H05K1/111 ,  H05K1/113 ,  H05K3/108 ,  H05K3/243 ,  H05K3/4007 ,  H05K2201/0367 ,  H05K2201/09436 ,  H05K2201/09781 ,  Y02P70/611 ,  Y10T29/49147

Abstract: A circuit board having an electrically connecting structure and a method for fabricating the same are provided. A circuit board body having inner-layer circuits is provided. A circuit layer is formed on at least an outermost surface of circuit board body, and including electrically connecting pads and circuits. The electrically connecting pads are partially electrically connected to the circuits, and are partially electrically connected to the inner-layer circuits via conductive vias. An insulating protective layer is disposed on the circuit board body and is formed with openings therein for exposing the electrically connecting pads. Conductive posts are formed on the electrically connecting pads. Standalone metal pads are formed on the insulating protective layer but are not used for electrical connection. The conductive posts and electrically connecting pads are absent from the insulating protective layer beneath the standalone metal pads, such that circuits can be formed under the insulating protective layer.

Abstract translation: 提供具有电连接结构的电路板及其制造方法。 提供具有内层电路的电路板主体。 电路层形成在电路板主体的至少最外表面上，并且包括电连接焊盘和电路。 电连接焊盘部分地电连接到电路，并且经由导电通孔部分地电连接到内层电路。 绝缘保护层设置在电路板主体上，并在其中形成有用于暴露电连接焊盘的开口。 导电柱形成在电连接焊盘上。 独立的金属焊盘形成在绝缘保护层上，但不用于电连接。 在独立的金属焊盘之下的绝缘保护层中不存在导电柱和电连接焊盘，使得电路可以形成在绝缘保护层下面。

公开(公告)号：US20090049688A1

公开(公告)日：2009-02-26

申请号：US12127432

申请日：2008-05-27

Applicant: Gareth G. Hougham ,  Brian S. Beaman ,  Evan G. Colgan ,  Paul W. Coteus ,  Stefano S. Oggioni ,  Enrique Vargas

Inventor： Gareth G. Hougham ,  Brian S. Beaman ,  Evan G. Colgan ,  Paul W. Coteus ,  Stefano S. Oggioni ,  Enrique Vargas

IPC: H05K3/00

CPC classification number: H01R12/714 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01R12/52 ,  H05K3/326 ,  H05K3/4007 ,  H05K7/1061 ,  H05K2201/0133 ,  H05K2201/0367 ,  H05K2201/09481 ,  H05K2201/09745 ,  H05K2201/10378 ,  H05K2201/10734 ,  Y10T29/49002 ,  Y10T29/49121 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49147 ,  Y10T29/49149 ,  Y10T29/49151 ,  Y10T29/49155 ,  Y10T29/49158 ,  Y10T29/49165 ,  Y10T29/49204 ,  Y10T29/49208 ,  Y10T29/49213 ,  Y10T29/49218 ,  Y10T29/49222 ,  H01L2924/00

Abstract: A method of producing a land grid array (LGA) interposer structure, including an electrically insulating carrier plane, and at least one interposer mounted on a first surface of said carrier plane. The interposer possesses a hemi-toroidal configuration in transverse cross-section and is constituted of a dielectric elastomeric material. A plurality of electrically-conductive elements are arranged about the surface of the at least one hemi-toroidal interposer and extend radically inwardly and downwardly from an uppermost end thereof into electrical contact with at least one component located on an opposite side of the electrically insulating carrier plane.

Abstract translation: 一种制造包括电绝缘载体平面的平面栅格阵列（LGA）插入器结构以及安装在所述载体平面的第一表面上的至少一个插入件的方法。 插入件在横截面中具有半环形结构，并由介电弹性体材料构成。 多个导电元件围绕至少一个半环形插入器的表面布置并且从其最上端向内和向下自由地延伸至与位于电绝缘载体的相对侧上的至少一个部件的电接触 飞机

公开(公告)号：US20090042414A1

公开(公告)日：2009-02-12

申请号：US12249035

申请日：2008-10-10

Applicant: Gareth G. Hougham ,  Keith E. Fogel ,  Paul A. Lauro ,  Joseph Zinter, JR.

Inventor： Gareth G. Hougham ,  Keith E. Fogel ,  Paul A. Lauro ,  Joseph Zinter, JR.

IPC: H01R12/00

CPC classification number: H01R13/2414 ,  H01R12/7082 ,  H01R12/714 ,  H01R43/007 ,  H05K3/4007 ,  H05K3/42 ,  H05K7/1061 ,  H05K2201/0133 ,  H05K2201/0367 ,  H05K2201/0959 ,  H05K2201/10378 ,  Y10S439/931 ,  Y10T442/109 ,  Y10T442/172

Abstract: Methods for fabricating Land Grid Array (LGA) interposer contacts that are both conducting and elastic. Also provided are LGA interposer contacts as produced by the inventive methods. Provided is LGA type which utilizes a pure unfilled elastomer button core that is covered with an electrically-conductive material that is continuous from the top surface to the bottom surface of the button structure. In order to obviate the disadvantages and drawbacks which are presently encountered in the technology pertaining to the fabrication and structure of land grid arrays using electrically-conductive interposer contacts, there is provided both methods and structure for molding elastomer buttons into premetallized LGA carrier sheets, and wherein the non-conductive elastomer buttons are surface-metallized in order to convert them into conductive electrical contacts.

Abstract translation: 制造导电和弹性的Land Grid Array（LGA）插入器触点的方法。 还提供了通过本发明的方法制造的LGA插入器触点。 提供了LGA型，其利用由从按钮结构的顶表面到底表面连续的导电材料覆盖的纯未填充弹性体按钮芯。 为了消除在使用导电插入器触点的地面栅格阵列的制造和结构的技术中目前遇到的缺点和缺点，提供了用于将弹性体按钮模制成预金属化的LGA载体片的方法和结构，以及 其中非导电弹性体按钮被表面金属化以便将它们转换为导电电触点。

公开(公告)号：US07484293B2

公开(公告)日：2009-02-03

申请号：US11567804

申请日：2006-12-07

Applicant: Yoshiyuki Yamaji ,  Hirokazu Noma ,  Hiroyuki Mori

Inventor： Yoshiyuki Yamaji ,  Hirokazu Noma ,  Hiroyuki Mori

IPC: H05K3/34

CPC classification number: H01L21/6835 ,  H01L21/4853 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/66 ,  H01L2223/6616 ,  H01L2224/11003 ,  H01L2224/16 ,  H01L2924/01078 ,  H01L2924/15311 ,  H01L2924/30105 ,  H05K1/0216 ,  H05K3/4015 ,  H05K3/4602 ,  H05K2201/0367 ,  H05K2201/0792 ,  H05K2201/09481 ,  H05K2201/096 ,  H05K2201/09909 ,  H05K2201/09981 ,  H05K2203/0113 ,  H05K2203/0235 ,  H05K2203/0338 ,  Y10T29/49144 ,  Y10T29/49147 ,  Y10T29/49149

Abstract: A semiconductor package that has a superior high frequency characteristics and that can obtain a large area for an internal wiring pattern is provided. According to the present invention, a semiconductor package includes: a multilayer printed wiring board 12, and an IC chip, mounted on the obverse face of the multilayer wiring board 12, and multiple bump terminals 16, mounted on the reverse face. Each bump terminal 16 includes an insulating core 42 having a flat face 40 and a conductive coating deposited on all external surfaces except that of the flat face 40. The end faces of the conductive coatings 44 appear like rings around the insulating cores 42, and are soldered to annular connection pads 52 formed on the reverse face of the multilayer printed wiring board 12. Vias 36 are arranged immediately above the bump terminals 16, and clearance holes 34, the diameter of which is smaller than the diameter of the bump terminals 16, are formed in internal wiring patterns 28 and 30 to permit the passage of the vias 36.

Abstract translation: 提供了具有优异的高频特性并且可以获得用于内部布线图案的大面积的半导体封装。 根据本发明，半导体封装包括：安装在多层布线板12的正面上的多层印刷布线板12和IC芯片以及安装在反面上的多个凸点端子16。 每个凸块端子16包括具有平坦面40的绝缘芯42和沉积在除了平面40之外的所有外表面上的导电涂层。导电涂层44的端面看起来像围绕绝缘芯42的环，并且是 焊接到形成在多层印刷电路板12的背面上的环形连接焊盘52.通孔36布置在凸块端子16的正上方，并且直径小于凸块端子16的直径的间隙孔34， 形成在内部布线图案28和30中以允许通孔36通过。

公开(公告)号：US07473102B2

公开(公告)日：2009-01-06

申请号：US11395355

申请日：2006-03-31

Applicant: Evan George Colgan ,  Paul W. Coteus ,  Hubert Harrer ,  Gareth Geoffrey Hougham ,  John Harold Magerlein ,  John Torok

Inventor： Evan George Colgan ,  Paul W. Coteus ,  Hubert Harrer ,  Gareth Geoffrey Hougham ,  John Harold Magerlein ,  John Torok

IPC: H01R12/00

CPC classification number: H05K1/141 ,  H01L23/13 ,  H01L23/49811 ,  H01L23/49838 ,  H01L2224/16225 ,  H01L2224/73253 ,  H01L2924/09701 ,  H01L2924/3011 ,  H01R12/7082 ,  H01R13/2414 ,  H05K2201/0367 ,  H05K2201/049 ,  H05K2201/10378 ,  H05K2201/10719

Abstract: An electronic apparatus includes first and second level package structures and an LGA (land grid array) interposer. The first level package structure includes a package substrate, one or more integrated circuit chips mounted on a first surface of the package substrate, and a first pattern of I/O contacts with pitch P1 formed on a second surface of the package substrate opposite the first surface. The second level package structure includes a second pattern of I/O contacts with pitch P2, wherein P2 is not equal to P1. The LGA interposer is disposed between the first and second level package structures and provides space transform electrical interconnections between the first second patterns of I/O contacts, and further includes a dummy contact formed on at least a first or second surface of the LGA interposer and aligned to an LGA contact on an opposing surface of the LGA interposer.

Abstract translation: 电子设备包括第一和第二级封装结构以及LGA（焊盘格阵列）插入器。 第一级封装结构包括封装衬底，安装在封装衬底的第一表面上的一个或多个集成电路芯片，以及形成在封装衬底的第二表面上的第一图案的I / O触点，其间距P1与第一 表面。 第二级封装结构包括具有间距P2的I / O触点的第二模式，其中P2不等于P1。 LGA插入器设置在第一和第二级封装结构之间并且在I / O触点的第一第二图案之间提供空间变换电互连，并且还包括形成在LGA插入件的至少第一或第二表面上的虚拟触点和 与LGA插入器的相对表面上的LGA接触对准。

公开(公告)号：US20080314633A1

公开(公告)日：2008-12-25

申请号：US12149522

申请日：2008-05-02

Applicant: Myung Sam Kang ,  Chin Kwan Kim

Inventor： Myung Sam Kang ,  Chin Kwan Kim

IPC: H01R12/04

CPC classification number: H05K3/4007 ,  H05K3/246 ,  H05K3/3457 ,  H05K3/4069 ,  H05K2201/0347 ,  H05K2201/0367 ,  H05K2201/0376 ,  H05K2201/09481 ,  H05K2201/09745

Abstract: A printed circuit board, which increases the contact area between an IC and a printed circuit board, thus increasing the degree of adhesion, is disclosed. The printed circuit board includes: an insulation layer which includes a first circuit pattern, including at least one via land, embedded in the upper surface of the insulation layer to be flush with the upper surface, and a second circuit pattern formed in the lower surface of the insulation layer to be flush with the lower surface; a solder resist layer formed on the insulation layer; a via hole and a bump integrally formed on the second circuit pattern through the via hole and the via land such that it protrudes from the insulation layer to be higher than the solder resist layer.

Abstract translation: 公开了一种印刷电路板，其增加了IC和印刷电路板之间的接触面积，从而增加了粘合度。 印刷电路板包括：绝缘层，其包括嵌入在绝缘层的上表面中以与上表面齐平的至少一个通孔焊盘的第一电路图案，以及形成在下表面中的第二电路图案 的绝缘层与下表面齐平; 形成在绝缘层上的阻焊层; 通孔和通过通孔和通孔焊盘一体地形成在第二电路图案上的突起，使得其从绝缘层突出成高于阻焊层。