公开(公告)号：US20050039948A1

公开(公告)日：2005-02-24

申请号：US10921525

申请日：2004-08-19

Applicant: Motoo Asai ,  Dongdong Wang ,  Takahiro Mori

Inventor： Motoo Asai ,  Dongdong Wang ,  Takahiro Mori

IPC: H01L21/48 ,  H01L23/498 ,  H05K1/03 ,  H05K3/00 ,  H05K3/10 ,  H05K3/18 ,  H05K3/38 ,  H05K3/42 ,  H05K3/46 ,  H05K1/11

CPC classification number: H05K3/423 ,  H01L21/486 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/15312 ,  H05K1/036 ,  H05K3/0032 ,  H05K3/0035 ,  H05K3/0038 ,  H05K3/108 ,  H05K3/181 ,  H05K3/381 ,  H05K3/385 ,  H05K3/387 ,  H05K3/388 ,  H05K3/426 ,  H05K3/427 ,  H05K3/4602 ,  H05K2201/0195 ,  H05K2201/0352 ,  H05K2201/0355 ,  H05K2201/0394 ,  H05K2201/09536 ,  H05K2201/09563 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2201/09736 ,  H05K2201/09881 ,  H05K2203/0315 ,  H05K2203/0733 ,  H05K2203/0773 ,  H05K2203/1476 ,  Y10T29/49126 ,  Y10T29/49144 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2224/05599

Abstract: A metal layer 18 is sandwiched between insulating layers 14 and 20 so that required strength is maintained. Hence it follows that the thickness of a core substrate 30 can be reduced and, therefore, the thickness of a multi-layer printed circuit board can be reduced. Formation of non-penetrating openings 22 which reach the metal layer 18 in the insulating layers 14 and 20 is simply required. Therefore, small non-penetrating openings 22 can easily be formed by applying laser beams. Thus, through holes 36 each having a small diameter can be formed.

Abstract translation: 金属层18夹在绝缘层14和20之间，从而保持所需的强度。 因此，可以减小芯基板30的厚度，因此可以减小多层印刷电路板的厚度。 仅仅需要在绝缘层14和20中到达金属层18的非穿透开口22的形成。 因此，通过施加激光束可以容易地形成小的非穿透开口22。 因此，可以形成各自具有小直径的通孔36。

公开(公告)号：US20050029014A1

公开(公告)日：2005-02-10

申请号：US10934389

申请日：2004-09-07

Applicant: Shigeki Miura

Inventor： Shigeki Miura

IPC: H01L21/60 ,  H01L21/48 ,  H05K1/11 ,  H05K3/10 ,  H05K3/38 ,  H05K3/42 ,  B32B3/26

CPC classification number: H01L21/4846 ,  H01L21/4864 ,  H05K3/108 ,  H05K3/381 ,  H05K3/388 ,  H05K3/423 ,  H05K3/426 ,  H05K2201/0154 ,  H05K2201/0355 ,  H05K2201/0394 ,  H05K2201/09509 ,  H05K2201/09563 ,  H05K2201/09609 ,  H05K2203/092 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T428/24917

Abstract: A conductive sheet according to the present invention includes: an insulating substrate having at least one via hole, a ground conductive layer; and a top conductive layer, and characterized in that the via hole is a fine pore penetrating through the insulating substrate, the ground conductive layer is formed by a sputtering method or a vapor deposition method on all of a surface of the insulating substrate, the top conductive layer is formed on all of or part of a surface of the ground conductive layer, and the via hole is filled with the top conductive layer.

Abstract translation: 根据本发明的导电片包括：具有至少一个通孔的绝缘基底，接地导电层; 和导电层，其特征在于，所述通孔是穿过所述绝缘基板的细孔，所述接地导电层通过溅射法或气相沉积法形成在所述绝缘基板的所有表面上，所述顶部 导电层形成在接地导电层的表面的全部或一部分上，并且通孔填充有顶部导电层。

公开(公告)号：US06848178B2

公开(公告)日：2005-02-01

申请号：US10437041

申请日：2003-05-14

Applicant: Koji Kondo ,  Ryohei Kataoka ,  Gentaro Masuda

Inventor： Koji Kondo ,  Ryohei Kataoka ,  Gentaro Masuda

IPC: H05K1/02 ,  H01L23/12 ,  H01L23/498 ,  H05K3/10 ,  H05K3/24 ,  H05K3/40 ,  H05K3/46 ,  H04K1/14

CPC classification number: H05K3/4632 ,  H01L23/498 ,  H01L23/49822 ,  H01L23/49838 ,  H01L2924/0002 ,  H05K3/4069 ,  H05K3/4617 ,  H05K2201/0129 ,  H05K2201/0394 ,  H05K2201/09881 ,  Y10T29/49165 ,  H01L2924/00

Abstract: A multilayer circuit board, in which a plurality of insulating layers and a plurality of conductive layers, each of which includes a conductive pattern, have been laminated, includes an insulating layer, a conductive compound, and a conductive pattern. The insulating layer has a trench. The conductive compound is located in the trench. The conductive pattern adjoins the trench and is electrically connected to the conductive compound. The conductive pattern and the conductive compound make up a conductive wire that has a higher current-carrying capacity than the conductive pattern.

Abstract translation: 层叠有多个绝缘层和多个导体层的多层电路基板，其中，所述多个绝缘层和多个导体层包含导体图案，其中包括绝缘层，导电性化合物和导体图案。 绝缘层具有沟槽。 导电化合物位于沟槽中。 导电图案与沟槽相邻并且与导电化合物电连接。 导电图案和导电化合物组成导电线，其具有比导电图案更高的载流能力。

公开(公告)号：US20040256739A1

公开(公告)日：2004-12-23

申请号：US10893993

申请日：2004-07-20

Applicant: Seiko Epson Corporation

Inventor： Nobuaki Hashimoto

IPC: H01L021/48 ,  H01L023/52

CPC classification number: H01L24/29 ,  H01L21/4853 ,  H01L21/563 ,  H01L23/3114 ,  H01L23/49816 ,  H01L23/4985 ,  H01L23/552 ,  H01L24/13 ,  H01L24/16 ,  H01L24/75 ,  H01L24/83 ,  H01L24/90 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/29101 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/75252 ,  H01L2224/83095 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83851 ,  H01L2224/83859 ,  H01L2224/83862 ,  H01L2224/83874 ,  H01L2224/90 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/0781 ,  H01L2924/15183 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/3025 ,  H05K1/112 ,  H05K1/189 ,  H05K3/28 ,  H05K3/284 ,  H05K3/323 ,  H05K2201/0394 ,  H05K2201/09472 ,  H05K2201/10674 ,  H05K2203/0278 ,  Y10T29/49117 ,  Y10T29/4913 ,  Y10T29/49144 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2224/05624 ,  H01L2224/05644

Abstract: A method of manufacturing a semiconductor device comprises: a first step of interposing a thermosetting anisotropic conductive material 16 between a substrate 12 and a semiconductor chip 20; a second step in which pressure and heat are applied between the semiconductor chip 20 and the substrate 12, an interconnect pattern 10 and electrodes 22 are electrically connected, and the anisotropic conductive material 16 is spreading out beyond the semiconductor chip 20 and is cured in the region of contact with the semiconductor chip 20; and a third step in which the region of the anisotropic conductive material 16 other than the region of contact with the semiconductor chip 20 is heated.

Abstract translation: 一种制造半导体器件的方法包括：在基板12和半导体芯片20之间插入热固性各向异性导电材料16的第一步骤; 在半导体芯片20和基板12之间施加压力和热量的第二步骤，布线图案10和电极22电连接，并且各向异性导电材料16扩散到半导体芯片20之外并在 与半导体芯片20的接触区域; 以及第三步骤，其中除了与半导体芯片20的接触区域之外的各向异性导电材料16的区域被加热。

公开(公告)号：US06822191B2

公开(公告)日：2004-11-23

申请号：US10378600

申请日：2003-03-05

Applicant: Hubert De Steur ,  Stefan Lesjak ,  Wei Pan

Inventor： Hubert De Steur ,  Stefan Lesjak ,  Wei Pan

IPC: B23K2636

CPC classification number: B23K26/0661 ,  B23K26/066 ,  B23K26/18 ,  B23K26/389 ,  B23K2101/36 ,  B23K2103/42 ,  B23K2103/50 ,  H05K1/0219 ,  H05K1/0366 ,  H05K3/0032 ,  H05K3/0035 ,  H05K2201/0394 ,  H05K2201/09036 ,  H05K2201/09981 ,  H05K2203/0554 ,  H05K2203/108

Abstract: In order to produce a trench structure having steep sidewalls free of residues in an, in particular, glass-fiber-reinforced substrate, the substrate is provided with a conformal mask having cutouts corresponding to the trench structure to be produced. In this case, the laser beam is guided over the cutouts of the mask in such a way that the low-energy edge regions of the laser beam are shielded and that proportion of the laser beam which impinges on the polymer surface, at each point, has an energy density above a threshold at which the substrate material including a glass fiber reinforcement that is possibly present is completely removed.

Abstract translation: 为了在特别是玻璃纤维增​​强的基板中产生具有不含残留物的陡峭的侧壁的沟槽结构，衬底设置有具有对应于待生产的沟槽结构的切口的保形掩模。 在这种情况下，激光束被引导到掩模的切口上，使得激光束的低能边缘区域被屏蔽，并且在每个点处撞击在聚合物表面上的激光束的比例， 具有高于阈值的能量密度，其中包括可能存在的玻璃纤维增​​强材料的基底材料被完全去除。

公开(公告)号：US20040228038A1

公开(公告)日：2004-11-18

申请号：US10733105

申请日：2003-12-10

Applicant: Hitachi Global Storage Technologies Japan, Ltd.

Inventor： Shigeo Nakamura ,  Naoki Maeda ,  Shinobu Hagiya ,  Haruhide Takahashi ,  Kousaku Wakatsuki

IPC: G11B005/55

CPC classification number: H05K1/118 ,  G11B5/4813 ,  G11B5/4826 ,  G11B5/4846 ,  H05K1/0281 ,  H05K1/056 ,  H05K2201/0394 ,  H05K2201/053 ,  H05K2201/2009 ,  H05K2201/2018

Abstract: To strengthen a flying lead portion of a long-tail flexible printed circuit (FPC) integrally formed with a flexure, stacked support portions of resin layers on both sides of a flying lead 7 of a long-tail FPC 6 are reinforced with metal frames 14. A fold-back portion 9 of the long-tail FPC 6 is folded back at 90 degrees so that flying lead 7 is disposed parallel with a turning shaft 21 of a carriage 20. The flying lead is then joined to a connection pad 26 on a main FPC board 24 using solder 18.

Abstract translation: 为了加强与挠曲件一体形成的长尾柔性印刷电路（FPC）的飞行引导部分，长尾翼FPC 6的飞行引线7的两侧的树脂层的堆叠支撑部分被金属框架14加强 长尾FPC6的折回部分9以90度折回，使得飞行引线7与滑架20的转动轴21平行设置。然后将飞行引线接合到连接垫26上 使用焊料18的主FPC基板24。

公开(公告)号：US20040208933A1

公开(公告)日：2004-10-21

申请号：US10842526

申请日：2004-05-11

Inventor： Koji Kondo

IPC: H05K001/00 ,  A61K009/14

CPC classification number: H05K3/4632 ,  H01L2224/1147 ,  H05K1/0206 ,  H05K1/056 ,  H05K3/244 ,  H05K3/4069 ,  H05K3/4617 ,  H05K2201/0129 ,  H05K2201/0394 ,  H05K2203/072 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49163

Abstract: A multilayer circuit board that has electrodes only on one surface is manufactured as follows. A plurality of conductor layers are formed on a resin film made of thermoplastic resin to form a single-sided conductor layer film. Then, a plurality of via-holes 24, which are bottomed by the conductor layers, are formed in the resin film. Then interlayer connecting material is packed in the via-holes 24 to form a single-sided conductor layer film having the interlayer connecting material. A plurality of single-sided conductor layer films are formed and stacked such that surfaces having the conductor layers face in the same direction. Then, the single-sided conductor layer films are pressed and heated to complete the multilayer circuit board. The multilayer circuit board is formed by using only the single-sided conductor layer films and pressing once, so the manufacturing process is simplified.

Abstract translation: 仅在一个表面上具有电极的多层电路板制造如下。 在由热塑性树脂制成的树脂膜上形成多个导体层以形成单面导体层膜。 然后，在树脂膜中形成有由导体层底部的多个通路孔24。 然后将层间连接材料包装在通孔24中，以形成具有层间连接材料的单面导体层膜。 多个单面导体层膜被形成并堆叠，使得具有导体层的表面面向相同的方向。 然后，对单面导体层膜进行加压加热以完成多层电路板。 多层电路板仅使用单面导体层膜并按压一次形成，因此制造工艺简化。

公开(公告)号：US20040198033A1

公开(公告)日：2004-10-07

申请号：US10829778

申请日：2004-04-22

Inventor： Teck Kheng Lee ,  Kian Chai Lee ,  Sian Yong Khoo

IPC: H01L021/44

CPC classification number: H05K3/4007 ,  H01L21/4853 ,  H01L21/486 ,  H01L23/49827 ,  H01L24/97 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K3/243 ,  H05K2201/0367 ,  H05K2201/0394 ,  H05K2201/10378 ,  H05K2203/1572 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/05599

Abstract: An apparatus and method for improving the yield and reducing the cost of forming a semiconductor device assembly. An interposer substrate is formed with interconnections in the form of conductive bumps on both a first surface and a second surface to provide a respective first level interconnect and a second level interconnect for a semiconductor die to be mounted to the interposer substrate. The conductive bumps and conductive elements may be formed simultaneously by a plating process. The conductive bumps on the first surface are arranged to correspond with bond pads of a semiconductor die for the first level interconnect. The conductive bumps on the second surface are configured to correspond with a terminal pad pattern of a carrier substrate or other higher-level packaging.

公开(公告)号：US20040172814A1

公开(公告)日：2004-09-09

申请号：US10788392

申请日：2004-03-01

Inventor： Akiji Shibata ,  Toyoharu Koizumi ,  Tsuyoshi Ishihara ,  Takashi Sato

IPC: H05K001/02

CPC classification number: H05K3/0094 ,  H01L21/4857 ,  H01L21/486 ,  H05K1/183 ,  H05K3/108 ,  H05K3/421 ,  H05K2201/0355 ,  H05K2201/0394 ,  H05K2201/09581 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: This invention reduces the amount of time required to manufacture double-sided printed circuit boards that contain conductor bridges. A method for producing a printed circuit board comprising the steps of forming a first conductor pattern on a first main side of an insulating board, forming a second conductor pattern which is electrically connected to said first conductor pattern on a side (hereinafter termed a second main side) opposite to said first main side of said insulating board, and forming holes in preset areas of said insulating board, wherein the step of forming the second conductor pattern forms the seconds conductor pattern so that part of said pattern may pass over the holes in the insulating board; wherein said method further comprises the steps of forming holes which pass through said insulating board and said first conductor layer formed on the first main side of the insulating board, bonding a second conductor layer to the second main side of the insulating board having said holes, forming a third conductor layer on the whole first main side of said insulating board after bonding the second conductor layer, masking preset holes among those formed by said hole forming process with a plating resist, plating said first conductor and holes in said insulating board, patterning said first conductor layer to form a first conductor pattern, patterning said second conductor layer to form a second conductor pattern, and removing said plating resist and said third conductor layer from an area which is covered with the plating resist.

Abstract translation: 本发明减少制造包含导体桥的双面印刷电路板所需的时间。 一种制造印刷电路板的方法，包括以下步骤：在绝缘板的第一主侧上形成第一导体图案，形成第二导体图案，该第二导体图案在侧面电连接到所述第一导体图案（以下称为第二主体 侧），并且在所述绝缘板的预设区域中形成孔，其中形成所述第二导体图案的步骤形成所述秒导体图案，使得所述图案的一部分可以越过所述绝缘板的所述孔 绝缘板; 其特征在于，所述方法还包括以下步骤：形成穿过所述绝缘板和形成在绝缘板的第一主侧上的第一导体层的孔，将第二导体层接合到具有所述孔的绝缘板的第二主侧， 在接合第二导体层之后，在所述绝缘板的整个第一主侧上形成第三导体层，在由所述孔形成工艺形成的那些之间用电镀抗蚀剂掩蔽预定孔，将所述第一导体和所述绝缘板中的孔， 所述第一导体层形成第一导体图案，图案化所述第二导体层以形成第二导体图案，并且从被电镀抗蚀剂覆盖的区域移除所述电镀抗蚀剂和所述第三导体层。

公开(公告)号：US20040159462A1

公开(公告)日：2004-08-19

申请号：US10774882

申请日：2004-02-09

Inventor： Kevin Kwong-Tai Chung

IPC: H05K001/03 ,  H05K001/11

CPC classification number: B32B37/203 ,  B32B2425/00 ,  B32B2429/00 ,  G06K19/07743 ,  G06K19/07745 ,  G06K19/07747 ,  H01L23/055 ,  H01L23/49838 ,  H01L23/4985 ,  H01L23/49855 ,  H01L23/5387 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/05001 ,  H01L2224/05023 ,  H01L2224/05026 ,  H01L2224/05548 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2225/06579 ,  H01L2225/06582 ,  H01L2225/06586 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01046 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15173 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/19041 ,  H01Q1/22 ,  H01Q1/2225 ,  H01Q1/36 ,  H01Q1/38 ,  H01Q7/00 ,  H01Q7/005 ,  H01Q23/00 ,  H05K1/0393 ,  H05K1/113 ,  H05K1/165 ,  H05K3/4069 ,  H05K3/423 ,  H05K2201/0355 ,  H05K2201/0394 ,  H05K2201/10674 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05669 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155

Abstract: A molecularly flexible dielectric electronic substrate for receiving an electronic device includes a sheet or layer of a molecularly flexible dielectric adhesive having patterned metal foil electrical conductors thereon.

Abstract translation: 用于接收电子器件的分子柔性电介质电子衬底包括其上具有图案化金属箔电导体的分子柔性电介质粘合剂的片或层。