公开(公告)号：US20110283535A1

公开(公告)日：2011-11-24

申请号：US13195936

申请日：2011-08-02

Applicant: Akio HORIUCHI ,  Kazuhiro Oshima

Inventor： Akio HORIUCHI ,  Kazuhiro Oshima

IPC: H01K3/10

CPC classification number: H05K1/116 ,  H05K3/108 ,  H05K3/244 ,  H05K3/427 ,  H05K3/4602 ,  H05K2201/0347 ,  H05K2201/09454 ,  H05K2201/09536 ,  H05K2201/0959 ,  Y10T29/49126 ,  Y10T29/49165

Abstract: A wiring board is provided. The wiring board includes: a resin substrate having a through-hole therethrough; metal foil patterns formed on the resin substrate; and a first wiring layer formed on the metal foil patterns and on an inner surface of the through-hole, wherein the first wiring layer includes: a first power feeding layer; and a first plated layer laminated on the first power feeding layer; a resin member filled in the through-hole and between adjacent wiring patterns of the first wiring layer, wherein an end surface of the resin member is flush with a surface of the first wiring layer; and a second wiring layer formed on the surface of the first wiring layer and formed to cover an end surface of the through-hole, wherein the second wiring layer includes: a second power feeding layer; and a second plated layer laminated on the second power feeding layer.

Abstract translation: 提供接线板。 布线板包括：具有穿过其的通孔的树脂基板; 形成在树脂基板上的金属箔图案; 以及形成在所述金属箔图案上和所述通孔的内表面上的第一布线层，其中所述第一布线层包括：第一馈电层; 以及层叠在所述第一供电层上的第一镀层; 填充在所述通孔中并且在所述第一布线层的相邻布线图案之间的树脂构件，其中所述树脂构件的端面与所述第一布线层的表面齐平; 以及形成在所述第一布线层的表面上并形成为覆盖所述通孔的端面的第二布线层，其中所述第二布线层包括：第二馈电层; 以及层叠在第二供电层上的第二镀层。

公开(公告)号：US08030579B2

公开(公告)日：2011-10-04

申请号：US12099957

申请日：2008-04-09

Applicant: Yukihiko Toyoda ,  Yoichiro Kawamura ,  Tomoyuki Ikeda

Inventor： Yukihiko Toyoda ,  Yoichiro Kawamura ,  Tomoyuki Ikeda

IPC: H01R12/04 ,  H05K1/11

CPC classification number: H05K1/115 ,  H01L21/486 ,  H01L23/49827 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/3011 ,  H05K1/0271 ,  H05K1/113 ,  H05K1/116 ,  H05K3/28 ,  H05K3/4602 ,  H05K3/4644 ,  H05K3/4661 ,  H05K3/4688 ,  H05K2201/0133 ,  H05K2201/0209 ,  H05K2201/0212 ,  H05K2201/068 ,  H05K2201/09454 ,  H05K2201/09536 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2201/09627 ,  H05K2201/09745 ,  H01L2924/00

Abstract: An object of the present invention is to provide a multilayered printed circuit board having a short wiring distance of the conductor circuits, wide option of the design of the conductor circuits and additionally excellent in reliability since cracking scarcely takes place in the interlaminar resin insulating layers in the vicinity of via-holes. The present invention is a multilayered printed circuit board comprising: a conductor circuit and an interlaminar resin insulating layer serially formed on a substrate in alternate fashion and in repetition, wherein a connection of the conductor circuits through the interlaminar resin insulating layers is performed by a via-hole, wherein via-holes in different level layers among the via-holes are formed so as to form a stack-via structure, and wherein at least one of the land diameters of the above-mentioned via-holes in different level layers having the stack via structure is different from the land diameters of other via-holes.

Abstract translation: 本发明的目的是提供一种具有导体电路的布线距离短的多层印刷电路板，可广泛选择导体电路的设计，并且由于在层间树脂绝缘层中几乎不发生破裂 通孔附近。 本发明是一种多层印刷电路板，包括：导体电路和层间树脂绝缘层，其以交替的方式和重复地串联形成在基板上，其中通过层间树脂绝缘层的导体电路的连接通过通孔 孔，其中形成通孔中的不同级别的通孔，以形成堆叠通孔结构，并且其中不同层级中的上述通孔的平台直径中的至少一个具有 堆叠通孔结构不同于其它通孔的焊盘直径。

公开(公告)号：US20110000707A1

公开(公告)日：2011-01-06

申请号：US12826276

申请日：2010-06-29

Applicant: Satoshi Kawai

Inventor： Satoshi Kawai

IPC: H05K1/11

CPC classification number: H05K1/116 ,  H05K1/0224 ,  H05K1/113 ,  H05K3/429 ,  H05K2201/062 ,  H05K2201/0723 ,  H05K2201/093 ,  H05K2201/09454 ,  H05K2201/0969 ,  H05K2201/09709

Abstract: An electronic circuit unit includes a multi-layer substrate in which high frequency circuits are provided on two different layers and a ground layer is formed between the two layers, and grounding lands connected to peripheral conductive members through connection bars formed on a plurality of layers of the multi-layer substrate. The grounding lands are connected to each other through a via hole and conducted to the ground layer, and the connection bars protruding radially outward from at least two grounding lands provided on different layers are arranged in different directions with respect to a circumferential direction such that the connection bars do not overlap each other along a thickness direction of the multi-layer substrate.

Abstract translation: 电子电路单元包括多层基板，其中高频电路设置在两个不同的层上，并且在两层之间形成接地层，以及通过形成在多个层上的连接条连接到外围导电构件的接地区 多层基板。 接地平台通过通孔相互连接并传导到接地层，并且从设置在不同层上的至少两个接地台径向向外突出的连接杆相对于圆周方向布置在不同的方向上，使得 连接条不沿着多层基板的厚度方向彼此重叠。

公开(公告)号：US20100314163A1

公开(公告)日：2010-12-16

申请号：US12485375

申请日：2009-06-16

Applicant: Craig Twardy ,  Robert McDonald

Inventor： Craig Twardy ,  Robert McDonald

IPC: H05K1/11 ,  G01R19/00 ,  G01R31/02 ,  H01R43/00

CPC classification number: H05K3/0047 ,  G01R31/024 ,  H05K1/0245 ,  H05K1/0251 ,  H05K1/0268 ,  H05K1/116 ,  H05K3/429 ,  H05K2201/09454 ,  H05K2201/09627 ,  H05K2201/09636 ,  H05K2201/09718 ,  H05K2201/09781 ,  H05K2203/0207 ,  H05K2203/0242 ,  H05K2203/175 ,  Y10T29/49117

Abstract: A method is disclosed for fabricating a PCB so that is can easily be determined if a via in the PCB has not been counterbored to a desired depth. A PCB fabricated according to the method also is disclosed.

Abstract translation: 公开了一种用于制造PCB的方法，使得如果PCB中的通孔没有被吸入到期望的深度，则可以容易地确定。 公开了根据该方法制造的PCB。

公开(公告)号：US20100264933A1

公开(公告)日：2010-10-21

申请号：US12648383

申请日：2009-12-29

Applicant: CHUN-SHAN HSIAO

Inventor： CHUN-SHAN HSIAO

IPC: G01R31/02

CPC classification number: G06F17/5068 ,  H05K1/116 ,  H05K3/0005 ,  H05K3/0047 ,  H05K3/429 ,  H05K2201/09454 ,  H05K2201/09718

Abstract: A system and method for testing size of vias reads a component group from a storage system and reads a via size of each via in the component group. If the via size of a via accords with a standard size corresponding to the component group, the via is determined as a qualified via. If the via size of a via does not accord with the standard size, the via is determined as an unqualified via. The unqualified via is highlighted on a printed circuit board (PCB) design map displayed on a display.

Abstract translation: 用于测试通孔尺寸的系统和方法从存储系统读取组件组，并读取组件组中每个通孔的通孔尺寸。 如果通孔的通孔尺寸符合与组件组对应的标准尺寸，则将通孔确定为合格通孔。 如果通孔的通孔尺寸不符合标准尺寸，则通孔被确定为不合格通孔。 不合格的通孔在显示屏上显示的印刷电路板（PCB）设计图上突出显示。

公开(公告)号：US20100259338A1

公开(公告)日：2010-10-14

申请号：US12801673

申请日：2010-06-21

Applicant: Uei-Ming Jow ,  Ching-Liang Weng ,  Ying-Jiunn Lai ,  Chang-Sheng Chen

Inventor： Uei-Ming Jow ,  Ching-Liang Weng ,  Ying-Jiunn Lai ,  Chang-Sheng Chen

IPC: H03H7/38

CPC classification number: H05K1/0251 ,  H01L23/66 ,  H01L2223/6616 ,  H01L2223/6638 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/3011 ,  H01P5/02 ,  H05K1/0222 ,  H05K1/0245 ,  H05K1/115 ,  H05K1/116 ,  H05K3/429 ,  H05K2201/09236 ,  H05K2201/09454 ,  H05K2201/09618 ,  H05K2201/09627 ,  H05K2201/09809 ,  H05K2201/09845 ,  H01L2924/00

Abstract: A high frequency and wide band impedance matching via is provided, applicable to multi-layer printed circuit boards, for example. The multi-layer circuit board may include several signal transmission traces, several ground layers, signal transmission vias and ground vias. The signal transmission traces and the ground layers may be sited on different circuit layers, and each signal transmission trace may be opposite to one of the ground layers. The signal transmission vias may be connected between the signal transmission traces. The ground vias may be connected between the ground layers. The ground vias may be opposite to the signal transmission vias, and the ground vias corresponding to the signal transmission vias may be sited to stabilize the characteristic impedance of the transmission traces.

Abstract translation: 提供了高频和宽带阻抗匹配通孔，例如适用于多层印刷电路板。 多层电路板可以包括几个信号传输迹线，几个接地层，信号传输通路和接地通孔。 信号传输迹线和接地层可以位于不同的电路层上，并且每个信号传输迹线可以与一个接地层相反。 信号传输通孔可以连接在信号传输迹线之间。 接地通孔可以连接在接地层之间。 接地通孔可能与信号传输通孔相反，并且可能选择对应于信号传输通孔的接地通孔来稳定传输迹线的特性阻抗。

公开(公告)号：US20100193231A1

公开(公告)日：2010-08-05

申请号：US12696962

申请日：2010-01-29

Applicant: Kimihiro YAMANAKA ,  Manabu ICHINOSE ,  Satoshi NAKAMURA

Inventor： Kimihiro YAMANAKA ,  Manabu ICHINOSE ,  Satoshi NAKAMURA

IPC: H05K1/16 ,  H05K1/11

CPC classification number: H05K1/116 ,  H05K1/0271 ,  H05K1/113 ,  H05K3/4644 ,  H05K2201/0769 ,  H05K2201/09454 ,  H05K2201/09509 ,  H05K2201/09627 ,  H05K2201/0969

Abstract: According to one of the invention, a circuit board comprises a conductive layer. The conductive layer includes a first land portion, a second land portion apart from the first land portion in a plan view, and a line portion connecting the first land portion and the second land portion to each other. The line portion includes lead portions through which a current is to flow and an opening portion arranged between the lead portions. The opening portion penetrates the conductive layer in a thickness direction.

Abstract translation: 根据本发明之一，电路板包括导电层。 导电层包括第一接地部分，在平面图中与第一接地部分分开的第二接地部分和将第一接地部分和第二接地部分彼此连接的线路部分。 线部分包括电流流过的引线部分和布置在引线部分之间的开口部分。 开口部在厚度方向上贯通导电层。

公开(公告)号：US20100033262A1

公开(公告)日：2010-02-11

申请号：US11558126

申请日：2006-11-09

Applicant: Angelo M. Puzella ,  Joseph M. Crowder ,  Patricia S. Dupuis ,  Michael C. Fallica ,  John B. Francis ,  Joseph A. Licciardello

Inventor： Angelo M. Puzella ,  Joseph M. Crowder ,  Patricia S. Dupuis ,  Michael C. Fallica ,  John B. Francis ,  Joseph A. Licciardello

IPC: H03H7/38

CPC classification number: H01Q21/0087 ,  H03H7/38 ,  H05K1/0251 ,  H05K1/116 ,  H05K3/429 ,  H05K3/4623 ,  H05K2201/09145 ,  H05K2201/09454 ,  H05K2201/09536 ,  H05K2201/09718 ,  H05K2201/09727 ,  H05K2201/209 ,  H05K2203/061 ,  Y10T29/49165

Abstract: A multilayer circuit board assembly includes one or more radio frequency (RF) interconnects between different circuit layers on different circuit boards which make up the circuit board assembly. The RF interconnects can include one or more RF matching pads which provide a mechanism for matching impedance characteristics of RF stubs to provide the RF interconnects having desired insertion loss and impedance characteristics over a desired RF operating frequency band. The RF matching pads allow the manufacture of circuit boards having RF interconnects without the need to perform any back drill and back fill operation to remove stub portions of the RF interconnects in the multilayer circuit board assembly.

Abstract translation: 多层电路板组件包括构成电路板组件的不同电路板上的不同电路层之间的一个或多个射频（RF）互连。 RF互连可以包括一个或多个RF匹配焊盘，其提供用于匹配RF短截线的阻抗特性的机制，以在期望的RF工作频带上提供具有期望的插入损耗和阻抗特性的RF互连。 RF匹配焊盘允许制造具有RF互连的电路板，而不需要执行任何后钻和反向填充操作以去除多层电路板组件中的RF互连的短截线部分。

公开(公告)号：US20090104772A1

公开(公告)日：2009-04-23

申请号：US12345474

申请日：2008-12-29

Applicant: Cheng-Po Yu

Inventor： Cheng-Po Yu

IPC: H01L21/44 ,  H01L21/02

CPC classification number: H05K1/116 ,  H01L21/6835 ,  H01L2221/68359 ,  H05K3/20 ,  H05K3/4644 ,  H05K3/4658 ,  H05K2201/09454 ,  H05K2201/09563 ,  H05K2201/096 ,  Y10T29/49124

Abstract: A process for forming a circuit structure includes providing a first composite-layer structure at first. A second composite-layer structure is then provided. The first composite-layer structure, a second dielectric layer and the second composite-layer structure are pressed so that a second circuit pattern and an independent via pad are embedded in the second dielectric layer, and the second dielectric layer is connected to the first dielectric layer. A first carrier substrate and a second carrier substrate are removed to expose a first circuit pattern and the second circuit pattern. At least one first opening that passes through the second dielectric layer and exposes the independent via pad is formed, and the first opening is filled with a conductive material to form a second conductive via that connects the independent via pad and a second via pad.

Abstract translation: 一种形成电路结构的工艺包括首先提供第一复合层结构。 然后提供第二复合层结构。 第一复合层结构，第二介电层和第二复合层结构被按压，使得第二电路图案和独立通孔焊盘嵌入第二电介质层中，并且第二电介质层连接到第一电介质层 层。 去除第一载体衬底和第二载体衬底以暴露第一电路图案和第二电路图案。 形成穿过第二电介质层并暴露独立通孔焊盘的至少一个第一开口，并且用导电材料填充第一开口以形成连接独立通孔焊盘和第二通孔焊盘的第二导电通孔。

公开(公告)号：US20080251288A1

公开(公告)日：2008-10-16

申请号：US12099875

申请日：2008-04-09

Applicant: Yuusuke YAMASHITA ,  Ryota Suzuki ,  Masahiro Tanabe ,  Taihei Nakada ,  Tsuyoshi Kumamoto

Inventor： Yuusuke YAMASHITA ,  Ryota Suzuki ,  Masahiro Tanabe ,  Taihei Nakada ,  Tsuyoshi Kumamoto

IPC: H01R12/04

CPC classification number: H05K1/0251 ,  H05K1/0222 ,  H05K1/116 ,  H05K3/429 ,  H05K2201/09454 ,  H05K2201/09618 ,  H05K2201/09718 ,  H05K2201/09809

Abstract: A multilayer high-frequency circuit board includes a signal line, ground layers, and an interlayer circuit. A signal line where a high-frequency signal flows is formed in the signal line layer. The ground layers are laminated on both sides of the signal line layer, each of which is grounded. The interlayer circuit is provided in the signal line layer and includes a ground connecting portion connected to the ground layers and a signal line connecting portion connected to the signal line. One of the signal line connecting portion and the ground connecting portion surrounds an outer periphery of the other of the signal line connecting portion and the ground connecting portion concentrically with the one being separated from the outer periphery of the other along the signal line layer. An inner periphery of the one and the outer periphery of the other have a similar shape excluding a complete circle.

Abstract translation: 多层高频电路板包括信号线，接地层和层间电路。 在信号线层中形成高频信号流动的信号线。 接地层层叠在信号线层的两侧，每一个都接地。 层间电路设置在信号线层中，并且包括连接到接地层的接地连接部分和连接到信号线的信号线连接部分。 信号线连接部分和接地连接部分之一围绕信号线连接部分和接地连接部分的另一个的外周围同步地沿着信号线层与另一个的外周分离。 另一个的一个和外周的内周具有除完整圆之外的类似形状。