公开(公告)号：US09763327B2

公开(公告)日：2017-09-12

申请号：US14834180

申请日：2015-08-24

Applicant: Multek Technologies Ltd.

Inventor： Kwan Pen ,  Pui Yin Yu

IPC: H05K1/11 ,  H05K1/02 ,  H05K3/42 ,  H05K3/46 ,  H05K3/00 ,  H05K3/06 ,  H05K3/18

CPC classification number: H05K1/115 ,  H05K1/0216 ,  H05K1/0298 ,  H05K1/112 ,  H05K3/0058 ,  H05K3/06 ,  H05K3/181 ,  H05K3/188 ,  H05K3/42 ,  H05K3/422 ,  H05K3/424 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/4623 ,  H05K3/4638 ,  H05K2201/095 ,  H05K2201/09545 ,  H05K2201/09554 ,  H05K2201/10303

Abstract: A selective segment via plating process for manufacturing a circuit board selectively interconnects inner conductive layers as separate segments within the same via. Plating resist is plugged into an inner core through hole and then stripped off after an electroless plating process. Stripping of the electroless plating on the plating resist results in a plating discontinuity on the via wall. In a subsequent electroplating process, the inner core layer can not be plated due to the plating discontinuity. The resulting circuit board structure has separate electrically interconnected segments within the via.

公开(公告)号：US20160324002A1

公开(公告)日：2016-11-03

申请号：US15105723

申请日：2014-10-14

Applicant: Auto-Kabel Management GmbH

Inventor： Wacim TAZARINE ,  Simon BETSCHER ,  Frank GRONWALD

IPC: H05K1/14 ,  H05K1/11 ,  H05K3/36 ,  H05K1/18

CPC classification number: H05K1/145 ,  C23C14/042 ,  H01L23/142 ,  H01L23/367 ,  H01L23/3677 ,  H01L2924/0002 ,  H05K1/0206 ,  H05K1/0209 ,  H05K1/056 ,  H05K1/111 ,  H05K1/117 ,  H05K1/142 ,  H05K1/181 ,  H05K1/182 ,  H05K3/28 ,  H05K3/282 ,  H05K3/368 ,  H05K2201/09372 ,  H05K2201/09554 ,  H05K2201/10166 ,  H05K2201/10689 ,  H05K2203/1377 ,  H01L2924/00

Abstract: Circuit having a first printed circuit board and a second printed circuit board. In the circuit, the printed circuit boards spaced apart from one another by means of an air gap are mechanically connected together by at least one power semiconductor.

Abstract translation: 具有第一印刷电路板和第二印刷电路板的电路。 在电路中，通过气隙彼此间隔开的印刷电路板通过至少一个功率半导体机械连接在一起。

公开(公告)号：US09107314B2

公开(公告)日：2015-08-11

申请号：US13799221

申请日：2013-03-13

Applicant: FUJITSU LIMITED

Inventor： Hideaki Yoshimura

IPC: H01K3/10 ,  H05K1/11 ,  H05K3/40 ,  H05K3/44 ,  H05K3/46 ,  G01R31/28 ,  H05K3/42

CPC classification number: H05K1/115 ,  G01R31/2889 ,  H05K1/0298 ,  H05K1/0366 ,  H05K3/4038 ,  H05K3/425 ,  H05K3/445 ,  H05K3/4608 ,  H05K2201/0323 ,  H05K2201/09545 ,  H05K2201/09554 ,  H05K2201/0959 ,  Y10T29/49165

Abstract: A method of manufacturing a wiring board includes: forming an outer through hole in a core substrate; filling the outer through hole with an insulation resin; forming a first conductive layer on a surface of the insulation resin at a portion where a core connecting via is formed; forming a land around the first conductive layer; laminating the wiring layer on the core substrate after the forming of the first conductive layer and the forming of the land; forming an inner through hole having a smaller diameter than that of the outer through hole and penetrating through the core substrate and the wiring layer so as to penetrate through the insulation resin; and coating a first conductive film on an inner wall surface of the inner through hole, in which the core substrate and the first conductive film are electrically connected through the first conductive layer and the land.

Abstract translation: 制造布线板的方法包括：在芯基板中形成外通孔; 用绝缘树脂填充外部通孔; 在形成芯连接通孔的部分上在绝缘树脂的表面上形成第一导电层; 形成围绕所述第一导电层的区域; 在形成第一导电层并形成焊盘之后，在芯基板上层叠布线层; 形成直径小于所述外通孔直径的内通孔，穿过所述芯基板和所述布线层以贯穿所述绝缘树脂; 并且在内部通孔的内壁表面上涂覆第一导电膜，其中芯基板和第一导电膜通过第一导电层和焊盘电连接。

公开(公告)号：US08598467B2

公开(公告)日：2013-12-03

申请号：US13275808

申请日：2011-10-18

Applicant: Kevin C. Olson ,  Alan G. Wang

Inventor： Kevin C. Olson ,  Alan G. Wang

IPC: H05K1/11

CPC classification number: H01L21/486 ,  C09D5/4488 ,  H01L21/481 ,  H01L21/4857 ,  H01L23/142 ,  H01L23/49827 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K1/056 ,  H05K3/0023 ,  H05K3/0032 ,  H05K3/0035 ,  H05K3/388 ,  H05K3/426 ,  H05K3/44 ,  H05K3/445 ,  H05K3/4608 ,  H05K2201/0179 ,  H05K2201/09554 ,  H05K2201/09609 ,  H05K2203/0582 ,  H05K2203/135 ,  H01L2924/00

Abstract: A process for fabricating a multi-layer circuit assembly is provided. The process includes (a) providing a substrate at least one area of which comprises a plurality of vias area(s) having a via density of 500 to 10,000 holes/square inch (75 to 1550 holes/square centimeter); (b) applying a dielectric coating onto all exposed surfaces of the substrate to form a conformal coating thereon; (c) removing the dielectric coating in a predetermined pattern to expose sections of the substrate; (d) applying a layer of metal to all surfaces to form metallized vias through and/or to the electrically conductive core; (e) applying a resist to the metal layer to form a photosensitive layer thereon; (f) imaging resist in predetermined locations; (g) developing resist to uncover selected areas of the metal layer; and (h) etching uncovered areas of metal to form an electrical circuit pattern connected by the metallized vias.

Abstract translation: 提供了一种用于制造多层电路组件的工艺。 该方法包括（a）提供基底，其至少一个区域包括通孔密度为500至10,000个孔/平方英寸（75至1550个孔/平方厘米）的多个通孔区域; （b）将介电涂层施加到所述基底的所有暴露表面上以在其上形成保形涂层; （c）以预定图案去除所述电介质涂层以暴露所述基板的部分; （d）将金属层施加到所有表面以形成通过和/或导电芯的金属化通孔; （e）在所述金属层上施加抗蚀剂以在其上形成感光层; （f）在预定位置的成像抗蚀剂; （g）显影抗蚀剂以露出金属层的选定区域; 和（h）蚀刻金属的未覆盖区域以形成通过金属化通孔连接的电路图案。

公开(公告)号：US08553364B1

公开(公告)日：2013-10-08

申请号：US12623983

申请日：2009-11-23

Applicant: Christopher Schreiber ,  Christopher Gene Dunn

Inventor： Christopher Schreiber ,  Christopher Gene Dunn

IPC: G11B5/48

CPC classification number: G11B5/48 ,  B33Y80/00 ,  G11B5/486 ,  H05K1/0215 ,  H05K1/0228 ,  H05K1/056 ,  H05K3/388 ,  H05K3/44 ,  H05K3/4685 ,  H05K2201/0347 ,  H05K2201/09554 ,  H05K2201/09827

Abstract: A low impedance, low crosstalk disk drive suspension circuit has multiple traces carrying a first polarity of a differential signal, interleaved with multiple traces carrying the second polarity of a differential signal. Each pair of conductors consisting of a trace of the first polarity and a trace of the second polarity may cross over each other at multiple crossover points. The crossover connections may utilize a second layer of copper trace conductors over the first and main layer, or alternatively the crossover connections may utilize an isolated portion of the suspension substrate.

公开(公告)号：US08399774B2

公开(公告)日：2013-03-19

申请号：US13303769

申请日：2011-11-23

Applicant: Yoichi Hitomi ,  Hiroaki Miyazawa ,  Shinji Kumon ,  Terutoshi Momose

Inventor： Yoichi Hitomi ,  Hiroaki Miyazawa ,  Shinji Kumon ,  Terutoshi Momose

IPC: H05K1/00 ,  H05K1/02

CPC classification number: G06F1/182 ,  G11B5/40 ,  G11B5/484 ,  G11B5/4853 ,  H05K1/0215 ,  H05K1/056 ,  H05K1/116 ,  H05K3/44 ,  H05K2201/09463 ,  H05K2201/09554

Abstract: A substrate for suspension comprises a metallic substrate, an insulating layer formed on the metallic substrate, having an opening for grounding terminal, and a grounding conductor formed on the insulating layer. A grounding-terminal-forming material is placed in the opening for grounding terminal to form a grounding terminal that connects the metallic substrate and the grounding conductor. The grounding conductor does not surround a portion of the circumference of the opening for grounding terminal.

Abstract translation: 悬浮基板包括金属基板，形成在金属基板上的绝缘层，具有用于接地端子的开口和形成在绝缘层上的接地导体。 接地端子形成材料放置在接地端子的开口中，形成连接金属基板和接地导体的接地端子。 接地导体不包围用于接地端子的开口的圆周的一部分。

公开(公告)号：US08247700B2

公开(公告)日：2012-08-21

申请号：US12382266

申请日：2009-03-12

Applicant: Jun Ishii ,  Yasunari Ooyabu ,  Visit Thaveeprungsriporn

Inventor： Jun Ishii ,  Yasunari Ooyabu ,  Visit Thaveeprungsriporn

IPC: H05K1/00

CPC classification number: H05K1/0259 ,  G11B5/484 ,  G11B5/486 ,  H05K1/056 ,  H05K1/167 ,  H05K2201/09554 ,  Y10T428/1328 ,  Y10T428/1393 ,  Y10T428/256 ,  Y10T428/257

Abstract: A wired circuit board has a metal supporting board, an insulating layer formed on the metal supporting board, a conductive pattern formed on the insulating layer and having a pair of wires arranged in spaced-apart relation, and a semiconductive layer formed on the insulating layer and electrically connected to the metal supporting board and the conductive pattern. The conductive pattern has a first region in which a distance between the pair of wires is small and a second region in which the distance between the pair of wires is larger than that in the first region. The semiconductive layer is provided in the second region.

Abstract translation: 布线电路板具有金属支撑板，形成在金属支撑板上的绝缘层，形成在绝缘层上并具有间隔布置的一对电线的导电图案，以及形成在绝缘层上的半导体层 并且电连接到金属支撑板和导电图案。 导电图案具有第一区域，其中一对导线之间的距离小，并且一对导线之间的距离大于第一区域中的距离的第二区域。 半导体层设置在第二区域中。

公开(公告)号：US08115108B2

公开(公告)日：2012-02-14

申请号：US12291892

申请日：2008-11-14

Applicant: Nobuyuki Sakai

Inventor： Nobuyuki Sakai

IPC: H05K1/11

CPC classification number: H05K3/0061 ,  H05K1/0393 ,  H05K1/056 ,  H05K3/005 ,  H05K3/321 ,  H05K3/4069 ,  H05K3/4084 ,  H05K3/44 ,  H05K2201/091 ,  H05K2201/09554 ,  H05K2203/063 ,  Y10T29/49153 ,  Y10T29/49155 ,  Y10T29/49156

Abstract: The insulation base side of single-sided FPC is turned to the die side, and the mounting surface side of ground circuit is turned to the upper side, and the FPC is placed on die (a). When the portion of ground circuit where the conduction is realized and metal reinforcing plate are punched by punch of which the clearance dimension is made to be 50 to 95% of the thickness of the material to be punched, hole sagging will be formed (b). The insulation base 1 side is turned up, electrically conductive adhesive and metal reinforcing plate are laminated in this order, heating pressing is performed with the press apparatus for metal reinforcing plate to be laminated (c). Thereby, laminated FPC is formed (d). At this time, since electrically conductive adhesive is injected into hole sagging by press pressing, the electrical connection of metal reinforcing plate and ground circuit can be attained by the interlaminar conduction by means of electrically conductive adhesive, and there is also no residual air.

Abstract translation: 单面FPC的绝缘基底侧向模具侧转动，接地电路的安装面侧向上侧转动，将FPC放置在模具（a）上。 当实现导通的接地电路的部分和金属加强板用冲孔冲压成冲孔材料厚度的50％至95％时，将形成孔下垂（b） 。 将绝缘基体1侧翻转，依次层压导电性粘合剂和金属加强板，用层叠（c）的金属加强板用加压装置进行加压加压。 由此形成层叠FPC（d）。 此时，由于通过压制将导电性粘合剂注入到孔下垂中，所以可以通过导电性粘合剂进行层间导电，可以实现金属加强板与接地电路的电连接，也不会有残留空气。

公开(公告)号：US08018047B2

公开(公告)日：2011-09-13

申请号：US12624622

申请日：2009-11-24

Applicant: Reinhold Bayerer ,  Thomas Hunger

Inventor： Reinhold Bayerer ,  Thomas Hunger

IPC: H01L23/053 ,  H01L23/12 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L23/3735 ,  H01L23/3731 ,  H01L23/3736 ,  H01L24/29 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L25/072 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/29339 ,  H01L2224/32225 ,  H01L2224/45014 ,  H01L2224/45124 ,  H01L2224/45147 ,  H01L2224/4809 ,  H01L2224/48091 ,  H01L2224/4813 ,  H01L2224/48227 ,  H01L2224/4846 ,  H01L2224/48472 ,  H01L2224/48699 ,  H01L2224/49 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2224/83825 ,  H01L2224/8384 ,  H01L2224/83851 ,  H01L2224/85205 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0781 ,  H01L2924/1301 ,  H01L2924/13055 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/3011 ,  H05K1/0206 ,  H05K1/0207 ,  H05K1/0256 ,  H05K1/0306 ,  H05K1/053 ,  H05K3/4046 ,  H05K3/4061 ,  H05K3/44 ,  H05K3/462 ,  H05K3/4629 ,  H05K3/4641 ,  H05K2201/0355 ,  H05K2201/0379 ,  H05K2201/09145 ,  H05K2201/09554 ,  H05K2201/09845 ,  H05K2201/10234 ,  H01L2224/8382 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/013 ,  H01L2924/00013 ,  H01L2224/83205 ,  H01L2224/85399 ,  H01L2224/05599

Abstract: A semiconductor module includes a multilayer substrate. The multilayer substrate includes a first metal layer and a first ceramic layer over the first metal layer. An edge of the first ceramic layer extends beyond an edge of the first metal layer. The multilayer substrate includes a second metal layer over the first ceramic layer and a second ceramic layer over the second metal layer. An edge of the second ceramic layer extends beyond an edge of the second metal layer. The multilayer substrate includes a third metal layer over the second ceramic layer.

Abstract translation: 半导体模块包括多层基板。 多层基板包括第一金属层和第一金属层上的第一陶瓷层。 第一陶瓷层的边缘延伸超过第一金属层的边缘。 多层基板包括在第一陶瓷层之上的第二金属层和在第二金属层上的第二陶瓷层。 第二陶瓷层的边缘延伸超过第二金属层的边缘。 多层基板包括在第二陶瓷层上的第三金属层。

公开(公告)号：US20100218891A1

公开(公告)日：2010-09-02

申请号：US12776771

申请日：2010-05-10

Applicant: Frank D. Egitto ,  Donald S. Farquhar ,  Voya R. Markovich ,  Mark D. Poliks ,  Douglas O. Powell

Inventor： Frank D. Egitto ,  Donald S. Farquhar ,  Voya R. Markovich ,  Mark D. Poliks ,  Douglas O. Powell

IPC: C09J5/06

CPC classification number: H01L21/4853 ,  H01L23/3735 ,  H01L23/49822 ,  H01L2224/16225 ,  H01L2924/01004 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01068 ,  H01L2924/01078 ,  H01L2924/01322 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/114 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/4608 ,  H05K3/462 ,  H05K3/4623 ,  H05K3/4626 ,  H05K3/4632 ,  H05K3/4641 ,  H05K3/4688 ,  H05K2201/0141 ,  H05K2201/0191 ,  H05K2201/068 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/09554 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2201/10378 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T156/1092

Abstract: A multi-layered interconnect structure and method of formation. In a first embodiment, first and second liquid crystal polymer (LCP) dielectric layers are directly bonded, respectively, to first and second opposing surface of a thermally conductive layer, with no extrinsic adhesive material bonding the thermally conductive layer with either the first or second LCP dielectric layer. In a second embodiment, first and second 2S1P substructures are directly bonded, respectively, to first and second opposing surfaces of a LCP dielectric joining layer, with no extrinsic adhesive material bonding the LCP dielectric joining layer with either the first or second 2S1P substructures.

Abstract translation: 多层互连结构和形成方法。 在第一实施例中，第一和第二液晶聚合物（LCP）电介质层分别直接接合到导热层的第一和第二相对表面，没有外在粘合材料将导热层与第一或第二液晶聚合物 LCP电介质层。 在第二实施例中，第一和第二2S1P子结构分别直接接合到LCP电介质接合层的第一和第二相对表面，没有外部粘合材料将LCP电介质接合层与第一或第二2S1P子结构结合。