公开(公告)号：US20140191396A1

公开(公告)日：2014-07-10

申请号：US14205880

申请日：2014-03-12

Applicant: MEDIA TEK INC.

Inventor： Tzu-Hung LIN ,  Wen-Sung HSU ,  Ta-Jen YU ,  Andrew C. CHANG

IPC: H01L23/00

CPC classification number: H01L24/13 ,  H01L21/48 ,  H01L23/49541 ,  H01L23/498 ,  H01L23/49811 ,  H01L23/49827 ,  H01L24/05 ,  H01L24/11 ,  H01L24/14 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L28/00 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05073 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05562 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/11462 ,  H01L2224/11849 ,  H01L2224/13026 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/3224 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2924/12042 ,  H05K1/111 ,  H05K3/3436 ,  H05K2201/0376 ,  H05K2201/09472 ,  H05K2201/10674 ,  Y02P70/611 ,  H01L2924/014 ,  H01L2224/05552 ,  H01L2924/00

Abstract: In one configuration, a semiconductor package includes a conductive trace embedded in a base and a semiconductor device mounted on the conductive trace via a conductive structure, wherein the conductive structure is a bump structure and the width of the bump structure is bigger than the width of the conductive trace. In another configuration, a method for fabricating a semiconductor package includes providing a base, forming at least one conductive trace on the base, forming an additional insulation material on the base, and defining patterns upon the additional insulation material, wherein the pattern is formed on at least one conductive trace, wherein the conductive structure is a bump structure and the width of the bump structure is bigger than the width of the conductive trace.

Abstract translation: 在一种配置中，半导体封装包括嵌入在基底中的导电迹线和通过导电结构安装在导电迹线上的半导体器件，其中导电结构是凸块结构，并且凸块结构的宽度大于 导电迹线。 在另一种结构中，制造半导体封装的方法包括提供基底，在基底上形成至少一个导电迹线，在基底上形成额外的绝缘材料，并在附加绝缘材料上限定图案，其中图案形成在 至少一个导电迹线，其中所述导电结构是凸块结构，并且所述凸块结构的宽度大于所述导电迹线的宽度。

公开(公告)号：US20140157593A1

公开(公告)日：2014-06-12

申请号：US13753625

申请日：2013-01-30

Applicant: BRIDGE SEMICONDUCTOR CORPORATION

Inventor： Charles W.C. LIN ,  Chia Chung WANG

IPC: H05K3/30

CPC classification number: H05K3/30 ,  H01L24/19 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/45144 ,  H01L2224/73259 ,  H01L2224/8314 ,  H01L2224/92144 ,  H01L2924/12042 ,  H05K1/183 ,  H05K3/4644 ,  H05K2201/09781 ,  H05K2201/10378 ,  H05K2201/10674 ,  H05K2201/2009 ,  H05K2203/1469 ,  H05K2203/167 ,  Y10T29/4913 ,  H01L2924/00

Abstract: The present invention relates to a method of making a hybrid wiring board with built-in stopper and interposer. In accordance with one preferred embodiment of the present invention, the method includes: forming a stopper on a dielectric layer; mounting an interposer on the dielectric layer using the stopper as a placement guide for the interposer; attaching a stiffener to the dielectric layer; and forming a build-up circuitry that covers the interposer, the stopper and the stiffener and provides signal routing for the interposer. Accordingly, the stopper can accurately confine the placement location of the interposer and avoid the electrical connection failure between the interposer and the build-up circuitry.

Abstract translation: 本发明涉及一种制造具有内置止动器和插入件的混合布线板的方法。 根据本发明的一个优选实施例，该方法包括：在电介质层上形成一个塞子; 使用所述塞子将所述介电层安装在所述介电层上作为所述插入件的放置引导件; 将加强件附接到介电层; 以及形成覆盖插入件，止动器和加强件并且为插入件提供信号路由的积聚电路。 因此，止动器可以精确地限制插入器的放置位置，并避免插入器和积聚电路之间的电连接故障。

公开(公告)号：US20140140031A1

公开(公告)日：2014-05-22

申请号：US14131847

申请日：2012-12-06

Applicant: Panasonic Corporation

Inventor： Suguru Fujita ,  Ryosuke Shiozaki ,  Toshiaki Nakamura ,  Jun'ichi Kimura

IPC: H05K1/18

CPC classification number: H05K1/18 ,  H01L23/13 ,  H01L23/49816 ,  H01L23/49833 ,  H01L2224/16235 ,  H01L2224/16238 ,  H01L2924/15153 ,  H01L2924/15321 ,  H01L2924/3511 ,  H01Q1/2283 ,  H01Q9/0407 ,  H01Q21/065 ,  H05K1/144 ,  H05K1/186 ,  H05K2201/042 ,  H05K2201/10098 ,  H05K2201/10234 ,  H05K2201/10674

Abstract: A wireless module, in which a first board (11) and a second board (12) are laminated, includes connecting members (18) which are connected to at least one of the first board (11) and the second board (12), and form a gap allowing mounting of mounting components including a semiconductor device (14) between the first board (11) and the second board (12). The connecting members (18) are arranged such that a plurality of connecting members (18A, 18B) are arranged uniformly in a planar direction of the boards of the wireless module.

Abstract translation: 其中层叠有第一板（11）和第二板（12）的无线模块包括连接到第一板（11）和第二板（12）中的至少一个的连接构件（18） 并且形成允许在第一板（11）和第二板（12）之间安装包括半导体器件（14）的安装部件的间隙。 连接构件（18）被布置成使得多个连接构件（18A，18B）在无线模块的板的平面方向上均匀地布置。

公开(公告)号：US20140138823A1

公开(公告)日：2014-05-22

申请号：US13683315

申请日：2012-11-21

Applicant: NVIDIA CORPORATION

Inventor： Leilei ZHANG ,  Zuhair BOKHAREY

IPC: H01L23/00

CPC classification number: H01L24/17 ,  H01L21/563 ,  H01L22/12 ,  H01L22/20 ,  H01L23/49811 ,  H01L23/49816 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/131 ,  H01L2224/1403 ,  H01L2224/16225 ,  H01L2224/1703 ,  H01L2224/73204 ,  H01L2224/81048 ,  H01L2224/81815 ,  H01L2224/831 ,  H01L2924/07802 ,  H01L2924/15311 ,  H01L2924/3511 ,  H05K3/3436 ,  H05K2201/10674 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/00

Abstract: One embodiment of the present invention sets forth an integrated circuit package including a substrate, an integrated circuit die, a first plurality of solder bump structures, and a first plurality of variable-size solder bump structures. The first plurality of solder bump structures electrically couple the integrated circuit die to the substrate. The first plurality of variable-size solder bump structures are disposed on a bottom surface of the substrate. The first plurality of variable-size solder bump structures are sized to be substantially coplanar with a seating plane of the integrated circuit package.

Abstract translation: 本发明的一个实施例提出了一种集成电路封装，其包括基板，集成电路管芯，第一多个焊料凸点结构以及第一多个可变大小的焊料凸点结构。 第一多个焊料凸块结构将集成电路管芯电耦合到衬底。 第一多个可变尺寸的焊料凸块结构设置在基板的底表面上。 第一多个可变尺寸的焊料凸块结构的尺寸设计成与集成电路封装的就座平面基本共面。

公开(公告)号：US08722536B2

公开(公告)日：2014-05-13

申请号：US13959003

申请日：2013-08-05

Applicant: International Business Machines Corporation

Inventor： Daniel Douriet ,  Francesco Preda ,  Brian L. Singletary ,  Lloyd A. Walls

IPC: H01L21/44

CPC classification number: H01L21/768 ,  H01L23/49827 ,  H01L23/50 ,  H01L24/16 ,  H01L2224/16 ,  H01L2924/01078 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19105 ,  H05K1/0231 ,  H05K1/0263 ,  H05K1/113 ,  H05K3/429 ,  H05K2201/09309 ,  H05K2201/09509 ,  H05K2201/09718 ,  H05K2201/10674 ,  Y10T29/49165

Abstract: A circuit substrate uses post-fed top side power supply connections to provide improved routing flexibility and lower power supply voltage drop/power loss. Plated-through holes are used near the outside edges of the substrate to provide power supply connections to the top metal layers of the substrate adjacent to the die, which act as power supply planes. Pins are inserted through the plated-through holes to further lower the resistance of the power supply path(s). The bottom ends of the pins may extend past the bottom of the substrate to provide solderable interconnects for the power supply connections, or the bottom ends of the pins may be soldered to “jog” circuit patterns on a bottom metal layer of the substrate which connect the pins to one or more power supply terminals of an integrated circuit package including the substrate.

Abstract translation: 电路基板使用后馈电顶部电源连接来提供改进的布线灵活性和较低的电源电压降/功率损耗。 在基板的外边缘附近使用电镀通孔，以提供与作为电源平面的管芯相邻的基板的顶部金属层的电源连接。 引脚插入通过电镀通孔以进一步降低电源路径的电阻。 引脚的底端可以延伸越过基板的底部以提供用于电源连接的可焊接互连，或者引脚的底端可以被焊接到基板的底部金属层上的“点动”电路图案，其连接 引脚连接到包括基板的集成电路封装的一个或多个电源端子。

公开(公告)号：US20140126166A1

公开(公告)日：2014-05-08

申请号：US13730408

申请日：2012-12-28

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Su Il Kim ,  Soon Jin Cho

IPC: H05K13/00 ,  H05K1/18

CPC classification number: H05K1/18 ,  H01L2224/45139 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2924/1461 ,  H01L2924/3025 ,  H05K3/303 ,  H05K2201/09909 ,  H05K2201/10674 ,  H05K2201/2036 ,  H05K2203/049 ,  Y02P70/613 ,  H01L2924/00014 ,  H01L2924/00

Abstract: Disclosed herein is a method of forming a solder resist (SR) post, including: (A) forming an SR layer on a printed circuit board; (B) disposing a patterning film on an upper surface on the SR layer; (C) forming a plurality of openings in the patterning film or the SR layer; (D) filling SR ink in the openings and performing an exposure process to form a plurality of SR posts; (E) delaminating the patterning film; (F) removing an uncured portion of the SR ink on which the exposure process is performed; and (G) drying the plurality of SR posts.

Abstract translation: 本文公开了一种形成阻焊剂（SR）柱的方法，包括：（A）在印刷电路板上形成SR层; （B）在SR层的上表面上配置图案化膜; （C）在图案化膜或SR层中形成多个开口; （D）在开口中填充SR墨水并执行曝光处理以形成多个SR柱; （E）分层图形膜; （F）去除进行曝光处理的SR墨水的未固化部分; 和（G）干燥多个SR柱。

公开(公告)号：US08716036B2

公开(公告)日：2014-05-06

申请号：US13730047

申请日：2012-12-28

Applicant: 3D Plus

Inventor： Christian Val

IPC: H01L21/00

CPC classification number: H01L22/14 ,  H01L21/561 ,  H01L21/568 ,  H01L23/50 ,  H01L24/24 ,  H01L24/82 ,  H01L24/83 ,  H01L24/92 ,  H01L24/96 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/05548 ,  H01L2224/24011 ,  H01L2224/24105 ,  H01L2224/24137 ,  H01L2224/24141 ,  H01L2224/24227 ,  H01L2224/73267 ,  H01L2224/8385 ,  H01L2224/9202 ,  H01L2224/92144 ,  H01L2224/96 ,  H01L2225/1035 ,  H01L2225/1064 ,  H01L2924/18162 ,  H05K1/185 ,  H05K3/0052 ,  H05K3/007 ,  H05K3/0097 ,  H05K3/225 ,  H05K3/4688 ,  H05K2201/09981 ,  H05K2201/10674 ,  H05K2203/1327 ,  H01L2224/83 ,  H01L2924/00014

Abstract: A method for collective fabrication of 3D electronic modules comprises: the fabrication of a stack of reconstructed wafers, comprising validated active components, this stack including a redistribution layer; the fabrication of a panel of validated passive printed circuits which comprises: fabrication of a panel of printed circuits, electrical testing of each printed circuit, fitting of the validated printed circuits to an adhesive substrate, molding of the mounted circuits in an electrically insulating resin, called coating resin and polymerization of the resin, removal of the adhesive substrate, a panel comprising only validated printed circuits being thus obtained; bonding the panel with a stack (of reconstructed wafers); cutting the “stack of panel” assembly for the purpose of obtaining the 3D electronic modules.

Abstract translation: 一种用于3D电子模块的集体制造的方法包括：制造重叠的晶片堆叠，其包括验证的有源元件，该叠层包括再分布层; 制造经验证的无源印刷电路板，其包括：制造印刷电路板，每个印刷电路的电气测试，将经验证的印刷电路装配到粘合剂基板上，将电路中的安装电路模制成电绝缘树脂， 所谓的涂布树脂和树脂的聚合，去除粘合剂基材，仅由验证的印刷电路构成的面板被获得; 用叠层（重构晶片）粘合面板; 为了获得3D电子模块，切割“堆叠”面板组件。

公开(公告)号：US08692132B2

公开(公告)日：2014-04-08

申请号：US13242488

申请日：2011-09-23

Applicant: Sotaro Ito ,  Michimasa Takahashi ,  Yukinobu Mikado

Inventor： Sotaro Ito ,  Michimasa Takahashi ,  Yukinobu Mikado

IPC: H05K1/16

CPC classification number: H01L24/83 ,  H01L23/5385 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/24 ,  H01L24/32 ,  H01L25/105 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/20 ,  H01L2224/24227 ,  H01L2224/29109 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/8385 ,  H01L2224/92 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/0133 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/15788 ,  H01L2924/1579 ,  H01L2924/351 ,  H05K1/185 ,  H05K3/0035 ,  H05K3/4652 ,  H05K2201/096 ,  H05K2201/10477 ,  H05K2201/10674 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49139 ,  Y10T29/49146 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T29/49167 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2924/01049 ,  H01L2924/01083 ,  H01L2924/3512 ,  H01L2924/00014 ,  H01L2224/13111 ,  H01L2224/13109

Abstract: A method for manufacturing a multilayered printed circuit board including forming a first insulating resin substrate having a metal layer substantially corresponding to dimensions of a semiconductor device, forming a second insulating resin substrate, forming a recess extending to the metal layer of the first insulating resin substrate such that a surface of the metal layer is exposed, accommodating the semiconductor device in the recess such that the semiconductor device is mounted on the surface of the metal layer, and forming a resin insulating layer on the first insulating resin substrate such that the semiconductor device accommodated in the recess is covered.

Abstract translation: 一种多层印刷电路板的制造方法，其特征在于，包括形成具有与半导体装置的尺寸基本对应的金属层的第一绝缘性树脂基板，形成第二绝缘树脂基板，形成延伸到第一绝缘树脂基板的金属层的凹部 使得金属层的表面露出，将半导体器件容纳在凹部中，使得半导体器件安装在金属层的表面上，并且在第一绝缘树脂基板上形成树脂绝缘层，使得半导体器件 容纳在凹处被覆盖。

公开(公告)号：US08692129B2

公开(公告)日：2014-04-08

申请号：US13429764

申请日：2012-03-26

Applicant: Toshiaki Kasai ,  Takema Adachi

Inventor： Toshiaki Kasai ,  Takema Adachi

IPC: H05K1/03 ,  H05K1/11 ,  H05K7/00 ,  H05K3/00 ,  H05K3/10

CPC classification number: H05K3/3452 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/16 ,  H01L24/81 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/81192 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15331 ,  H05K3/4602 ,  H05K2201/0367 ,  H05K2201/094 ,  H05K2201/10515 ,  H05K2201/10674 ,  H05K2203/0588 ,  Y10T29/49124 ,  Y10T29/49155 ,  H01L2924/00

Abstract: A printed wiring board includes an interlayer insulation layer, first pads positioned to mount a semiconductor element and forming a first pad group on the insulation layer, second pads forming a second pad group on the insulation layer and positioned along a peripheral portion of the first group, a first solder-resist layer formed on the insulation layer and having first openings exposing the first pads, respectively, and second openings exposing the second pads, respectively, conductive posts formed on the second pads through the second openings of the first solder-resist layer, respectively, and a second solder-resist layer formed on the first solder-resist layer and having a third opening exposing the first pads and fourth openings exposing surfaces of the posts, respectively. The second openings have a diameter greater than a diameter of the posts, and the second solder-resist layer is filling gaps formed between the second openings and the posts.

Abstract translation: 印刷电路板包括层间绝缘层，第一焊盘被定位成安装半导体元件并在绝缘层上形成第一焊盘组，第二焊盘在绝缘层上形成第二焊盘组并且沿着第一组的周边部分定位 分别形成在所述绝缘层上并具有分别暴露所述第一焊盘的第一开口的第一阻焊层和分别暴露所述第二焊盘的所述第二焊盘的第二焊盘的形成在所述第二焊盘上的导电柱穿过所述第一阻焊层的所述第二开口 以及形成在第一阻焊层上的第二阻焊层，并且具有第三开口，第三开口分别暴露第一焊盘和暴露焊盘表面的第四开口。 第二开口具有大于柱的直径的直径，并且第二阻焊层填充形成在第二开口和柱之间的间隙。

公开(公告)号：US20140090877A1

公开(公告)日：2014-04-03

申请号：US14041743

申请日：2013-09-30

Applicant: IBIDEN CO., LTD.

Inventor： Fumitaka TAKAGI ,  Nobuhisa Kuroda ,  Mariko Kimura

IPC: H05K1/18 ,  H05K3/02

CPC classification number: H05K1/183 ,  H01L23/49827 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/83385 ,  H01L2224/83411 ,  H01L2224/83444 ,  H01L2224/83455 ,  H01L2224/83464 ,  H01L2224/92125 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15331 ,  H05K1/181 ,  H05K3/02 ,  H05K3/3436 ,  H05K3/3452 ,  H05K2201/09845 ,  H05K2201/10515 ,  H05K2201/10674 ,  Y02P70/611 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A printed wiring board includes an interlayer resin insulation layer, a pad structure formed on the interlayer resin insulation layer and positioned to mount a semiconductor device, and a solder-resist layer formed on the interlayer resin insulation layer and having an opening portion exposing a portion of the pad structure from the solder-resist layer. The opening portion of the solder-resist layer has a bottom surface such that the bottom surface of the opening portion is exposing an upper surface and a portion of a side surface of the pad structure.

Abstract translation: 印刷布线板包括层间树脂绝缘层，形成在层间树脂绝缘层上并定位成安装半导体器件的焊盘结构，以及形成在层间树脂绝缘层上的阻焊层，并且具有露出部分 的焊料结构。 阻焊层的开口部分具有底表面，使得开口部分的底表面暴露焊盘结构的上表面和侧表面的一部分。