公开(公告)号：US20120175156A1

公开(公告)日：2012-07-12

申请号：US13088297

申请日：2011-04-15

Applicant: CHANG-XIN HUANG

Inventor： CHANG-XIN HUANG

IPC: H05K1/09 ,  H05K1/02

CPC classification number: H05K3/22 ,  H05K1/0292 ,  H05K3/3452 ,  H05K2201/0305 ,  H05K2201/0989 ,  H05K2203/173

Abstract: A printed circuit board includes a substrate, a plurality of metal wires, and a solder mask layer. The substrate includes a first area and a second area. The second area surrounds and does not overlap the first area. The metal wires are disposed on the first area of the substrate. One end of one of two adjacent metal wires faces one end of the other one of the two adjacent metal wires. The solder mask layer is formed on the second area of the substrate. In the present invention, a short circuit or an open circuit between the two adjacent metal wires is directly formed during processes of manufacturing the printed circuit board, whereby a jumper is not required so as to reduce a layout area, and cost of a manual post-welding treatment can be reduced.

Abstract translation: 印刷电路板包括基板，多个金属线和焊接掩模层。 基板包括第一区域和第二区域。 第二区域围绕并且不与第一区域重叠。 金属线设置在基板的第一区域上。 两个相邻的金属线中的一个的一端面对两个相邻金属线中另一个的一端。 焊料掩模层形成在衬底的第二区域上。 在本发明中，在制造印刷电路板的过程中直接形成两个相邻的金属线之间的短路或开路，由此不需要跳线以减少布局面积和手动柱的成本 可以减少焊接处理。

公开(公告)号：US20120168208A1

公开(公告)日：2012-07-05

申请号：US12981865

申请日：2010-12-30

Applicant: WAYNE A. SOZANSKY ,  SHING YEH

Inventor： WAYNE A. SOZANSKY ,  SHING YEH

IPC: H05K1/02 ,  B23K1/20

CPC classification number: H05K3/3421 ,  H05K2201/0305 ,  H05K2201/09781 ,  H05K2201/10689 ,  H05K2201/2036 ,  H05K2203/0278 ,  Y02P70/613

Abstract: A system and method for supporting an electronic component attached to a circuit board. Solder paste is applied to a solder pad underneath and aligned with a non-wetting region of an electronic component to form a support formed of solder to prevent electronic component lead flexing. The amount of solder for forming the support and the size of the solder pad are selected to bring the support into contact with, or in close proximity to, the non-wetting region.

Abstract translation: 一种用于支撑附接到电路板的电子部件的系统和方法。 将焊膏施加到下面的焊盘并与电子部件的非润湿区域对准以形成由焊料形成的支撑件，以防止电子部件引线弯曲。 选择用于形成载体的焊料的量和焊盘的尺寸以使支撑体与非润湿区域接触或非常接近。

公开(公告)号：US08138608B2

公开(公告)日：2012-03-20

申请号：US12691255

申请日：2010-01-21

Applicant: Chonghua Zhong

Inventor： Chonghua Zhong

IPC: H01L23/48 ,  H01L23/52

CPC classification number: H01L23/5382 ,  H01L24/16 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2924/01013 ,  H01L2924/01028 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K1/0293 ,  H05K3/321 ,  H05K3/3452 ,  H05K2201/0305 ,  H05K2201/09381 ,  H05K2201/09809 ,  H05K2201/0989 ,  H05K2201/10674 ,  H05K2203/173 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: Methods, systems, and apparatuses for integrated circuit package substrates, integrated circuit packages, and processes for assembling the same, are provided. A substrate for a flip chip integrated circuit package includes a substrate body having opposing first and second surfaces. A solder mask layer covers at least a portion of the first surface of the substrate body. First and second electrically conductive features are formed on the substrate body. The first electrically conductive feature is a portion of a first electrical signal net, and the second electrically conductive feature is a portion of a second electrical signal net. The first and second electrically conductive features are configured to be selectively electrically coupled together by application of an electrically conductive material. The electrically conductive material may be a conductive epoxy, a jumper, a solder paste, a solder ball, or a solder bump that couples a flip chip die to the substrate.

Abstract translation: 提供了用于集成电路封装基板，集成电路封装以及用于组装其的工艺的方法，系统和装置。 用于倒装芯片集成电路封装的衬底包括具有相对的第一和第二表面的衬底本体。 焊接掩模层覆盖基板主体的第一表面的至少一部分。 第一和第二导电特征形成在衬底主体上。 第一导电特征是第一电信号网的一部分，第二导电特征是第二电信号网的一部分。 第一和第二导电特征被配置为通过施加导电材料选择性地电耦合在一起。 导电材料可以是导电环氧树脂，跳线，焊膏，焊球或将倒装芯片裸片耦合到衬底的焊料凸块。

公开(公告)号：US20110273856A1

公开(公告)日：2011-11-10

申请号：US13187404

申请日：2011-07-20

Applicant: Tomohiko NAWATA

Inventor： Tomohiko NAWATA

IPC: H05K1/18 ,  H05K7/02

CPC classification number: G01R31/2818 ,  H05K1/0268 ,  H05K1/0293 ,  H05K3/3452 ,  H05K3/3484 ,  H05K2201/0305 ,  H05K2203/043 ,  H05K2203/173

Abstract: A circuit board includes a board, a first conductive land over the board, a second conductive land over the board, a resist extending over the board, and a conductive material within the opening. The second conductive land is distanced from the first conductive land. The resist has an opening that extends over at leat a portion of the first conductive land, at least a portion of the second conductive land, and at least a portion of an intervening region of the board. The intervening region extends between the first and second conductive lands. The conductive material extends over the at least a portion of the intervening region, the at least a portion of the first conductive land, and the at least a portion of the second conductive land.

Abstract translation: 电路板包括板，板上的第一导电焊盘，板上的第二导电焊盘，在板上延伸的抗蚀剂以及开口内的导电材料。 第二个导电区距离第一个导电区域。 抗蚀剂具有在第一导电焊盘的一部分，第二导电焊盘的至少一部分以及板的中间区域的至少一部分上延伸的开口。 中间区域在第一和第二导电焊盘之间延伸。 导电材料在中间区域的至少一部分，第一导电焊盘的至少一部分和第二导电焊盘的至少一部分上延伸。

公开(公告)号：US08028403B2

公开(公告)日：2011-10-04

申请号：US12379156

申请日：2009-02-13

Applicant: Deepak K. Pai ,  Ronald R. Denny

Inventor： Deepak K. Pai ,  Ronald R. Denny

IPC: H05K3/36 ,  B23K31/00

CPC classification number: H05K3/462 ,  H01L2224/05548 ,  H05K3/28 ,  H05K3/3463 ,  H05K3/3484 ,  H05K3/4623 ,  H05K2201/0305 ,  H05K2201/0347 ,  H05K2201/0949 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2203/043 ,  H05K2203/063 ,  H05K2203/0733 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49147 ,  Y10T29/49149 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T29/49213

Abstract: The present invention provides a number of techniques for laminating and interconnecting multiple substrates to form a multilayer package or other circuit component. A solder bump may be formed on the conductive pad of at least one of two or more substrates. The solder bump preferably is formed from an application of solder paste to the conductive pad(s). Adhesive films may be positioned between the surfaces of the substrates having the conductive pads, where the adhesive films include apertures located substantially over the conductive pads such that the conductive pads and/or solder bumps confront each other through the aperture. The two or more substrates then may be pressed together to mechanically bond the two or more substrates via the adhesive films. The solder bump(s) may be reflowed during or after the lamination to create a solder segment that provides an electrical connection between the conductive pads through the aperture in the adhesive films.

Abstract translation: 本发明提供了用于层叠和互连多个基板以形成多层封装或其他电路部件的多种技术。 可以在两个或更多个基板中的至少一个的导电焊盘上形成焊料凸块。 焊料凸块优选地由焊膏应用于导电焊盘形成。 粘合剂膜可以位于具有导电焊盘的基板的表面之间，其中粘合剂膜包括基本上位于导电焊盘上方的孔，使得导电焊盘和/或焊料凸块通过孔彼此面对。 然后可以将两个或更多个基底压在一起以经由粘合剂膜机械地粘合两个或更多个基底。 可以在叠层期间或之后回流焊料凸块以产生焊接段，该焊料段通过粘合剂膜中的孔提供导电焊盘之间的电连接。

公开(公告)号：US08013536B2

公开(公告)日：2011-09-06

申请号：US12226602

申请日：2007-04-20

Applicant: Takeshi Hatakeyama

Inventor： Takeshi Hatakeyama

IPC: H05B37/00 ,  H05B39/00

CPC classification number: H05B41/2824 ,  H05B41/2821 ,  H05K1/0293 ,  H05K1/162 ,  H05K2201/0305 ,  H05K2201/09672 ,  H05K2203/171

Abstract: From the individual small areas of a conductor pattern arranged on the back side of a circuit board, there are individually extended leader patterns, which are midway led by through holes to the surface side of the circuit board. The individual leader patterns led to the surface side are connected with a terminal portion on the low-voltage side through jumper pads. The desired small areas are enabled to function by shorting the jumper pads with solder. The individual small areas are constituted to have a capacity of 1 pF, when caused to function, and they have such a capacity as a pattern capacitor as is proportional to the number of the shorted jumper pads.

Abstract translation: 从设置在电路板的背面的导体图案的各个小区域，存在单独延伸的引导图案，其中间通过通孔引导到电路板的表面侧。 导致表面侧的单个引线图案通过跨接垫与低压侧的端子部分连接。 通过用焊料短路跳线垫，可以使所需的小区域起作用。 各个小区域被构造成具有1pF的容量，当其起作用时，并且它们具有与短路跳线焊盘的数量成比例的图案电容器的容量。

公开(公告)号：US08008581B2

公开(公告)日：2011-08-30

申请号：US11466942

申请日：2006-08-24

Applicant: Tomohiko Nawata ,  Makiko Nawata, legal representative

Inventor： Tomohiko Nawata

IPC: H05K1/03

CPC classification number: G01R31/2818 ,  H05K1/0268 ,  H05K1/0293 ,  H05K3/3452 ,  H05K3/3484 ,  H05K2201/0305 ,  H05K2203/043 ,  H05K2203/173

Abstract: A circuit board includes a board, a first conductive pad provided on the board, a second conductive pad provided with a first distance from the first conductive pad. A mask extends over the board and has an opening that extends over at least a part of the first conductive pad, at least a part of the second conductive pad, and at least a part of an intervening region of the board between the first and second conductive pads. A conductive material is provided in the opening, and extends over the at least a part of the first conductive pad, the at least a part of the intervening region, and the at least a part of the second conductive pad.

Abstract translation: 电路板包括板，设置在板上的第一导电焊盘，设置有距第一导电焊盘第一距离的第二导电焊盘。 掩模在板上延伸并且具有在第一导电焊盘的至少一部分上延伸的开口，第二导电焊盘的至少一部分以及在第一和第二导电焊盘之间的板的中间区域的至少一部分 导电垫。 导电材料设置在开口中，并且在第一导电垫的至少一部分，中间区域的至少一部分和第二导电垫的至少一部分之上延伸。

公开(公告)号：US20110186335A1

公开(公告)日：2011-08-04

申请号：US13010441

申请日：2011-01-20

Applicant: Sheng-Cheng Chang ,  Chien-Chung Chiang ,  Wei-Lun Hsu ,  Jin-Fu Chen ,  Chien-Ming Yeh

Inventor： Sheng-Cheng Chang ,  Chien-Chung Chiang ,  Wei-Lun Hsu ,  Jin-Fu Chen ,  Chien-Ming Yeh

IPC: H05K7/20 ,  H05K3/12

CPC classification number: H05K1/0209 ,  H05K1/0207 ,  H05K3/3452 ,  H05K2201/0305 ,  H05K2201/09781 ,  Y10T29/49165

Abstract: The circuit board with a heat dissipating structure is provided. A first grounding conductor layer is formed on a first surface of a substrate. A first insulting layer is formed on the first grounding conductor layer and defines a number of circuit element pin openings and a plurality of heat dissipating openings therein so that the first grounding conductor layer is exposed from the circuit element pin openings and the heat dissipating openings. A number of solder balls are disposed in the circuit element pin openings and contacted with the first grounding conductor layer. A number of heat dissipating structures are disposed in the heat dissipating openings and contacted with the first grounding conductor layer. The heat dissipating structures and the solder balls have an identical material. The method for manufacturing the circuit board is also provided.

Abstract translation: 提供具有散热结构的电路板。 第一接地导体层形成在基板的第一表面上。 第一绝缘层形成在第一接地导体层上并且在其中限定多个电路元件针开口和多个散热开口，使得第一接地导体层从电路元件销开口和散热开口露出。 多个焊球设置在电路元件销开口中并与第一接地导体层接触。 多个散热结构设置在散热开口中并与第一接地导体层接触。 散热结构和焊球具有相同的材料。 还提供了用于制造电路板的方法。

公开(公告)号：US20110120759A1

公开(公告)日：2011-05-26

申请号：US13017544

申请日：2011-01-31

Applicant: Shigenobu SEKINE ,  Yurina SEKINE ,  Yoshiharu KUWANA

Inventor： Shigenobu SEKINE ,  Yurina SEKINE ,  Yoshiharu KUWANA

IPC: H05K1/09

CPC classification number: H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H05K3/4038 ,  H05K3/4061 ,  H05K3/4614 ,  H05K2201/0215 ,  H05K2201/0218 ,  H05K2201/0305 ,  H05K2201/0394 ,  H05K2201/083 ,  H05K2203/0285 ,  H05K2203/104 ,  H05K2203/128 ,  Y10T29/49155 ,  Y10T29/49156 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A circuit board includes a substrate, a circuit pattern and a through electrode. The circuit pattern is disposed on one side of the substrate in a thickness direction thereof. The through electrode is filled in a through-hole formed in the substrate with one end connected to the circuit pattern. The circuit pattern and the through electrode each have an area containing a noble metal component (e.g., Au component) and are connected to each other therethrough.

Abstract translation: 电路板包括基板，电路图案和通孔电极。 电路图案沿其厚度方向设置在基板的一侧。 通孔电极填充在形成在基板中的通孔中，其一端连接到电路图案。 电路图案和贯通电极各自具有含有贵金属成分（例如Au成分）的区域，并且通过其彼此连接。

公开(公告)号：US07871858B2

公开(公告)日：2011-01-18

申请号：US12314146

申请日：2008-12-04

Applicant: Nobuaki Hashimoto

Inventor： Nobuaki Hashimoto

IPC: H01L21/00

CPC classification number: H01L24/10 ,  H01L21/486 ,  H01L21/563 ,  H01L23/13 ,  H01L23/16 ,  H01L23/24 ,  H01L23/3114 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/562 ,  H01L24/13 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05548 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/81801 ,  H01L2224/83102 ,  H01L2224/83192 ,  H01L2224/83194 ,  H01L2224/8385 ,  H01L2224/92125 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/07811 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/15151 ,  H01L2924/15183 ,  H01L2924/15184 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/351 ,  H05K1/112 ,  H05K3/3457 ,  H05K3/386 ,  H05K3/4038 ,  H05K2201/0305 ,  H05K2201/0394 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/05647 ,  H01L2224/05099 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2224/85399

Abstract: A method of manufacturing a semiconductor device forms a penetrating hole in a substrate so that the penetrating hole extends from a first surface of the substrate to a second surface of the substrate being opposite to the first surface. An internal wall surface of the penetrating hole has a protrusion formed of a material constituting the substrate, the first surface of the substrate being closer to the protrusion than the second surface. A conductive member is formed on the first surface so that the conductive member covers the penetrating hole. A semiconductor chip is mounted on the first surface so that an electrode of the semiconductor chip is electrically connected to the conductive member. An external electrode is provided through the penetrating hole so that the external electrode is electrically connected to the conductive member and the external electrode projects from the second surface of the substrate.

Abstract translation: 半导体器件的制造方法在基板中形成贯通孔，使得贯通孔从基板的第一面延伸到与第一面相反的基板的第二面。 所述贯通孔的内壁面具有由构成所述基板的材料形成的突起，所述基板的所述第一表面比所述第二表面更靠近所述突起。 导电构件形成在第一表面上，使得导电构件覆盖穿透孔。 半导体芯片安装在第一表面上，使得半导体芯片的电极电连接到导电构件。 通过贯通孔设置外部电极，使得外部电极与导电部件电连接，外部电极从基板的第二面突出。