公开(公告)号：US07355863B2

公开(公告)日：2008-04-08

申请号：US11147332

申请日：2005-06-08

Applicant: Ryota Suzuki ,  Taihei Nakada ,  Tsuyoshi Kumamoto ,  Yuusuke Yamashita

Inventor： Ryota Suzuki ,  Taihei Nakada ,  Tsuyoshi Kumamoto ,  Yuusuke Yamashita

IPC: H05K1/11 ,  H05K1/14

CPC classification number: H01L23/50 ,  H01L23/552 ,  H01L2924/0002 ,  H01L2924/15153 ,  H01L2924/1517 ,  H05K1/0218 ,  H05K1/0243 ,  H05K1/0298 ,  H05K1/113 ,  H05K1/115 ,  H05K1/182 ,  H05K2201/0715 ,  H05K2201/0723 ,  H05K2201/09336 ,  H05K2201/10545 ,  H01L2924/00

Abstract: A high frequency multilayer integrated circuit is provided with: a multilayer board including n earth conductor layers (n: integer of two or more than two) and (n-1) dielectric layers each arranged between adjacent earth conductor layers; a first high frequency circuit disposed in one of the most outside earth conductor layers of the multilayer board; a first power-supply/control circuit disposed in this most outside earth conductor layer; a second high frequency circuit disposed in at least one of the dielectric layers and connected to the first high frequency circuit in the multilayer board; a second power-supply/control circuit disposed in another one of the most outside earth conductor layers of the multilayer board; and a third power-supply/control circuit disposed in at least one of the dielectric layers at a portion at which the second high frequency circuit does not exist, the third power-supply/control circuit being connected to the first and second power-supply/control circuits.

Abstract translation: 高频多层集成电路具备：分别配置在相邻的接地导体层之间的n个接地导体层（n为2以上的整数）和（n-1）个电介质层的多层基板; 设置在所述多层板的最外侧的接地导体层之一中的第一高频电路; 设置在该最外部接地导体层中的第一电源/控制电路; 设置在所述电介质层中的至少一个并连接到所述多层板中的所述第一高频电路的第二高频电路; 第二电源/控制电路，设置在所述多层板的最外部的接地导体层中的另一个中; 以及第三电源/控制电路，设置在所述第二高频电路不存在的部分的所述电介质层中的至少一个中，所述第三电源/控制电路连接到所述第一和第二电源 /控制电路。

公开(公告)号：US20070173086A1

公开(公告)日：2007-07-26

申请号：US10591890

申请日：2005-09-16

Applicant: Claus Schmiederer ,  Michael Haerer ,  Tobias Kuechen

Inventor： Claus Schmiederer ,  Michael Haerer ,  Tobias Kuechen

IPC: H01R13/648

CPC classification number: H02K11/026 ,  H02K11/024 ,  H05K1/0231 ,  H05K2201/0715 ,  H05K2201/09318

Abstract: An interference suppressor (10) for suppressing high-frequency interference emissions of a direct current motor (26) that is drivable in a plurality of stages and/or directions is proposed, having a plurality of capacitors (16) located on a first side (12) of a printed circuit board (14) and having a plurality of first conductor tracks (18), located on the first side (12) of the printed circuit board (14), for putting the various capacitors (16) into contact with a ground terminal (20), and having a first terminal (22) and at least one further terminal (24) for the individual stages of the direct current motor (26), the first terminal (22) and the at least one further terminal (24) being put into contact with a first connection line (48) for the first stage and at least one further connection line (50) for the at least one further stage of the direct current motor (26). The interference suppressor (10) is characterized in that a ground face (34) is located on a further side (32), diametrically opposite the first side (12), of the printed circuit board (14), and the first connection line (48) and the at least one further connection line (50) are fed through in insulated fashion relative to the ground face (34).

Abstract translation: 提出了用于抑制在多个级和/或方向上可驱动的直流电动机（26）的高频干扰发射的干扰抑制器（10），其具有位于第一侧的多个电容器（16） （14）的多个第一导体轨道（18），位于印刷电路板（14）的第一侧（12）上，用于将各种电容器（16）与 接地端子（20），并且具有用于直流电动机（26）的各个级的第一端子（22）和至少一个另外的端子（24），第一端子（22）和至少一个另外的端子 （24）与用于第一级的第一连接线（48）和用于直流电动机（26）的至少另一级的至少一个另外的连接线（50）接触。 干涉抑制器（10）的特征在于，接地面（34）位于与印刷电路板（14）的第一侧（12）直径相对的另一侧（32）上，并且第一连接线 48），并且所述至少一个另外的连接线（50）相对于所述接地面（34）以绝缘方式进给。

公开(公告)号：US07243423B2

公开(公告)日：2007-07-17

申请号：US11000255

申请日：2004-11-30

Applicant: Dustin P. Wood

Inventor： Dustin P. Wood

IPC: H01R43/00

CPC classification number: H05K1/0224 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2924/15311 ,  H01L2924/3011 ,  H05K1/0253 ,  H05K1/112 ,  H05K3/4602 ,  H05K2201/0715 ,  H05K2201/093 ,  H05K2201/09681 ,  H05K2203/1178 ,  Y10S428/901 ,  Y10T29/49155 ,  Y10T428/24917

Abstract: A semiconductor device package includes multiple built-up layers of metal sandwiching non-conductive layers. The metal layers have grids of degassing holes arranged in rows and columns. The rows and columns are locatable via a first coordinate system. Signal traces are embedded within the non-conductive layers such that the signal traces are also sandwiched between the metal layers with degassing holes. The signal traces generally run at zero degrees, 45 degrees, and 90 degrees relative to a second coordinate system. The first coordinate system is rotated relative to the second coordinate system to lower impedance variations of different traces. Impedance variations decrease due to the decreased variation in the number of degassing holes passed over or under by a trace. The grid of degassing holes on one metal layer can be offset in two dimensions relative to the degassing holes on another layer.

Abstract translation: 半导体器件封装包括金属夹层非导电层的多个堆积层。 金属层具有以排和列排列的脱气孔格栅。 行和列可通过第一个坐标系定位。 信号迹线嵌入在非导电层内，使得信号迹线也被夹在具有脱气孔的金属层之间。 信号迹线通常相对于第二坐标系以零度，45度和90度的速度运行。 第一坐标系相对于第二坐标系旋转以降低不同轨迹的阻抗变化。 阻抗变化由于通过痕迹通过或减少的脱气孔的数量的变化减小而减小。 一个金属层上的脱气孔的网格可以相对于另一层上的脱气孔在两个维度上偏移。

公开(公告)号：US20070053167A1

公开(公告)日：2007-03-08

申请号：US11517402

申请日：2006-09-08

Applicant: Jun Ueda

Inventor： Jun Ueda

IPC: H05K7/20

CPC classification number: H01L23/3121 ,  H01L23/66 ,  H01L24/45 ,  H01L24/48 ,  H01L25/162 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/07811 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/1305 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/1532 ,  H01L2924/16152 ,  H01L2924/16195 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19106 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/0218 ,  H05K1/0237 ,  H05K1/144 ,  H05K1/145 ,  H05K2201/0715 ,  H05K2201/10378 ,  H05K2201/10477 ,  H05K2201/10666 ,  H05K2201/2018 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: An electronic circuit module includes (i) a semiconductor integrated circuit component which is a transistor integrated circuit formed on a semiconductor substrate, (ii) a passive element component constituting a peripheral circuit of the semiconductor integrated circuit component, and (iii) first and second circuit substrates each of which has a component mounting surface on which at least one of the semiconductor integrated circuit component and the passive element component. The respective component mounting surfaces of the first and second circuit substrate face one another. The first circuit substrate functions as one outer wall of a housing, where the electronic circuit module contacts an external circuit substrate on which the electronic circuit module is mounted. The second circuit substrate functions as the other outer wall of the housing of the module.

Abstract translation: 电子电路模块包括：（i）半导体集成电路部件，其是形成在半导体基板上的晶体管集成电路，（ii）构成半导体集成电路部件的外围电路的无源元件部件，以及（iii）第一和第二 电路基板，每个基板具有其上至少一个半导体集成电路部件和无源元件部件的部件安装表面。 第一和第二电路基板的各个部件安装表面彼此面对。 第一电路基板用作壳体的一个外壁，其中电子电路模块接触安装有电子电路模块的外部电路基板。 第二电路基板用作模块壳体的另一个外壁。

公开(公告)号：US20070013056A1

公开(公告)日：2007-01-18

申请号：US11362882

申请日：2006-02-28

Applicant: Si-Hoon Lee ,  Eun-Seok Song

Inventor： Si-Hoon Lee ,  Eun-Seok Song

IPC: H01L23/34

CPC classification number: H01L23/552 ,  H01L23/36 ,  H01L23/3677 ,  H01L23/49838 ,  H01L23/4985 ,  H01L23/50 ,  H01L24/17 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/13099 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/181 ,  H05K1/0216 ,  H05K1/113 ,  H05K1/189 ,  H05K2201/0715 ,  H05K2201/09318 ,  H01L2924/00 ,  H01L2224/05599

Abstract: A chip-on-film package may include a tape wiring substrate, a semiconductor chip mounted on the tape wiring substrate, and a molding compound provided between the semiconductor chip and the tape wiring substrate. The tape wiring substrate may include a film having upper and lower surfaces. Vias may penetrate the film. An upper metal layer may be provided on the upper surface of the film and include input terminal patterns and/or output terminal patterns. The input terminal patterns may include ground terminal patterns and/or power terminal patterns. A lower metal layer may be provided on the lower surface of the film and include a ground layer and/or a power layer. The ground layer and the power layer may cover at least a chip mounting area.

Abstract translation: 胶片封装可以包括带布线基板，安装在带布线基板上的半导体芯片，以及设置在半导体芯片和带布线基板之间的模塑料。 带状布线基板可以包括具有上表面和下表面的膜。 通风口可能会穿透电影。 上层金属层可以设置在膜的上表面上并且包括输入端子图案和/或输出端子图案。 输入端子图案可以包括接地端子图案和/或电源端子图案。 下部金属层可以设置在膜的下表面上并且包括接地层和/或功率层。 接地层和功率层可以至少覆盖芯片安装区域。

公开(公告)号：US20060264092A1

公开(公告)日：2006-11-23

申请号：US11384239

申请日：2006-03-21

Applicant: Hideto Kumakura ,  Nobuyuki Asakura

Inventor： Hideto Kumakura ,  Nobuyuki Asakura

IPC: H01R11/20

CPC classification number: H05K9/0024 ,  H01R12/594 ,  H01R12/616 ,  H01R12/68 ,  H05K1/0218 ,  H05K1/0393 ,  H05K3/326 ,  H05K3/4046 ,  H05K2201/0715 ,  H05K2203/1189

Abstract: Providing a method of shielding a flat circuit body, which can improve efficiency of assembling a shield film and reliability thereof, and a wiring harness including the shielded flat circuit body, the shielded flat circuit body of the wiring harness includes a FFC having insulator covering around a conductor, a shield film covering the FFC and a connecting terminal. The clamp blade is pierced through an end of the FFC and is bent so as to connect electrically to the conductor. A joint blade extending perpendicularly from a joint terminal, which connects a plurality of conductors to each other, is pierced through the shield film and the FFC in the same direction of piercing the clamp blade, and is bent so as to connect the conductor and the shield film electrically.

Abstract translation: 提供一种屏蔽扁平电路体的方法，其可以提高组装屏蔽膜的效率及其可靠性，以及包括屏蔽扁平电路体的线束，线束的屏蔽扁平电路体包括具有绝缘体覆盖的FFC 导体，覆盖FFC的屏蔽膜和连接端子。 夹紧刀片穿过FFC的端部并被弯曲以便与导体电连接。 从连接多个导体的接合端子垂直地延伸的接合刀片穿过屏蔽膜和FFC穿过夹持刀片的相同方向被弯曲，从而将导体和 屏蔽膜电气。

公开(公告)号：US07122787B2

公开(公告)日：2006-10-17

申请号：US10829576

申请日：2004-04-22

Applicant: Hiroshi Nishizawa

Inventor： Hiroshi Nishizawa

IPC: H01L27/14 ,  H01L31/0203

CPC classification number: H01L27/14 ,  H04N5/2253 ,  H04N5/2254 ,  H04N5/2257 ,  H05K1/0274 ,  H05K1/189 ,  H05K2201/0715 ,  H05K2201/10121

Abstract: Light that has entered a lens held by a barrel portion of a three-dimensional circuit board transmitting virtually no visible light enters a semiconductor imaging device held inside the three-dimensional circuit board. On the side opposite to the barrel portion, the three-dimensional circuit board is provided with a flexible printed circuit for sending a signal to and receiving a signal from the semiconductor imaging device. The region of the flexible printed circuit facing the semiconductor imaging device has sufficient shielding characteristics in a range sensitive to light reception by the semiconductor imaging device. This makes it possible to provide a sufficient shield against a light beam entering from the back surface of the semiconductor imaging device, so that the image quality does not deteriorate even when a conventional shielding sheet is not used. Since the shielding sheet becomes unnecessary, it is possible to reduce the cost of the shielding sheet itself and the number of steps of bonding the shielding sheet. Furthermore, the thickness corresponding to the shielding sheet and the adhesive can be reduced.

Abstract translation: 已经进入透过实际上不可见光的三维电路板的筒部保持的透镜的光进入保持在三维电路板内部的半导体成像装置。 在与筒部相对的一侧上，三维电路板设置有用于向半导体成像装置发送信号并从其接收信号的柔性印刷电路。 面对半导体成像装置的柔性印刷电路的区域在半导体成像装置的光接收敏感范围内具有足够的屏蔽特性。 这使得可以提供对从半导体成像装置的背面进入的光束的足够的屏蔽，使得即使不使用传统的屏蔽片也不会劣化图像质量。 由于不需要屏蔽片，因此可以降低屏蔽片本身的成本和接合屏蔽片的步骤的数量。 此外，可以减少对应于屏蔽片和粘合剂的厚度。

公开(公告)号：US20060225915A1

公开(公告)日：2006-10-12

申请号：US11403086

申请日：2006-04-12

Applicant: Araf Suhail

Inventor： Araf Suhail

IPC: H05K1/11 ,  H05K1/16

CPC classification number: H05K1/0218 ,  H05K1/0298 ,  H05K2201/0715 ,  H05K2201/09618

Abstract: A printed circuit board (PCB) is provided for use in electrical apparatus. The PCB has a plurality of layers, at least one layer being dedicated to define the PCB's external electromagnetic environment and at least one further layer used for another known PCB function.

Abstract translation: 提供用于电气设备的印刷电路板（PCB）。 PCB具有多个层，专门用于限定PCB的外部电磁环境的至少一个层和用于另一已知PCB功能的至少一个另外的层。

公开(公告)号：US07086788B2

公开(公告)日：2006-08-08

申请号：US11095637

申请日：2005-03-30

Applicant: William Paul Mazotti ,  Peter Deane ,  Luu Thanh Nguyen ,  Ken Pham ,  Bruce Carlton Roberts ,  Jia Liu ,  Yongseon Koh ,  John P. Briant ,  Roger William Clarke ,  Michael R. Nelson ,  Christopher J. Smith ,  Janet E. Townsend

Inventor： William Paul Mazotti ,  Peter Deane ,  Luu Thanh Nguyen ,  Ken Pham ,  Bruce Carlton Roberts ,  Jia Liu ,  Yongseon Koh ,  John P. Briant ,  Roger William Clarke ,  Michael R. Nelson ,  Christopher J. Smith ,  Janet E. Townsend

IPC: G02B6/36

CPC classification number: G02B6/4201 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48465 ,  H05K1/0219 ,  H05K1/189 ,  H05K3/403 ,  H05K2201/0715 ,  H05K2201/09236 ,  H05K2201/10121 ,  H01L2924/00014 ,  H01L2924/00

Abstract: Concepts for conveniently arranging devices for the transduction of signals to and from voltage and current domains to infrared radiation domains is described. Specifically, optoelectronic components and methods of making the same are described. In one aspect, the optoelectronic component includes a base substrate having a pair of angled (or substantially perpendicular) faces with electrical traces extending therebetween. A semiconductor chip assembly is mounted on the first face of the base substrate and a photonic device is mounted on the second face. Both the semiconductor chip assembly and the photonic device are electrically connected to traces on the base substrate. The semiconductor chip assembly is generally arranged to be electrically connected to external devices. The photonic devices are generally arranged to optically communicate with one or more optical fibers. The described structure may be used with a wide variety of photonic devices. In some embodiments the base substrate is formed from a ceramic material having the electrical traces formed thereon. In other implementations the substrate includes a backing block having a flexible printed circuit substrate adhered thereto.

Abstract translation: 描述了用于方便地布置用于将电压和电流域的信号传导到红外辐射域的装置的概念。 具体地说，描述了光电子元件及其制造方法。 在一个方面，光电子部件包括具有一对成角度（或基本上垂直）的表面的基底基板，其间延伸有电迹线。 半导体芯片组件安装在基底基板的第一面上，并且光子器件安装在第二面上。 半导体芯片组件和光子器件都与基底衬底上的迹线电连接。 半导体芯片组件通常被布置成电连接到外部设备。 光子器件通常布置成与一根或多根光纤光学通信。 所描述的结构可以与各种各样的光子器件一起使用。 在一些实施例中，基底由具有形成在其上的电迹线的陶瓷材料形成。 在其它实施方式中，基板包括具有粘附到其上的柔性印刷电路基板的背衬块。

公开(公告)号：US20060164179A1

公开(公告)日：2006-07-27

申请号：US11290681

申请日：2005-12-01

Applicant: Tatsuya Arai ,  Toshiyuki Takada

Inventor： Tatsuya Arai ,  Toshiyuki Takada

IPC: H03H7/38

CPC classification number: H05K1/116 ,  H01P1/047 ,  H05K1/0216 ,  H05K1/0251 ,  H05K1/114 ,  H05K3/429 ,  H05K2201/0715 ,  H05K2201/09336 ,  H05K2201/09727 ,  H05K2201/10189 ,  H05K2201/10734

Abstract: A multilayer interconnection board (10) comprises a dielectric substrate (11), a through-hole (15), a signal line (12) having a large width section (12A) and a small width section (12B) connected with the through-hole (15), and a ground layer (13, 14). A length L (mm) of the small width section (12B) meets the formula of 0

Abstract translation: 多层互连板（10）包括电介质基板（11），通孔（15），具有大宽度部分（12A）的信号线（12）和与其相连的小宽度部分（12B） 通孔（15）和接地层（13,14）。 小宽度部分（12B）的长度L（mm）满足公式0