公开(公告)号：US06856008B2

公开(公告)日：2005-02-15

申请号：US10641037

申请日：2003-08-15

Applicant: Deepak K. Pai ,  Ronald R. Denny

Inventor： Deepak K. Pai ,  Ronald R. Denny

IPC: H05K1/14 ,  H01L23/12 ,  H05K3/28 ,  H05K3/34 ,  H05K3/36 ,  H05K3/46 ,  H01L23/02

CPC classification number: H05K3/462 ,  H01L2224/05548 ,  H05K3/28 ,  H05K3/3463 ,  H05K3/3484 ,  H05K3/4623 ,  H05K2201/0305 ,  H05K2201/0347 ,  H05K2201/0949 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2203/043 ,  H05K2203/063 ,  H05K2203/0733 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49147 ,  Y10T29/49149 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T29/49213

Abstract: The present invention provides a number of techniques for laminating and interconnecting multiple high-layer-count (HLC) substrates to form a multilayer package or other circuit component. A solder bump may be formed on the conductive pad of at least one of two HLC substrates. The solder bump preferably is formed from an application of solder paste to the conductive pad(s). An adhesive film may be positioned between the surfaces of the HLC substrates having the conductive pads, where the adhesive film includes an aperture located substantially over the conductive pads such that the conductive pads and/or solder bumps confront each other through the aperture. The HLC substrates then may be pressed together to mechanically bond the two substrates via the adhesive. The solder bump(s) may be reflowed during or after the lamination to create a solder segment that provides an electrical connection between the two conductive pads through the aperture in the adhesive film.

Abstract translation: 本发明提供了用于层叠和互连多个高层计数（HLC）衬底以形成多层封装或其它电路部件的多种技术。 可以在两个HLC衬底中的至少一个的导电焊盘上形成焊料凸块。 焊料凸块优选地由焊膏应用于导电焊盘形成。 粘合剂膜可以位于具有导电焊盘的HLC衬底的表面之间，其中粘合剂膜包括基本上位于导电焊盘上方的孔，使得导电焊盘和/或焊料凸块通过孔彼此面对。 然后可以将HLC基底压在一起以经由粘合剂机械地粘合两个基底。 在叠层期间或之后可以回流焊料凸点，以产生焊接段，该焊料段通过粘合膜中的孔提供两个导电焊盘之间的电连接。

公开(公告)号：US20050008833A1

公开(公告)日：2005-01-13

申请号：US10854598

申请日：2004-05-26

Applicant: Brian Curcio ,  Frank Egitto ,  Robert Japp ,  Thomas Miller ,  Manh-Quan Nguyen ,  Douglas Powell

Inventor： Brian Curcio ,  Frank Egitto ,  Robert Japp ,  Thomas Miller ,  Manh-Quan Nguyen ,  Douglas Powell

IPC: H01L21/48 ,  H05K3/40 ,  H05K3/46 ,  B32B3/00

CPC classification number: H01L21/486 ,  H05K3/4069 ,  H05K3/4614 ,  H05K3/462 ,  H05K2201/09536 ,  H05K2201/096 ,  H05K2203/0191 ,  H05K2203/0264 ,  H05K2203/061 ,  H05K2203/1152 ,  Y10S438/976 ,  Y10T29/49165 ,  Y10T428/24917 ,  Y10T428/28 ,  Y10T428/2804 ,  Y10T428/2839 ,  Y10T428/2848

Abstract: A method for producing small pitch z-axis electrical interconnections in layers of dielectric materials which are applied to printed wiring boards and diverse electronic packages. A method for parallel fabrication of intermediate structures which are subsequently jointed to form a final structure. In addition there is provided a z-interconnected electrical structure, employing dielectric materials such as resin coated copper, employable in the manufacture of diverse type of electronic packages, including printed wiring boards (PWBs), substrates, multi-chip modules and the like.

公开(公告)号：US20040226742A1

公开(公告)日：2004-11-18

申请号：US10437006

申请日：2003-05-14

Inventor： Aneta Wyrzykowska ,  Herman Kwong ,  Luigi Difilippo

IPC: H05K007/10

CPC classification number: H05K1/112 ,  H01L2224/14 ,  H01L2224/17 ,  H01L2924/00014 ,  H05K3/303 ,  H05K3/4623 ,  H05K2201/09472 ,  H05K2201/09518 ,  H05K2201/09536 ,  H05K2201/10318 ,  H05K2201/10424 ,  H05K2201/10659 ,  H05K2201/10704 ,  H05K2201/10734 ,  Y02P70/613 ,  Y10T29/4913 ,  Y10T29/49135 ,  Y10T29/49139 ,  Y10T29/49147 ,  Y10T29/49165 ,  H01L2224/0401

Abstract: A method for implementing a circuit component on a surface of a multilayer circuit board is provided. The circuit component includes a plurality of pins and the circuit board includes a plurality of electrically conductive vias penetrating at least one layer of the circuit board and being arranged so as to form at least one channel for routing one or more traces at one or more signal layers of the circuit board. The method comprises the step of forming at least one pin of the plurality of pins of the circuit component to have a length compatible with a depth of a corresponding via of the circuit board.

Abstract translation: 提供一种在多层电路板的表面上实现电路元件的方法。 电路部件包括多个引脚，并且电路板包括穿透电路板的至少一个层的多个导电通孔，并被布置成形成用于在一个或多个信号处路由一个或多个迹线的至少一个通道 层的电路板。 该方法包括以下步骤：形成电路部件的多个引脚中的至少一个引脚以具有与电路板的相应通孔的深度相兼容的长度。

公开(公告)号：US06809269B2

公开(公告)日：2004-10-26

申请号：US10322527

申请日：2002-12-19

Applicant: James W. Fuller, Jr. ,  John M. Lauffer ,  Voya R. Markovich

Inventor： James W. Fuller, Jr. ,  John M. Lauffer ,  Voya R. Markovich

IPC: H01R1204

CPC classification number: H05K3/462 ,  H05K3/321 ,  H05K3/4069 ,  H05K3/429 ,  H05K3/4623 ,  H05K2201/0347 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/096 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49151 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T29/49167

Abstract: A circuitized substrate assembly and method for making same wherein the assembly includes individual circuitized substrates bonded together. The substrates each include at least one opening, only one of which is substantially filled with a conductive paste prior to bonding. Once bonded, the paste is also partially located within the other opening to provide an effective electrical connection therewith.

公开(公告)号：US06802120B2

公开(公告)日：2004-10-12

申请号：US10191986

申请日：2002-07-10

Applicant: Toshiki Uehara

Inventor： Toshiki Uehara

IPC: H05K310

CPC classification number: H05K1/112 ,  H05K1/18 ,  H05K3/4069 ,  H05K3/4623 ,  H05K3/4652 ,  H05K2201/035 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/10189 ,  H05K2201/1059 ,  H05K2203/1572 ,  Y10S29/016 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165

Abstract: A method of manufacturing a printed wiring board, enabling insertion components to be mounted on both sides thereof, including: a) providing first and second copper-clad laminates, including plated through-holes thereon; b) hot-pressing the laminates with each other and a first prepreg bonding sheet therebetween, so that the through-holes are closed by the prepreg to form non-through holes; c) laminating a second prepreg on each of the surfaces of the composite laminate; d) covering the opening of respective non-through holes with a heat resistant resin film; e) laminating one-side copper-clad laminate on each of the surfaces of the product of (d), with the copper side out, followed by hot-pressing; f) etching the copper sides to form outer layer circuit patterns; g) removing the base material layers covering the openings of the non-through holes; and h) removing the heat resistant resin films of the openings of the non-through holes.

Abstract translation: 一种制造印刷电路板的方法，其能够在两侧安装插入部件，包括：a）提供第一和第二铜包覆层压板，其上包括镀覆的通孔; b）将层叠体彼此热压，并在其间进行第一预浸料接合片，使得通孔被预浸料坯封闭以形成非通孔; c）在复合层压板的每个表面上层压第二预浸料; d）用耐热树脂膜覆盖各个非通孔的开口; e）在（d）的产品的每个表面上层叠一面覆铜层压板，将铜侧排出，然后热压; f）蚀刻铜边以形成外层电路图案; g）去除覆盖非通孔的开口的基材层; 以及h）去除非通孔的开口的耐热树脂膜。

公开(公告)号：US06800537B2

公开(公告)日：2004-10-05

申请号：US10342969

申请日：2003-01-15

Applicant: Belgacem Haba

Inventor： Belgacem Haba

IPC: H01L2130

CPC classification number: H01L21/568 ,  B29C70/62 ,  B29C70/882 ,  G02F1/1339 ,  H01L21/6835 ,  H01L23/49827 ,  H01L24/27 ,  H01L24/29 ,  H01L24/83 ,  H01L2224/27438 ,  H01L2224/29101 ,  H01L2224/2919 ,  H01L2224/29499 ,  H01L2224/83101 ,  H01L2224/83192 ,  H01L2224/83851 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/0781 ,  H01L2924/12044 ,  H01L2924/14 ,  H05K3/323 ,  H05K3/368 ,  H05K3/4623 ,  H05K2201/0133 ,  H05K2201/0248 ,  H05K2201/083 ,  H05K2201/09536 ,  H05K2203/104 ,  H05K2203/105 ,  H01L2924/00

Abstract: A layer of an anisotropic material has a pair of substantially flat oppositely-directed major faces, a vertical direction extending between the faces and horizontal directions transverse to the vertical direction, the layer including a dielectric material and a plurality of conductive particles in the dielectric material. The particles are distributed non-uniformly in the horizontal directions so as to provide areas of high particle concentration interspersed with areas of low particle concentration.

Abstract translation: 各向异性材料层具有一对基本平坦的相反方向的主面，垂直方向在横向于垂直方向的面和水平方向之间延伸，所述层包括电介质材料和电介质材料中的多个导电颗粒 。 颗粒在水平方向上不均匀地分布，以提供散布有低颗粒浓度区域的高颗粒浓度的区域。

公开(公告)号：US20040150969A1

公开(公告)日：2004-08-05

申请号：US10354000

申请日：2003-01-30

Applicant: Endicott Interconnect Technologies Inc.

Inventor： Benson Chan ,  John M. Lauffer ,  How T. Lin ,  Voya R. Markovich ,  David L. Thomas

IPC: H05K001/11

CPC classification number: H05K3/4688 ,  H01L23/3128 ,  H01L23/5383 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/18 ,  H01L2224/16 ,  H01L2224/73253 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/16195 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/024 ,  H05K1/113 ,  H05K3/4623 ,  H05K2201/09536 ,  H05K2201/096 ,  H05K2203/061 ,  Y10T29/49126 ,  Y10T29/49165 ,  H01L2224/0401

Abstract: A multilayered PCB including two multilayered portions, one of these able to electrically connect electronic components mounted on the PCB to assure high frequency connections therebetween. The PCB further includes a conventional PCB portion to reduce costs while assuring a structure having a satisfactory overall thickness for use in the PCB field. Coupling is also possible to the internal portion from these components. Methods of making these structures have also been provided.

公开(公告)号：US20040150114A1

公开(公告)日：2004-08-05

申请号：US10394107

申请日：2003-03-24

Applicant: Endicott Interconnect Technologies, Inc.

Inventor： Lawrence R. Fraley ,  Voya R. Markovich

IPC: H01L023/48 ,  H01L023/52 ,  H01L029/40

CPC classification number: H01L25/18 ,  H01L23/3128 ,  H01L23/5383 ,  H01L25/0652 ,  H01L25/0655 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/16195 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/024 ,  H05K1/113 ,  H05K3/4623 ,  H05K3/4688 ,  H05K2201/09536 ,  H05K2201/096 ,  H05K2201/10378 ,  H05K2203/061 ,  H01L2224/0401

Abstract: A multi-chip electronic package which utilizes an organic, laminate chip carrier and a plurality of semiconductor chips positioned on an upper surface of the carrier. The organic, laminate chip carrier is comprised of a plurality of conductive planes and dielectric layers and couples the chips to underlying conductors on the bottom surface thereof. The carrier may include a high-speed portion to assure high-frequency connection between the semiconductor chips and may also include an internal capacitor and/or thermally conductive member for enhanced operational capabilities.

Abstract translation: 一种多芯片电子封装，其利用位于载体的上表面上的有机层压芯片载体和多个半导体芯片。 有机层压芯片载体由多个导电平面和电介质层组成，并将芯片连接到其底表面上的底层导体。 载体可以包括高速部分，以确保半导体芯片之间的高频连接，并且还可以包括用于增强操作能力的内部电容器和/或导热构件。

公开(公告)号：US20040150095A1

公开(公告)日：2004-08-05

申请号：US10661616

申请日：2003-09-15

Applicant: Endicott Interconnect Technologies, Inc.

Inventor： Lawrence R. Fraley ,  Voya Markovich

IPC: H01L023/538

CPC classification number: H01L25/18 ,  H01L23/3128 ,  H01L23/5383 ,  H01L25/0652 ,  H01L25/0655 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/16195 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/024 ,  H05K1/113 ,  H05K3/4623 ,  H05K3/4688 ,  H05K2201/09536 ,  H05K2201/096 ,  H05K2201/10378 ,  H05K2203/061 ,  H01L2224/0401

Abstract: A multi-chip electronic package which utilizes an organic, laminate chip carrier and a pair of semiconductor chips positioned on an upper surface of the carrier in a stacked orientation. The organic, laminate chip carrier is comprised of a plurality of conductive planes and dielectric layers and couples one or both of the chips to underlying conductors on the bottom surface thereof. The carrier may include a high-speed portion to assure high-frequency connection between the semiconductor chips and may also include an internal capacitor and/or thermally conductive member for enhanced operational capabilities. The first chip, e.g., an ASIC chip, is solder bonded to the carrier while the second chip, e.g., a memory chip, is secured to the first chip's upper surface and coupled to the carrier using a plurality of wirebond connections.

Abstract translation: 一种多芯片电子封装，其利用位于载体的上表面上的堆叠取向的有机层压芯片载体和一对半导体芯片。 有机层压芯片载体由多个导电平面和电介质层组成，并将芯片中的一个或两个耦合到其底表面上的下面的导体。 载体可以包括高速部分，以确保半导体芯片之间的高频连接，并且还可以包括用于增强操作能力的内部电容器和/或导热构件。 第一芯片（例如ASIC芯片）被焊接到载体上，而第二芯片（例如存储器芯片）被固定到第一芯片的上表面并且使用多个引线键合连接到载体。

公开(公告)号：US20040136168A1

公开(公告)日：2004-07-15

申请号：US10407460

申请日：2003-04-07

Inventor： Guy M.A.F. Duxbury ,  Aneta Wyrzykowska ,  Luigi G. Difilippo ,  Herman Kwong

IPC: H02H003/00

CPC classification number: H05K1/115 ,  H05K1/0298 ,  H05K1/112 ,  H05K3/0005 ,  H05K3/429 ,  H05K3/4602 ,  H05K2201/09227 ,  H05K2201/09236 ,  H05K2201/09263 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/09627 ,  H05K2201/10734 ,  Y10T29/49016 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: Techniques for reducing the number of layers in a multilayer signal routing device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a method wherein the multilayer signal routing device has a plurality of electrically conductive signal path layers for routing a plurality of electrical signals thereon. The method may comprise forming a plurality of electrically conductive vias in the multilayer signal routing device for electrically connecting at least two of the plurality of electrically conductive signal path layers, wherein the plurality of vias are arranged so as to form at least one channel in at least one other of the plurality of electrically conductive signal path layers. The method may also comprise grouping at least a portion of the plurality of electrical signals based at least in part upon their proximity to the at least one channel so that they may be efficiently routed therein.

Abstract translation: 公开了用于减少多层信号路由设备中的层数的技术。 在一个特定的示例性实施例中，这些技术可以被实现为一种方法，其中多层信号路由设备具有用于在其上路由多个电信号的多个导电信号路径层。 所述方法可以包括在所述多层信号路由设备中形成多个导电通孔，用于电连接所述多个导电信号路径层中的至少两个，其中所述多个通孔被布置成在其中形成至少一个通道 多个导电信号路径层中的至少另一个。 该方法还可以包括至少部分地基于它们与至少一个信道的接近度来分组多个电信号的至少一部分，使得它们可以被有效地路由到其中。