公开(公告)号：US20120281375A1

公开(公告)日：2012-11-08

申请号：US13551151

申请日：2012-07-17

Applicant: Shih-Ping Hsu

Inventor： Shih-Ping Hsu

IPC: H05K1/18

CPC classification number: H05K1/185 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5389 ,  H01L23/66 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/04105 ,  H01L2224/20 ,  H01L2224/211 ,  H01L2224/2518 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/18162 ,  H05K3/4602 ,  H05K3/465 ,  H05K2201/0376 ,  H05K2201/10674 ,  H01L2924/00

Abstract: A circuit board having a semiconductor chip embedded therein includes: a core board having opposing first and second surfaces and a through-hole; a semiconductor chip received in the through-hole and having a first active surface and an opposing second active surface, wherein first electrode pads comprising signal pads, power pads, and ground pads are provided on the first active surface; a first dielectric layer provided on the first surface of the core board and the first active surface of the semiconductor chip and configured to fill a gap between the through-hole and the semiconductor chip so as to secure the semiconductor chip in position to the through-hole; and a first circuit layer disposed in the first dielectric layer so as to be flush with the first dielectric layer, provided with first conductive vias disposed in the first dielectric layer, and electrically connected to the first electrode pads.

Abstract translation: 具有嵌入其中的半导体芯片的电路板包括：具有相对的第一和第二表面的芯板和通孔; 半导体芯片，其被容纳在所述通孔中并且具有第一有源表面和相对的第二有源表面，其中包括信号焊盘，功率焊盘和接地焊盘的第一电极焊盘设置在所述第一有源表面上; 设置在所述芯板的第一表面和所述半导体芯片的所述第一有源表面上并且被配置为填充所述通孔和所述半导体芯片之间的间隙的第一介电层，以将所述半导体芯片固定在通孔的位置， 孔; 以及第一电路层，设置在第一电介质层中以与第一电介质层齐平，设置有设置在第一介电层中的第一导电通孔，并且电连接到第一电极焊盘。

公开(公告)号：US08294039B2

公开(公告)日：2012-10-23

申请号：US11950816

申请日：2007-12-05

Applicant: Chih-kuang Yang ,  Chieh-lin Hsing

Inventor： Chih-kuang Yang ,  Chieh-lin Hsing

IPC: H05K1/11 ,  H05K3/36

CPC classification number: H05K3/4007 ,  H01L23/498 ,  H01L23/49822 ,  H01L23/49838 ,  H01L2924/0002 ,  H05K3/205 ,  H05K3/243 ,  H05K3/3452 ,  H05K2201/0367 ,  H05K2201/0376 ,  H05K2201/099 ,  Y10T29/49126 ,  Y10T29/49155 ,  H01L2924/00

Abstract: A surface finish structure of multi-layer substrate and manufacturing method thereof. The surface finish structure of the present invention includes a bond pad layer, at least one cover metal layer and a solder mask. The cover metal layer covers the bond pad layer. The solder mask has a hole to expose the cover metal layer. The present invention can form the cover metal layer to cover the bond pad layer and then forms the solder mask. Thereafter, the hole is made to the solder mask at the position of the cover metal layer to expose thereof. Because the bond pad layer is embedded in a dielectric layer of the multi-layer substrate, adhesion intensity between the bond pad layer and the dielectric layer can be enhanced. Meanwhile, contact of the bond pad layer with the solder can be prevented with the cover metal layer.

Abstract translation: 多层基板的表面处理结构及其制造方法。 本发明的表面光洁度结构包括接合焊盘层，至少一个覆盖金属层和焊接掩模。 覆盖金属层覆盖接合焊盘层。 焊接掩模具有用于露出覆盖金属层的孔。 本发明可以形成覆盖金属层以覆盖接合焊盘层，然后形成焊接掩模。 此后，在覆盖金属层的位置处将该孔制成焊料掩模以使其露出。 由于接合焊盘层嵌入在多层基板的电介质层中，所以可以提高接合焊盘层与电介质层之间的粘合强度。 同时，可以通过覆盖金属层来防止接合焊盘层与焊料的接触。

公开(公告)号：US20120256320A1

公开(公告)日：2012-10-11

申请号：US13525779

申请日：2012-06-18

Applicant: Kentaro Kaneko

Inventor： Kentaro Kaneko

IPC: H05K1/11 ,  H01L23/48

CPC classification number: H01L21/486 ,  H01L21/4857 ,  H01L21/6835 ,  H01L24/16 ,  H01L24/81 ,  H01L2221/68345 ,  H01L2224/13099 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/48227 ,  H01L2224/81801 ,  H01L2224/85444 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01088 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/351 ,  H05K1/113 ,  H05K3/108 ,  H05K3/205 ,  H05K3/382 ,  H05K3/423 ,  H05K3/4682 ,  H05K2201/0376 ,  H05K2201/09454 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2201/098 ,  Y10T29/49126 ,  Y10T29/49147 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2924/00

Abstract: A semiconductor device 100 has such a structure that a semiconductor chip 110 is flip-chip mounted on a wiring board 120. The wiring board 120 has a multilayer structure in which a plurality of wiring layers and a plurality of insulating layers are arranged, and a first electrode pad 130 is formed on a chip mounting side. A taper surface 132 of the first electrode pad 130 has a gradient in an orientation reduced in an upward direction toward a solder connecting side or a chip mounting side. Therefore, a holding force for a force applied to the solder connecting side or the chip mounting side is increased, and furthermore, the taper surface 132 adheres to a tapered internal wall of an insulating layer of a first layer so that a bonding strength to the insulating layer is increased.

Abstract translation: 半导体器件100具有半导体芯片110倒装芯片安装在布线板120上的结构。布线板120具有布置多个布线层和多​​个绝缘层的多层结构，并且 第一电极焊盘130形成在芯片安装侧。 第一电极焊盘130的锥形表面132具有沿向上朝向焊接连接侧或芯片安装侧减小的取向的梯度。 因此，施加到焊料连接侧或芯片安装侧的力的保持力增大，此外，锥形表面132粘附到第一层的绝缘层的锥形内壁，使得与 绝缘层增加。

公开(公告)号：US20120255769A1

公开(公告)日：2012-10-11

申请号：US13527040

申请日：2012-06-19

Applicant: Hee-Bum SHIN ,  Jeong-Ho MOON ,  Jae-Hyun EOM ,  Jee-Soo MOK

Inventor： Hee-Bum SHIN ,  Jeong-Ho MOON ,  Jae-Hyun EOM ,  Jee-Soo MOK

IPC: H05K1/02

CPC classification number: H05K3/107 ,  H05K3/0023 ,  H05K3/045 ,  H05K3/423 ,  H05K3/426 ,  H05K2201/0376 ,  H05K2201/09563 ,  H05K2203/0353 ,  Y10T29/49126 ,  Y10T29/49165

Abstract: A printed circuit board including: a first insulation layer; a second insulation layer stacked over the first insulation layer; a circuit pattern and a via land buried in the second insulation layer; and a via penetrating the first insulation layer and integrated with the via land, the via made of a conductive material.

Abstract translation: 一种印刷电路板，包括：第一绝缘层; 层叠在所述第一绝缘层上的第二绝缘层; 电路图案和掩埋在第二绝缘层中的通孔焊盘; 以及穿过第一绝缘层并且与通孔焊盘一体化的通孔，由导电材料制成的通孔。

公开(公告)号：US20120111609A1

公开(公告)日：2012-05-10

申请号：US13354446

申请日：2012-01-20

Applicant: Seok Hwan AHN ,  Young Gwan Ko

Inventor： Seok Hwan AHN ,  Young Gwan Ko

IPC: H05K1/03

CPC classification number: H05K3/107 ,  H05K3/0032 ,  H05K3/045 ,  H05K3/426 ,  H05K2201/0376 ,  H05K2201/0959 ,  H05K2203/025 ,  H05K2203/1461

Abstract: A printed circuit board having a plating pattern buried in a via. The printed circuit board has: an insulating substrate including an electrically insulating resin; a via hole passing through the insulating substrate; a via including a metal layer formed on an inner wall of the via hole and a filler charged in the via hole; a circuit layer including a circuit pattern buried in the insulating substrate and transmitting an electrical signal; and a plating pattern buried in an end of the filler.

Abstract translation: 具有掩埋在通孔中的电镀图案的印刷电路板。 印刷电路板具有：包含电绝缘树脂的绝缘基板; 穿过所述绝缘基板的通孔; 通孔，其包括形成在所述通孔的内壁上的金属层和填充在所述通孔中的填充物; 电路层，其包括埋在所述绝缘基板中并传输电信号的电路图案; 以及埋在填料末端的电镀图案。

公开(公告)号：US08138423B2

公开(公告)日：2012-03-20

申请号：US11719803

申请日：2005-11-18

Applicant: Mitsuhiro Watanabe ,  Kinji Saijo ,  Shinji Ohsawa ,  Kazuo Yoshida ,  Koji Nanbu

Inventor： Mitsuhiro Watanabe ,  Kinji Saijo ,  Shinji Ohsawa ,  Kazuo Yoshida ,  Koji Nanbu

IPC: H05K1/03

CPC classification number: H05K3/427 ,  H05K1/0265 ,  H05K1/116 ,  H05K3/062 ,  H05K3/20 ,  H05K3/4658 ,  H05K2201/0352 ,  H05K2201/0355 ,  H05K2201/0361 ,  H05K2201/0376 ,  H05K2201/09509 ,  H05K2201/09736 ,  H05K2203/0361 ,  H05K2203/0384 ,  H05K2203/1476 ,  Y10T156/10

Abstract: A printed wiring board and a method for manufacturing the printed wiring board in which widths of a first and a second circuit are close to each other and substantial miniaturization can be achieved. In order to achieve this object, a first circuit and a second circuit having different thicknesses are formed in the same reference plane by etching a metal-clad laminate including a conductive layer and an insulating layer. The thicker of the circuits has a clad-like configuration in which three layers, a first copper layer/a different kind of metal layer/a second copper layer, are sequentially stacked. The manufacture of the printed wiring board includes a clad composite material in which three layers of a first copper layer/a different kind of metal layer/a second copper layer are sequentially stacked as a start material, and selective etching characteristics between the layers are utilized.

Abstract translation: 一种印刷电路板和用于制造印刷电路板的方法，其中第一和第二电路的宽度彼此接近并且可以实现实质的小型化。 为了实现该目的，通过蚀刻包括导电层和绝缘层的覆金属层压体，在相同的参考平面中形成具有不同厚度的第一电路和第二电路。 较厚的电路具有包层状构造，其中依次层叠有三层，第一铜层/不同种类的金属层/第二铜层。 印刷电路板的制造包括其中依次层叠有三层第一铜层/不同种类的金属层/第二铜层作为起始材料的覆层复合材料，并且利用层之间的选择性蚀刻特性 。

公开(公告)号：US08080741B2

公开(公告)日：2011-12-20

申请号：US12149522

申请日：2008-05-02

Applicant: Myung Sam Kang ,  Chin Kwan Kim

Inventor： Myung Sam Kang ,  Chin Kwan Kim

IPC: H05K1/11

CPC classification number: H05K3/4007 ,  H05K3/246 ,  H05K3/3457 ,  H05K3/4069 ,  H05K2201/0347 ,  H05K2201/0367 ,  H05K2201/0376 ,  H05K2201/09481 ,  H05K2201/09745

Abstract: A printed circuit board, which increases the contact area between an IC and a printed circuit board, thus increasing the degree of adhesion, is disclosed. The printed circuit board includes: an insulation layer which includes a first circuit pattern, including at least one via land, embedded in the upper surface of the insulation layer to be flush with the upper surface, and a second circuit pattern formed in the lower surface of the insulation layer to be flush with the lower surface; a solder resist layer formed on the insulation layer; a via hole and a bump integrally formed on the second circuit pattern through the via hole and the via land such that it protrudes from the insulation layer to be higher than the solder resist layer.

Abstract translation: 公开了一种印刷电路板，其增加了IC和印刷电路板之间的接触面积，从而增加了粘合度。 印刷电路板包括：绝缘层，其包括嵌入在绝缘层的上表面中以与上表面齐平的至少一个通孔焊盘的第一电路图案，以及形成在下表面中的第二电路图案 的绝缘层与下表面齐平; 形成在绝缘层上的阻焊层; 通孔和通过通孔和通孔焊盘一体地形成在第二电路图案上的突起，使得其从绝缘层突出成高于阻焊层。

公开(公告)号：US20110303636A1

公开(公告)日：2011-12-15

申请号：US13137505

申请日：2011-08-22

Applicant: Jin-Yong Ahn ,  Chang-Sup Ryu ,  Byung-Youl Min ,  Myung-Sam Kang

Inventor： Jin-Yong Ahn ,  Chang-Sup Ryu ,  Byung-Youl Min ,  Myung-Sam Kang

IPC: H05K3/22

CPC classification number: H05K1/113 ,  H01L23/13 ,  H01L23/49816 ,  H01L2224/16 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H05K3/20 ,  H05K3/4644 ,  H05K2201/0376 ,  H05K2201/09472 ,  H01L2224/0401

Abstract: A method of manufacturing a mounting substrate, the method including: providing an insulation layer, the insulation layer having a circuit pattern formed in one side thereof; forming at least one bonding pad in the other side of the insulation layer, the bonding pad electrically connected with the circuit pattern; and etching the bonding pad such that a surface of the bonding pad is recessed from a surface of the insulation layer by a predetermined depth.

Abstract translation: 一种安装基板的制造方法，所述方法包括：提供绝缘层，所述绝缘层具有形成在其一侧的电路图案; 在所述绝缘层的另一侧形成至少一个焊盘，所述焊盘与所述电路图案电连接; 以及蚀刻所述焊盘，使得所述焊盘的表面从所述绝缘层的表面凹陷预定深度。

公开(公告)号：US20110286189A1

公开(公告)日：2011-11-24

申请号：US13196129

申请日：2011-08-02

Applicant: Junichi Nakamura ,  Yuji Kobayashi

Inventor： Junichi Nakamura ,  Yuji Kobayashi

IPC: H05K1/18 ,  H05K1/11

CPC classification number: H05K1/115 ,  H01L21/4857 ,  H01L21/563 ,  H01L21/6835 ,  H01L23/49816 ,  H01L24/16 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/97 ,  H01L2221/68345 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/81001 ,  H01L2224/81192 ,  H01L2224/81801 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/15311 ,  H05K1/116 ,  H05K3/205 ,  H05K3/28 ,  H05K3/3473 ,  H05K3/4007 ,  H05K3/421 ,  H05K3/423 ,  H05K3/4644 ,  H05K2201/0376 ,  H05K2201/09481 ,  H05K2201/0949 ,  H05K2201/09509 ,  H05K2203/0338 ,  H05K2203/0361 ,  H05K2203/1536 ,  Y10T29/49126 ,  Y10T29/49144 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A method of fabricating a wiring board includes forming a resist layer, such as a solder or plating resist layer, defining an opening portion on a support board such that a portion of the support board is exposed. An electrode is formed directly on the support board within the opening portion, and the plating resist layer, when used, is removed. An insulating layer is formed on the electrode, as well as the support board or solder resist layer, and a wiring portion connected to the electrode at the insulating layer is also formed. A solder resist layer having an opening portion is then formed on the wiring portion, and the support board is removed to expose a surface of the electrode or a surface of the electrode and insulating layer. Another solder resist layer having an opening portion may then be formed on the exposed surface of the insulating layer.

Abstract translation: 制造布线板的方法包括在支撑板上形成限定开口部分的焊料或电镀抗蚀剂层的抗蚀剂层，使得支撑板的一部分露出。 电极直接形成在开口部内的支撑板上，当使用时，电镀抗蚀剂层被去除。 在电极以及支撑板或阻焊层上形成绝缘层，并且还形成连接到绝缘层处的电极的布线部分。 然后在布线部分上形成具有开口部分的阻焊层，并且去除支撑板以暴露电极的表面或电极和绝缘层的表面。 然后可以在绝缘层的暴露表面上形成具有开口部分的另一阻焊层。

公开(公告)号：US07972460B2

公开(公告)日：2011-07-05

申请号：US12408366

申请日：2009-03-20

Applicant: Myung-Sam Kang ,  Jung-Hyun Park ,  Jeong-Woo Park ,  Ji-Eun Kim

Inventor： Myung-Sam Kang ,  Jung-Hyun Park ,  Jeong-Woo Park ,  Ji-Eun Kim

IPC: B32B37/02 ,  H05K1/02 ,  H01L21/70

CPC classification number: B32B38/04 ,  B32B38/10 ,  B32B2038/0092 ,  B32B2038/047 ,  B32B2309/105 ,  B32B2310/0843 ,  B32B2457/08 ,  H05K3/0035 ,  H05K3/108 ,  H05K3/421 ,  H05K3/428 ,  H05K3/4652 ,  H05K2201/0376 ,  H05K2203/0384 ,  H05K2203/0554 ,  Y10T156/1056 ,  Y10T156/1057 ,  Y10T156/1064 ,  Y10T156/1082

Abstract: Disclosed is a method of manufacturing a printed circuit board. The method of manufacturing a printed circuit board having a via for connecting one layer to another layer can include forming a circuit pattern on one surface of a carrier; processing a hole corresponding to the via on one surface of the carrier; compressing the surface of the carrier into one surface of an insulation body; removing the carrier; processing a via hole on the insulation body, corresponding to a position of the hole; and forming a conductive material in the via hole, to thereby easily process a hole for forming a via and have high design freedom.

Abstract translation: 公开了印刷电路板的制造方法。 制造具有用于将一层连接到另一层的通路的印刷电路板的制造方法可以包括在载体的一个表面上形成电路图案; 在载体的一个表面上处理与通孔对应的孔; 将载体的表面压缩到绝缘体的一个表面中; 移除载体; 处理绝缘体上的通孔，对应于孔的位置; 并且在通孔中形成导电材料，从而容易地加工用于形成通孔的孔，并具有高的设计自由度。